专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US08404626B2 Post-deposition cleaning methods and formulations for substrates with cap layers 有权
标题翻译：具有盖层的基底的后沉积清洗方法和配方
公开(公告)号：US08404626B2
公开(公告)日：2013-03-26
申请号：US12334462
申请日：2008-12-13
申请人： Artur Kolics , Shijian Li , Tiruchirapalli Arunagiri , William Thie
发明人： Artur Kolics , Shijian Li , Tiruchirapalli Arunagiri , William Thie
IPC分类号： C11D3/26 , C11D3/20 , C11D3/43 , C09K13/00
CPC分类号： H05K3/0085 , C11D7/3209 , C11D11/0047 , H01L21/02068 , H01L21/76849 , H01L21/76861
摘要： One embodiment of the present invention is a method of fabricating an integrated circuit. The method includes providing a substrate having a metal and dielectric damascene metallization layer and depositing substantially on the metal a cap. After deposition of the cap, the substrate is cleaned with a solution comprising an amine to provide a pH for the cleaning solution of 7 to about 13. Another embodiment of the presented invention is a method of cleaning substrates. Still another embodiment of the present invention is a formulation for a cleaning solution.
摘要翻译：本发明的一个实施例是一种制造集成电路的方法。该方法包括提供具有金属和电介质镶嵌金属化层并且基本上在金属上沉积盖的基板。在沉积盖之后，用包含胺的溶液清洗基底以提供7至约13的清洁溶液的pH。本发明的另一个实施方案是清洁基底的方法。本发明的另一个实施方案是用于清洁溶液的制剂。

2. 发明申请

US20120205807A1 DEVICE WITH POST-CONTACT BACK END OF LINE THROUGH-HOLE VIA INTEGRATION 有权
标题翻译：具有通过一体化的线接触后端的装置
公开(公告)号：US20120205807A1
公开(公告)日：2012-08-16
申请号：US13455453
申请日：2012-04-25
申请人： John Boyd , Fritz Redeker , Yezdi Dordi , Hyungsuk Alexander Yoon , Shijian Li
发明人： John Boyd , Fritz Redeker , Yezdi Dordi , Hyungsuk Alexander Yoon , Shijian Li
IPC分类号： H01L23/48
CPC分类号： H01L23/48 , H01L21/4763 , H01L21/76898 , H01L2924/14
摘要： Presented are device structures and methods of fabricating three-dimensional integrated circuits that include post-contact back end of line through-hole via integration for the three-dimensional integrated circuits. Another aspect of the present invention includes three-dimensional integrated circuits fabricated according to methods of the present invention.
摘要翻译：提出了三维集成电路的器件结构和方法，该三维集成电路包括用于三维集成电路的集成的线通孔的后接后端。本发明的另一方面包括根据本发明的方法制造的三维集成电路。

3. 发明授权

US08168519B2 Plasma immersion ion implantation method using a pure or nearly pure silicon seasoning layer on the chamber interior surfaces 有权
标题翻译：等离子体浸没离子注入方法，在室内表面上使用纯的或接近纯的硅调味层
公开(公告)号：US08168519B2
公开(公告)日：2012-05-01
申请号：US13101843
申请日：2011-05-05
申请人： Shijian Li , Kartik Ramaswamy , Hiroji Hanawa , Seon-Mee Cho , Biagio Gallo , Dongwon Choi , Majeed A. Foad
发明人： Shijian Li , Kartik Ramaswamy , Hiroji Hanawa , Seon-Mee Cho , Biagio Gallo , Dongwon Choi , Majeed A. Foad
IPC分类号： H01L21/425
CPC分类号： H01J37/32412 , C23C14/48 , C23C14/564 , H01L21/2236
摘要： Plasma immersion ion implantation employing a very high RF bias voltage on an electrostatic chuck to attain a requisite implant depth profile is carried out by first depositing a partially conductive silicon-containing seasoning layer over the interior chamber surfaces prior to wafer introduction.
摘要翻译：在静电卡盘上采用非常高的RF偏置电压以获得必要的植入深度分布的等离子体浸没离子注入是通过在晶片引入之前首先在内部腔室表面上沉积部分导电的含硅调节层来进行的。

4. 发明申请

US20080315418A1 Methods of post-contact back end of line through-hole via integration 有权
标题翻译：通过一体化的后通孔后端的方法
公开(公告)号：US20080315418A1
公开(公告)日：2008-12-25
申请号：US11820811
申请日：2007-06-20
申请人： John Boyd , Fritz Redeker , Yezdi Dordi , Hyungsuk Alexander Yoon , Shijian Li
发明人： John Boyd , Fritz Redeker , Yezdi Dordi , Hyungsuk Alexander Yoon , Shijian Li
IPC分类号： H01L21/4763 , H01L23/48
CPC分类号： H01L23/48 , H01L21/4763 , H01L21/76898 , H01L2924/14
摘要： Presented are methods of fabricating three-dimensional integrated circuits that include post-contact back end of line through-hole via integration for the three-dimensional integrated circuits. In one embodiment, the method comprises forming metal plug contacts through a hard mask and a premetal dielectric to transistors in the semiconductor. The method also includes etching a hole for a through-hole via through the hard mask to the semiconductor using a patterned photoresist process, removing the patterned photoresist and using a hard mask process to etch the hole to an amount into the semiconductor. The method further includes depositing a dielectric liner to isolate the hole from the semiconductor, depositing a gapfill metal to fill the hole, and planarizing the surface of the substrate to the hard mask. Another aspect of the present invention includes three-dimensional integrated circuits fabricated according to methods of the present invention.
摘要翻译：提出了制造三维集成电路的方法，其包括用于三维集成电路的集成的线路通孔的后接触后端。在一个实施例中，该方法包括通过硬掩模和前金属电介质形成金属插头触点到半导体中的晶体管。该方法还包括使用图案化的光致抗蚀剂工艺将用于通孔的通孔穿过硬掩模蚀刻到半导体，去除图案化的光致抗蚀剂并使用硬掩模工艺将孔蚀刻到半导体中的量。所述方法还包括沉积介电衬垫以将所述孔与所述半导体隔离，沉积间隙填充金属以填充所述孔，以及将所述衬底的表面平面化至所述硬掩模。本发明的另一方面包括根据本发明的方法制造的三维集成电路。

5. 发明申请

US20080152464A1 METHODS, APPARATUSES, AND SYSTEMS FOR FABRICATING THREE DIMENSIONAL INTEGRATED CIRCUITS 有权
标题翻译：制造三维集成电路的方法，装置和系统
公开(公告)号：US20080152464A1
公开(公告)日：2008-06-26
申请号：US11958025
申请日：2007-12-17
申请人： Shijian LI , Fritz Redeker , Yezdi Dordi
发明人： Shijian LI , Fritz Redeker , Yezdi Dordi
IPC分类号： H01L21/677 , B25B5/00
CPC分类号： H01L21/70 , C23C16/045 , C23C16/4586 , H01L21/67017 , H01L21/677 , H01L21/6838 , H01L21/68714 , H01L21/76898 , H01L23/481 , H01L2924/0002 , H01L2924/12044 , Y10T24/44 , H01L2924/00012 , H01L2924/00
摘要： The present invention pertains to methods, apparatuses, and systems for fabricating three-dimensional integrated circuits. One embodiment of the method comprises providing a wafer or other substrate having a plurality of through holes. In addition, the method includes supporting the wafer or other substrate with a wafer or other substrate holder mounted in a process chamber. The method further includes generating a pressure differential between the front side of the wafer or other substrate and the back side of the wafer or other substrate while the wafer or other substrate is supported on the wafer or other substrate holder so that the pressure differential causes fluid flow through the through holes. Also, the method includes establishing process conditions in the process chamber for at least one process to fabricate integrated circuits. Embodiments of a system and embodiments of an apparatus according to the present invention are also presented.
摘要翻译：本发明涉及用于制造三维集成电路的方法，装置和系统。该方法的一个实施例包括提供具有多个通孔的晶片或其它基板。此外，该方法包括用安装在处理室中的晶片或其它衬底保持器来支撑晶片或其它衬底。该方法还包括在晶片或其它基板被支撑在晶片或其它基板保持器上的同时，在晶片或其它基板的前侧与晶片或其它基板的背面之间产生压差，使得压力差导致流体流过通孔。此外，该方法包括在处理室中建立用于制造集成电路的至少一个工艺的工艺条件。还提供了根据本发明的系统和实施例的装置的实施例。

6. 发明申请

US20080045021A1 DUAL REDUCED AGENTS FOR BARRIER REMOVAL IN CHEMICAL MECHANICAL POLISHING 审中-公开
标题翻译：用于化学机械抛光中的障碍物去除的双重还原剂
公开(公告)号：US20080045021A1
公开(公告)日：2008-02-21
申请号：US11923276
申请日：2007-10-24
申请人： Stan Tsai , Shijian Li , Feng Liu , Lizhong Sun , Liang-Yuh Chen
发明人： Stan Tsai , Shijian Li , Feng Liu , Lizhong Sun , Liang-Yuh Chen
IPC分类号： H01L21/461
CPC分类号： B24B37/0056 , B24B37/044 , C09G1/02 , C09K3/1463 , H01L21/3212
摘要： Compositions and methods for removal of barrier layer materials by a chemical mechanical polishing technique are provided. In one aspect, the invention provides a composition adapted for removing a barrier layer material in a chemical mechanical polishing technique including at least one reducing agent selected from the group of bicarboxylic acids, tricarboxylic acids, and combinations thereof, at least one reducing agent selected from the group of glucose, hydroxylamine, and combinations thereof, and deionized water, wherein the composition has a pH of about 7 or less. The composition may be used in a method for removing the barrier layer material including applying the composition to a polishing pad and polishing the substrate in the presence of the composition to remove the barrier layer.
摘要翻译：提供了通过化学机械抛光技术去除阻挡层材料的组合物和方法。一方面，本发明提供一种组合物，其适于在化学机械抛光技术中除去阻挡层材料，该技术包括至少一种选自二羧酸，三羧酸及其组合的还原剂，至少一种还原剂，其选自该组葡萄糖，羟胺及其组合以及去离子水，其中所述组合物具有约7或更低的pH。组合物可以用于除去阻挡层材料的方法，包括将组合物施加到抛光垫上，并在组合物存在下抛光基底以除去阻挡层。

7. 发明授权

US07232761B2 Method of chemical mechanical polishing with high throughput and low dishing 失效
标题翻译：化学机械抛光方法，具有高通量和低凹陷
公开(公告)号：US07232761B2
公开(公告)日：2007-06-19
申请号：US10924417
申请日：2004-08-24
申请人： Shijian Li , Jui-Lung Li , Shi-Ping Wang , Gary Lam , David Mai , Fred C. Redeker
发明人： Shijian Li , Jui-Lung Li , Shi-Ping Wang , Gary Lam , David Mai , Fred C. Redeker
IPC分类号： H01L21/461
CPC分类号： H01L21/3212 , B24B37/042 , B24B37/30 , H01L21/7684
摘要： Method and apparatus are provided for polishing conductive materials with low dishing of features and reduced or minimal remaining residues. In one aspect, a method is provided for processing a substrate by polishing the substrate to remove bulk conductive material and polishing the substrate by a ratio of carrier head rotational speed to platen rotational speed of between about 2:1 and about 3:1 to remove residual conductive material. In another aspect, a method is provided for processing a substrate including polishing the substrate at a first relative linear velocity between about 600 mm/second and about 1900 mm/second at the center of the substrate, and polishing the substrate at a second relative linear velocity between about 100 mm/second and about 550 mm/second at the center of the substrate.
摘要翻译：提供了用于抛光导电材料的方法和装置，其具有低的特征凹陷和减少的或最小的剩余残余物。在一个方面，提供了一种通过抛光衬底以去除体导电材料并通过载体头部旋转速度与平板旋转速度的比率在约2:1至约3:1之间来抛光衬底来进行衬底处理的方法，以去除残留导电材料。在另一方面，提供了一种用于处理衬底的方法，包括在衬底的中心以约600mm /秒至约1900mm /秒的第一相对线速度抛光衬底，并以第二相对线性在衬底的中心处的速度在约100mm /秒到约550mm /秒之间。

8. 发明授权

US07220322B1 Cu CMP polishing pad cleaning 失效
标题翻译： Cu CMP抛光垫清洗
公开(公告)号：US07220322B1
公开(公告)日：2007-05-22
申请号：US09645690
申请日：2000-08-24
申请人： Lizhong Sun , Shijian Li , Fred C. Redeker
发明人： Lizhong Sun , Shijian Li , Fred C. Redeker
IPC分类号： B08B7/04 , H01L21/302
CPC分类号： B24B53/017
摘要： A polishing pad is cleaned of Cu CMP by-products, subsequent to planarizing a wafer, to reduce pad-glazing by applying to the polishing pad surface a composition comprising about 0.1 to about 3.0 wt. % of at least one organic compound having one or more amine or amide groups, an acid or a base in an amount sufficient to adjust the pH of the composition to about 5.0 to about 12.0, the remainder water. Embodiments comprise ex situ cleaning of a rotating polishing pad by applying a solution having a pH of about 5.0 to about 12.0 at a flow rate of about 100 to about 600 ml/min. for about 3 to about 20 seconds after polishing a wafer having a Cu-containing surface and then removing the cleaning solution from the polishing pad by high pressure rinsing with water.
摘要翻译：在平坦化晶片之后，将抛光垫清除为Cu CMP副产物，通过向抛光垫表面施加包含约0.1至约3.0重量％的组合物的组合物来减少垫玻璃。％的至少一种具有一个或多个胺或酰胺基团的有机化合物，酸或碱的量足以将组合物的pH调节至约5.0至约12.0，其余为水。实施例包括通过以约100至约600ml / min的流速施加pH为约5.0至约12.0的溶液来旋转抛光垫的原位清洁。在研磨具有含Cu表面的晶片之后约3至约20秒，然后通过用水高压冲洗从抛光垫除去清洁溶液。

9. 发明授权

US06991517B2 Linear polishing sheet with window 失效
公开(公告)号：US06991517B2
公开(公告)日：2006-01-31
申请号：US10814405
申请日：2004-03-31
申请人： Fred C. Redeker , Manoocher Birang , Shijian Li , Sasson Somekh
发明人： Fred C. Redeker , Manoocher Birang , Shijian Li , Sasson Somekh
IPC分类号： B24B1/00
CPC分类号： B24B37/005 , B24B21/04 , B24B49/04 , B24B49/12 , H01L21/30625
摘要： A polishing article for chemical mechanical polishing. The polishing article includes a generally elongated polishing sheet with a polishing surface. The polishing article is formed from a material that is substantially opaque, and has a discrete region extending substantially the length of the polishing sheet that is at least semi-transparent.

10. 发明申请

US20050282380A1 METHOD AND APPARATUS FOR CHEMICAL MECHANICAL POLISHING OF SEMICONDUCTOR SUBSTRATES 失效
标题翻译：半导体基板的化学机械抛光方法与装置
公开(公告)号：US20050282380A1
公开(公告)日：2005-12-22
申请号：US10972191
申请日：2004-10-22
申请人： Stan Tsai , Liang-Yuh Chen , Lizhong Sun , Shijian Li , Feng Liu , Rashid Mavliev , Ratson Morad , Daniel Carl
发明人： Stan Tsai , Liang-Yuh Chen , Lizhong Sun , Shijian Li , Feng Liu , Rashid Mavliev , Ratson Morad , Daniel Carl
IPC分类号： B24B37/04 , B24B49/16 , H01L21/321 , H01L21/768 , H01L21/00 , B24B49/00 , B24B51/00 , H01L21/4763
CPC分类号： H01L21/7684 , B24B37/042 , B24B49/16 , H01L21/3212 , Y02P80/30
摘要： Methods and apparatus for processing substrates to improve polishing uniformity, improve planarization, remove residual material and minimize defect formation are provided. In one aspect, a method is provided for processing a substrate having a conductive material and a low dielectric constant material disposed thereon including polishing a substrate at a polishing pressures of about 2 psi or less and at platen rotational speeds of about 200 cps or greater. The polishing process may use an abrasive-containing polishing composition having up to about 1 wt. % of abrasives. The polishing process may be integrated into a multi-step polishing process.
摘要翻译：提供了用于处理基板以改善抛光均匀性，改善平面化，去除残留材料并最小化缺陷形成的方法和装置。在一个方面，提供了一种用于处理具有导电材料和设置在其上的低介电常数材料的衬底的方法，其包括在约2psi或更小的抛光压力和约200cps或更高的压板旋转速度下抛光衬底。抛光工艺可以使用含有至多约1重量％的磨料的抛光组合物。磨料的百分比。抛光工艺可以集成到多步抛光工艺中。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式