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1. 发明授权

US09299852B2 Semiconductor device and method for manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US09299852B2
公开(公告)日：2016-03-29
申请号：US13483078
申请日：2012-05-30
申请人： Kyoko Yoshioka , Junichi Koezuka , Shinji Ohno , Yuichi Sato , Shinya Sasagawa
发明人： Kyoko Yoshioka , Junichi Koezuka , Shinji Ohno , Yuichi Sato , Shinya Sasagawa
IPC分类号： H01L21/00 , H01L29/786 , H01L21/324 , H01L29/66
CPC分类号： H01L29/7869 , H01L21/324 , H01L29/66969
摘要： A miniaturized semiconductor device in which an increase in power consumption is suppressed and a method for manufacturing the semiconductor device are provided. A highly reliable semiconductor device having stable electric characteristics and a method for manufacturing the semiconductor device are provided. An oxide semiconductor film is irradiated with ions accelerated by an electric field in order to reduce the average surface roughness of a surface of the oxide semiconductor film. Consequently, an increase in the leakage current and power consumption of a transistor can be suppressed. Moreover, by performing heat treatment so that the oxide semiconductor film includes a crystal having a c-axis substantially perpendicular to the surface of the oxide semiconductor film, a change in electric characteristics of the oxide semiconductor film due to irradiation with visible light or ultraviolet light can be suppressed.
摘要翻译：提供抑制功耗增加的小型化半导体装置及其制造方法。提供了一种具有稳定电特性的高度可靠的半导体器件及其半导体器件的制造方法。为了降低氧化物半导体膜的表面的平均表面粗糙度，用电场加速的离子照射氧化物半导体膜。因此，可以抑制晶体管的漏电流和功耗的增加。此外，通过进行热处理使得氧化物半导体膜包括具有与氧化物半导体膜的表面基本垂直的c轴的晶体，由于可见光或紫外线的照射而导致的氧化物半导体膜的电特性的变化可以抑制。

2. 发明授权

US08809992B2 Semiconductor device and manufacturing method thereof 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08809992B2
公开(公告)日：2014-08-19
申请号：US13356012
申请日：2012-01-23
申请人： Shunpei Yamazaki , Atsuo Isobe , Toshihiko Saito , Takehisa Hatano , Hideomi Suzawa , Shinya Sasagawa , Junichi Koezuka , Yuichi Sato , Shinji Ohno
发明人： Shunpei Yamazaki , Atsuo Isobe , Toshihiko Saito , Takehisa Hatano , Hideomi Suzawa , Shinya Sasagawa , Junichi Koezuka , Yuichi Sato , Shinji Ohno
IPC分类号： H01L29/786
CPC分类号： H01L29/66969 , H01L21/02488 , H01L21/02565 , H01L27/1225 , H01L29/786 , H01L29/78606 , H01L29/7869
摘要： A semiconductor device which includes an oxide semiconductor and has favorable electrical characteristics is provided. In the semiconductor device, an oxide semiconductor film and an insulating film are formed over a substrate. Side surfaces of the oxide semiconductor film are in contact with the insulating film. The oxide semiconductor film includes a channel formation region and regions containing a dopant between which the channel formation region is sandwiched. A gate insulating film is formed on and in contact with the oxide semiconductor film. A gate electrode with sidewall insulating films is formed over the gate insulating film. A source electrode and a drain electrode are formed in contact with the oxide semiconductor film and the insulating film.
摘要翻译：提供了包括氧化物半导体并且具有良好的电特性的半导体器件。在半导体器件中，在衬底上形成氧化物半导体膜和绝缘膜。氧化物半导体膜的侧面与绝缘膜接触。氧化物半导体膜包括沟道形成区域和包含掺杂剂的区域，沟道形成区域夹在其间。栅极绝缘膜与氧化物半导体膜形成并接触。在栅绝缘膜上形成具有侧壁绝缘膜的栅电极。源电极和漏电极形成为与氧化物半导体膜和绝缘膜接触。

3. 发明授权

US09431545B2 Semiconductor device and method for manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US09431545B2
公开(公告)日：2016-08-30
申请号：US13604962
申请日：2012-09-06
申请人： Toshihiko Saito , Atsuo Isobe , Kazuya Hanaoka , Junichi Koezuka , Shinya Sasagawa , Motomu Kurata , Akihiro Ishizuka
发明人： Toshihiko Saito , Atsuo Isobe , Kazuya Hanaoka , Junichi Koezuka , Shinya Sasagawa , Motomu Kurata , Akihiro Ishizuka
IPC分类号： H01L29/786 , H01L21/28 , H01L27/12
CPC分类号： H01L29/7869 , H01L27/1225
摘要： A miniaturized transistor having high electric characteristics is provided with high yield. In a semiconductor device including the transistor, high performance, high reliability, and high productivity are achieved. In a semiconductor device including a transistor in which an oxide semiconductor film, a gate insulating film, and a gate electrode layer on side surfaces of which sidewall insulating layers are provided are stacked in this order, source and drain electrode layers are provided in contact with the oxide semiconductor film and the sidewall insulating layers. In a process for manufacturing the semiconductor device, a conductive film and an interlayer insulating film are stacked to cover the oxide semiconductor film, the sidewall insulating layers, and the gate electrode layer, and the interlayer insulating film and the conductive film over the gate electrode layer are removed by a chemical mechanical polishing method, so that the source and drain electrode layers are formed.
摘要翻译：提供具有高电特性的小型化晶体管，其产率高。在包括晶体管的半导体器件中，实现了高性能，高可靠性和高生产率。在包括晶体管的半导体器件中，依次堆叠其中设置有侧壁绝缘层的侧表面上的氧化物半导体膜，栅极绝缘膜和栅极电极层的晶体管，源极和漏极电极层被设置为与氧化物半导体膜和侧壁绝缘层。在制造半导体器件的过程中，层叠导电膜和层间绝缘膜以覆盖氧化物半导体膜，侧壁绝缘层和栅极电极层，以及栅极上的层间绝缘膜和导电膜通过化学机械抛光方法去除层，从而形成源极和漏极电极层。

4. 发明授权

US08436403B2 Semiconductor device including transistor provided with sidewall and electronic appliance 有权
标题翻译：包括设置有侧壁和电子设备的晶体管的半导体器件
公开(公告)号：US08436403B2
公开(公告)日：2013-05-07
申请号：US13014081
申请日：2011-01-26
申请人： Shunpei Yamazaki , Hiromichi Godo , Hideomi Suzawa , Shinya Sasagawa , Motomu Kurata , Mayumi Mikami
发明人： Shunpei Yamazaki , Hiromichi Godo , Hideomi Suzawa , Shinya Sasagawa , Motomu Kurata , Mayumi Mikami
IPC分类号： H01L21/84
CPC分类号： H01L29/7869 , H01L29/41733 , H01L29/45 , H01L29/66969 , Y10T428/24421
摘要： One object is to provide a semiconductor device that includes an oxide semiconductor and is reduced in size with favorable characteristics maintained. The semiconductor device includes an oxide semiconductor layer, a source electrode and a drain electrode in contact with the oxide semiconductor layer, a gate electrode overlapping with the oxide semiconductor layer; and a gate insulating layer between the oxide semiconductor layer and the gate electrode. The source electrode or the drain electrode includes a first conductive layer and a second conductive layer having a region extended in a channel length direction from an end face of the first conductive layer. The sidewall insulating layer has a length of a bottom surface in the channel length direction smaller than a length in the channel length direction of the extended region of the second conductive layer and is provided over the extended region.
摘要翻译：一个目的是提供一种包括氧化物半导体的半导体器件，并且尺寸减小，并保持良好的特性。半导体器件包括与氧化物半导体层接触的氧化物半导体层，源电极和漏电极，与氧化物半导体层重叠的栅电极; 以及在氧化物半导体层和栅电极之间的栅极绝缘层。源电极或漏极包括第一导电层和具有从第一导电层的端面在沟道长度方向上延伸的区域的第二导电层。侧壁绝缘层的沟道长度方向的底面的长度小于第二导电层的延伸区域的沟道长度方向的长度，并且设置在延伸区域上。

5. 发明授权

US08349671B2 Methods for manufacturing thin film transistor and display device 有权
公开(公告)号：US08349671B2
公开(公告)日：2013-01-08
申请号：US12230048
申请日：2008-08-22
申请人： Hidekazu Miyairi , Shinya Sasagawa , Akihiro Ishizuka
发明人： Hidekazu Miyairi , Shinya Sasagawa , Akihiro Ishizuka
IPC分类号： H01L21/336
CPC分类号： H01L29/6675 , H01L29/04 , H01L29/66765 , H01L29/78696 , H01L33/0058 , H01L2924/0002 , H01L2924/00
摘要： The present invention provides a method for manufacturing a highly reliable semiconductor device with a small amount of leakage current. In a method for manufacturing a thin film transistor, etching is conducted using a resist mask to form a back channel portion in the thin film transistor, the resist mask is removed, a part of the back channel is etched to remove etching residue and the like left over the back channel portion, whereby leakage current caused by the residue and the like can be reduced. The etching step of the back channel portion can be conducted by dry etching using non-bias.

6. 发明授权

US08236635B2 Method for manufacturing semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US08236635B2
公开(公告)日：2012-08-07
申请号：US12582074
申请日：2009-10-20
申请人： Hideomi Suzawa , Shinya Sasagawa , Taiga Muraoka
发明人： Hideomi Suzawa , Shinya Sasagawa , Taiga Muraoka
IPC分类号： H01L21/00 , H01L21/336 , H01L21/8234 , H01L21/84 , H01L21/20
CPC分类号： H01L27/1288 , H01L27/1214 , H01L27/1225 , H01L29/7869
摘要： In a method for manufacturing a semiconductor device including a channel-etched inverted-staggered thin film transistor, an oxide semiconductor film and a conductive film are etched using a mask layer formed with the use of a multi-tone mask which is a light-exposure mask through which light is transmitted so as to have a plurality of intensities. The etching step is performed by dry etching in which an etching gas is used.
摘要翻译：在制造包括通道蚀刻反交错薄膜晶体管的半导体器件的方法中，使用使用作为曝光的多色调掩模形成的掩模层来蚀刻氧化物半导体膜和导电膜光透过该掩模以具有多个强度。蚀刻步骤通过使用蚀刻气体的干蚀刻进行。

7. 发明授权

US08207025B2 Manufacturing method of semiconductor device 有权
标题翻译：半导体器件的制造方法
公开(公告)号：US08207025B2
公开(公告)日：2012-06-26
申请号：US13078020
申请日：2011-04-01
申请人： Hideomi Suzawa , Shinya Sasagawa
发明人： Hideomi Suzawa , Shinya Sasagawa
IPC分类号： H01L21/336
CPC分类号： H01L29/78636 , G11C16/0433 , H01L27/0688 , H01L27/11521 , H01L27/11551 , H01L27/1156 , H01L27/1214 , H01L27/1225 , H01L27/1288 , H01L29/66969 , H01L29/7869
摘要： In an embodiment, an insulating film is formed over a flat surface; a mask is formed over the insulating film; a slimming process is performed on the mask; an etching process is performed on the insulating film using the mask; a conductive film covering the insulating film is formed; a polishing process is performed on the conductive film and the insulating film, so that the conductive film and the insulating film have equal thicknesses; the conductive film is etched, so that a source electrode and a drain electrode which are thinner than the conductive film are formed; an oxide semiconductor film is formed in contact with the insulating film, the source electrode, and the drain electrode; a gate insulating film covering the oxide semiconductor film is formed; and a gate electrode is formed in a region which is over the gate insulating film and overlaps with the insulating film.
摘要翻译：在一个实施例中，在平坦表面上形成绝缘膜; 在绝缘膜上形成掩模; 在面罩上进行减肥过程; 使用掩模对绝缘膜进行蚀刻处理; 形成覆盖绝缘膜的导电膜; 对导电膜和绝缘膜进行抛光处理，使得导电膜和绝缘膜具有相等的厚度; 蚀刻导电膜，形成比导电膜薄的源电极和漏电极; 形成与绝缘膜，源电极和漏电极接触的氧化物半导体膜; 形成覆盖氧化物半导体膜的栅极绝缘膜; 并且栅电极形成在栅极绝缘膜上并与绝缘膜重叠的区域中。

8. 发明授权

US07998801B2 Manufacturing method of thin film transistor having altered semiconductor layer 有权
标题翻译：具有改变的半导体层的薄膜晶体管的制造方法
公开(公告)号：US07998801B2
公开(公告)日：2011-08-16
申请号：US12424563
申请日：2009-04-16
申请人： Shinya Sasagawa , Motomu Kurata , Sho Osada
发明人： Shinya Sasagawa , Motomu Kurata , Sho Osada
IPC分类号： H01L21/00 , H01L21/302
CPC分类号： H01L27/1288 , H01L27/1214 , H01L29/04 , H01L29/40 , H01L29/41733 , H01L29/66765 , H01L29/78669 , H01L29/78678 , H01L29/78696
摘要： Decrease of the off-state current, increase of the on-state current, and reduction of variations of electrical characteristics. A method for manufacturing a channel-etched inversed staggered thin film transistor includes the following steps: removing, by first dry-etching, a part of a semiconductor layer including an impurity element which imparts one conductivity type, which is exposed from the source and drain electrodes, and partially a part of an amorphous semiconductor layer just below and in contact with the part of the semiconductor layer; removing, by second dry-etching, partially the part of the amorphous semiconductor layer which is exposed by the first dry-etching; and performing plasma treatment on the surface of the part of the amorphous semiconductor layer which is exposed by the second dry-etching so that an altered layer is formed.
摘要翻译：关闭状态电流的减小，导通电流的增加以及电特性变化的减小。用于制造通道蚀刻反向交错薄膜晶体管的方法包括以下步骤：通过首先干蚀刻除去包括从源极和漏极暴露的赋予一种导电类型的杂质元素的半导体层的一部分电极，以及半导体层的正下方并与半导体层的一部分接触的部分非晶半导体层的一部分; 通过第二干法蚀刻部分地除去通过第一干法蚀刻暴露的部分非晶半导体层; 并且通过第二干蚀刻曝光的非晶半导体层的部分的表面进行等离子体处理，从而形成改变的层。

9. 发明授权

US07989351B2 Method for manufacturing a wiring over a substrate 有权
标题翻译：在基板上制造布线的方法
公开(公告)号：US07989351B2
公开(公告)日：2011-08-02
申请号：US12431170
申请日：2009-04-28
申请人： Shinya Sasagawa , Satoru Okamoto , Shigeharu Monoe
发明人： Shinya Sasagawa , Satoru Okamoto , Shigeharu Monoe
IPC分类号： H01L21/302
CPC分类号： H01L27/3276 , G02F2001/13629 , H01L21/32136 , H01L21/32137 , H01L21/32139 , H01L51/0021 , H01L51/0023 , H01L51/5281 , H01L2924/0002 , H05K3/06 , H05K2203/0315 , H05K2203/0346 , H05K2203/095 , H05K2203/1476 , H01L2924/00
摘要： A wiring over a substrate capable of reducing particles between wirings and a method for manufacturing the wiring is disclosed. A wiring over a substrate capable of preventing short-circuiting between wirings due to big difference in projection and depression between wirings and a method for manufacturing the wiring is also disclosed. Further, a wiring over a substrate capable of preventing cracks in the insulating layer due to stress at the edge of a wiring or particles and a method for manufacturing the wiring is also disclosed. According to the present invention, a method for manufacturing a wiring over a substrate is provided that comprises the steps of: forming a first conductive layer over an insulating surface; forming a first mask pattern over the first conductive layer; forming a second mask pattern by etching the first mask pattern under a first condition, simultaneously, forming a second conductive layer having a side having an angle of inclination cross-sectionally by etching the first conductive layer; and forming a third conductive layer and a third mask pattern by etching the second conductive layer and the second mask pattern under a second condition; wherein a selective ratio under the first condition of the first conductive layer to the first mask pattern is in a range of 0.25 to 4, and a selective ratio under the second condition of the second conductive layer to the second mask pattern is larger than that under the first condition.
摘要翻译：公开了一种能够减少布线之间的颗粒的基板上的布线和用于制造布线的方法。还公开了一种能够防止布线之间的大的差异和配线间的凹陷之间的布线之间的短路的布线和布线的制造方法。此外，还公开了能够防止由于布线或颗粒的边缘处的应力导致的绝缘层中的裂纹的基板上的布线以及布线的制造方法。根据本发明，提供了一种用于在衬底上制造布线的方法，包括以下步骤：在绝缘表面上形成第一导电层; 在所述第一导电层上形成第一掩模图案; 通过在第一条件下蚀刻第一掩模图案形成第二掩模图案，同时通过蚀刻第一导电层形成具有横截面为倾斜角的一侧的第二导电层; 以及通过在第二条件下蚀刻所述第二导电层和所述第二掩模图案来形成第三导电层和第三掩模图案; 其中在第一导电层与第一掩模图案的第一条件下的选择比在0.25至4的范围内，并且在第二导电层与第二掩模图案的第二条件下的选择比大于第一个条件。

10. 发明授权

US07968884B2 Semiconductor device and manufacturing method thereof 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US07968884B2
公开(公告)日：2011-06-28
申请号：US11945739
申请日：2007-11-27
申请人： Shunpei Yamazaki , Kazuko Ikeda , Shinya Sasagawa , Hideomi Suzawa
发明人： Shunpei Yamazaki , Kazuko Ikeda , Shinya Sasagawa , Hideomi Suzawa
IPC分类号： H01L29/10 , H01L29/76 , H01L31/036 , H01L31/112
CPC分类号： H01L29/4908 , H01L21/84 , H01L27/1203 , H01L29/66772 , H01L29/78609
摘要： A semiconductor device manufactured utilizing an SOI substrate, in which defects due to an end portion of an island-shaped silicon layer are prevented and the reliability is improved, and a manufacturing method thereof. The following are included: an SOI substrate in which an insulating layer and an island-shaped silicon layer are stacked in order over a support substrate; a gate insulating layer provided over one surface and a side surface of the island-shaped silicon layer; and a gate electrode which is provided over the island-shaped silicon layer with the gate insulating layer interposed therebetween. The gate insulating layer is formed such that the dielectric constant in the region which is in contact with the side surface of the island-shaped silicon layer is lower than that over the one surface of the island-shaped silicon layer.
摘要翻译：利用SOI衬底制造的半导体器件及其制造方法，其中防止了由岛状硅层的端部引起的缺陷并提高了可靠性。包括以下：SOI基板，其中绝缘层和岛状硅层依次层叠在支撑基板上; 设置在岛状硅层的一个表面和侧面上的栅极绝缘层; 以及栅极电极，其设置在岛状硅层上，栅极绝缘层插入其间。栅极绝缘层形成为与岛状硅层的侧面接触的区域的介电常数低于岛状硅层的一个表面的介电常数。

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