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1. 发明授权

US09431545B2 Semiconductor device and method for manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US09431545B2
公开(公告)日：2016-08-30
申请号：US13604962
申请日：2012-09-06
申请人： Toshihiko Saito , Atsuo Isobe , Kazuya Hanaoka , Junichi Koezuka , Shinya Sasagawa , Motomu Kurata , Akihiro Ishizuka
发明人： Toshihiko Saito , Atsuo Isobe , Kazuya Hanaoka , Junichi Koezuka , Shinya Sasagawa , Motomu Kurata , Akihiro Ishizuka
IPC分类号： H01L29/786 , H01L21/28 , H01L27/12
CPC分类号： H01L29/7869 , H01L27/1225
摘要： A miniaturized transistor having high electric characteristics is provided with high yield. In a semiconductor device including the transistor, high performance, high reliability, and high productivity are achieved. In a semiconductor device including a transistor in which an oxide semiconductor film, a gate insulating film, and a gate electrode layer on side surfaces of which sidewall insulating layers are provided are stacked in this order, source and drain electrode layers are provided in contact with the oxide semiconductor film and the sidewall insulating layers. In a process for manufacturing the semiconductor device, a conductive film and an interlayer insulating film are stacked to cover the oxide semiconductor film, the sidewall insulating layers, and the gate electrode layer, and the interlayer insulating film and the conductive film over the gate electrode layer are removed by a chemical mechanical polishing method, so that the source and drain electrode layers are formed.
摘要翻译：提供具有高电特性的小型化晶体管，其产率高。在包括晶体管的半导体器件中，实现了高性能，高可靠性和高生产率。在包括晶体管的半导体器件中，依次堆叠其中设置有侧壁绝缘层的侧表面上的氧化物半导体膜，栅极绝缘膜和栅极电极层的晶体管，源极和漏极电极层被设置为与氧化物半导体膜和侧壁绝缘层。在制造半导体器件的过程中，层叠导电膜和层间绝缘膜以覆盖氧化物半导体膜，侧壁绝缘层和栅极电极层，以及栅极上的层间绝缘膜和导电膜通过化学机械抛光方法去除层，从而形成源极和漏极电极层。

2. 发明授权

US08809992B2 Semiconductor device and manufacturing method thereof 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08809992B2
公开(公告)日：2014-08-19
申请号：US13356012
申请日：2012-01-23
申请人： Shunpei Yamazaki , Atsuo Isobe , Toshihiko Saito , Takehisa Hatano , Hideomi Suzawa , Shinya Sasagawa , Junichi Koezuka , Yuichi Sato , Shinji Ohno
发明人： Shunpei Yamazaki , Atsuo Isobe , Toshihiko Saito , Takehisa Hatano , Hideomi Suzawa , Shinya Sasagawa , Junichi Koezuka , Yuichi Sato , Shinji Ohno
IPC分类号： H01L29/786
CPC分类号： H01L29/66969 , H01L21/02488 , H01L21/02565 , H01L27/1225 , H01L29/786 , H01L29/78606 , H01L29/7869
摘要： A semiconductor device which includes an oxide semiconductor and has favorable electrical characteristics is provided. In the semiconductor device, an oxide semiconductor film and an insulating film are formed over a substrate. Side surfaces of the oxide semiconductor film are in contact with the insulating film. The oxide semiconductor film includes a channel formation region and regions containing a dopant between which the channel formation region is sandwiched. A gate insulating film is formed on and in contact with the oxide semiconductor film. A gate electrode with sidewall insulating films is formed over the gate insulating film. A source electrode and a drain electrode are formed in contact with the oxide semiconductor film and the insulating film.
摘要翻译：提供了包括氧化物半导体并且具有良好的电特性的半导体器件。在半导体器件中，在衬底上形成氧化物半导体膜和绝缘膜。氧化物半导体膜的侧面与绝缘膜接触。氧化物半导体膜包括沟道形成区域和包含掺杂剂的区域，沟道形成区域夹在其间。栅极绝缘膜与氧化物半导体膜形成并接触。在栅绝缘膜上形成具有侧壁绝缘膜的栅电极。源电极和漏电极形成为与氧化物半导体膜和绝缘膜接触。

3. 发明授权

US08575608B2 Thin film transistor and manufacturing method thereof 有权
标题翻译：薄膜晶体管及其制造方法
公开(公告)号：US08575608B2
公开(公告)日：2013-11-05
申请号：US12973123
申请日：2010-12-20
申请人： Shinya Sasagawa , Akihiro Ishizuka , Shinobu Furukawa , Motomu Kurata
发明人： Shinya Sasagawa , Akihiro Ishizuka , Shinobu Furukawa , Motomu Kurata
IPC分类号： H01L29/786
CPC分类号： H01L29/66765 , H01L29/78669 , H01L29/78678 , H01L29/78696
摘要： An embodiment is a thin film transistor which includes a gate electrode layer, a gate insulating layer provided so as to cover the gate electrode layer; a first semiconductor layer entirely overlapped with the gate electrode layer; a second semiconductor layer provided over and in contact with the first semiconductor layer and having a lower carrier mobility than the first semiconductor layer; an impurity semiconductor layer provided in contact with the second semiconductor layer; a sidewall insulating layer provided so as to cover at least a sidewall of the first semiconductor layer; and a source and drain electrode layers provided in contact with at least the impurity semiconductor layer. The second semiconductor layer may consist of parts which are apart from each other over the first semiconductor layer.
摘要翻译：一个实施例是一种薄膜晶体管，其包括栅极电极层，设置为覆盖栅极电极层的栅极绝缘层; 与栅电极层完全重叠的第一半导体层; 第二半导体层，设置在第一半导体层上并与第一半导体层接触，并具有比第一半导体层低的载流子迁移率; 设置成与所述第二半导体层接触的杂质半导体层; 侧壁绝缘层，设置成覆盖所述第一半导体层的至少一个侧壁; 以及设置成与至少杂质半导体层接触的源极和漏极电极层。第二半导体层可以由在第一半导体层上彼此分开的部分组成。

4. 发明授权

US08247308B2 Method for manufacturing SOI substrate 有权
标题翻译：制造SOI衬底的方法
公开(公告)号：US08247308B2
公开(公告)日：2012-08-21
申请号：US12505020
申请日：2009-07-17
申请人： Akihiro Ishizuka , Shinya Sasagawa , Motomu Kurata , Atsushi Hikosaka , Taiga Muraoka , Hitoshi Nakayama
发明人： Akihiro Ishizuka , Shinya Sasagawa , Motomu Kurata , Atsushi Hikosaka , Taiga Muraoka , Hitoshi Nakayama
IPC分类号： H01L21/30
CPC分类号： H01L21/76254
摘要： It is an object of the preset invention to increase adhesiveness of a semiconductor layer and a base substrate and to reduce defective bonding. An oxide film is formed on a semiconductor substrate and the semiconductor substrate is irradiated with accelerated ions through the oxide film, whereby an embrittled region is formed at a predetermined depth from a surface of the semiconductor substrate. Plasma treatment is performed on the oxide film on the semiconductor substrate and the base substrate by applying a bias voltage, the surface of the semiconductor substrate and a surface of the base substrate are disposed opposite to each other, a surface of the oxide film is bonded to the surface of the base substrate, heat treatment is performed after the surface of the oxide film is bonded to the surface of the base substrate, and separation is caused along the embrittled region, whereby a semiconductor layer is formed over the base substrate with the oxide film interposed therebetween.
摘要翻译：本发明的一个目的是增加半导体层和基底衬底的粘附性并减少不良接合。在半导体衬底上形成氧化物膜，半导体衬底通过氧化膜照射加速离子，从而在半导体衬底的表面形成预定深度的脆化区域。通过施加偏置电压对半导体衬底和基底衬底上的氧化物膜进行等离子体处理，半导体衬底的表面和基底衬底的表面彼此相对设置，氧化膜的表面被接合在基底表面上进行热处理之后，在氧化膜的表面接合到基底表面之后进行热处理，沿着脆化区域分离，由此在基底基板上形成半导体层氧化膜。

5. 发明授权

US09006803B2 Semiconductor device and method for manufacturing thereof 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US09006803B2
公开(公告)日：2015-04-14
申请号：US13446028
申请日：2012-04-13
申请人： Atsuo Isobe , Toshinari Sasaki , Shinya Sasagawa , Akihiro Ishizuka
发明人： Atsuo Isobe , Toshinari Sasaki , Shinya Sasagawa , Akihiro Ishizuka
IPC分类号： H01L29/76 , H01L27/06 , H01L27/12 , H01L29/786 , H01L29/423 , H01L29/66 , H01L21/02
CPC分类号： H01L29/66969 , H01L21/02554 , H01L21/02565 , H01L21/02667 , H01L27/0688 , H01L27/1225 , H01L29/42384 , H01L29/78603 , H01L29/78642 , H01L29/7869 , H01L29/78696
摘要： An insulating layer is provided with a projecting structural body, and a channel formation region of an oxide semiconductor layer is provided in contact with the projecting structural body, whereby the channel formation region is extended in a three dimensional direction (a direction perpendicular to a substrate). Thus, it is possible to miniaturize a transistor and to extend an effective channel length of the transistor. Further, an upper end corner portion of the projecting structural body, where a top surface and a side surface of the projecting structural body intersect with each other, is curved, and the oxide semiconductor layer is formed to include a crystal having a c-axis perpendicular to the curved surface.
摘要翻译：绝缘层设置有突出的结构体，并且设置与突出结构体接触的氧化物半导体层的沟道形成区域，由此沟道形成区域沿三维方向（垂直于衬底的方向）延伸）。因此，可以使晶体管小型化并且延长晶体管的有效沟道长度。此外，突出结构体的顶表面和侧表面彼此相交的突出结构体的上端角部弯曲，并且氧化物半导体层形成为包括具有c轴的晶体垂直于曲面。

6. 发明授权

US08916868B2 Semiconductor device and method for manufacturing semiconductor device 有权
标题翻译：半导体装置及半导体装置的制造方法
公开(公告)号：US08916868B2
公开(公告)日：2014-12-23
申请号：US13446016
申请日：2012-04-13
申请人： Atsuo Isobe , Toshinari Sasaki , Shinya Sasagawa , Akihiro Ishizuka
发明人： Atsuo Isobe , Toshinari Sasaki , Shinya Sasagawa , Akihiro Ishizuka
IPC分类号： H01L29/10 , H01L29/786 , H01L27/12 , H01L27/115
CPC分类号： H01L29/66969 , H01L21/02565 , H01L21/0262 , H01L21/477 , H01L27/1156 , H01L27/1225 , H01L29/045 , H01L29/24 , H01L29/7869
摘要： A semiconductor device having a transistor including an oxide semiconductor film is disclosed. In the semiconductor device, the oxide semiconductor film is provided along a trench formed in an insulating layer. The trench includes a lower end corner portion and an upper end corner portion having a curved shape with a curvature radius of longer than or equal to 20 nm and shorter than or equal to 60 nm, and the oxide semiconductor film is provided in contact with a bottom surface, the lower end corner portion, the upper end corner portion, and an inner wall surface of the trench. The oxide semiconductor film includes a crystal having a c-axis substantially perpendicular to a surface at least over the upper end corner portion.
摘要翻译：公开了一种具有包括氧化物半导体膜的晶体管的半导体器件。在半导体装置中，沿着形成在绝缘层中的沟槽设置氧化物半导体膜。沟槽包括具有曲率半径大于或等于20nm且小于或等于60nm的弯曲形状的下端拐角部分和上端拐角部分，并且氧化物半导体膜设置成与底面，下端角部，上端角部和沟槽的内壁面。氧化物半导体膜包括至少在上端角部上方具有基本上垂直于表面的c轴的晶体。

7. 发明授权

US08664118B2 Semiconductor device and method for manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08664118B2
公开(公告)日：2014-03-04
申请号：US13539907
申请日：2012-07-02
申请人： Akihiro Ishizuka , Kazuya Hanaoka , Shinya Sasagawa , Sho Nagamatsu
发明人： Akihiro Ishizuka , Kazuya Hanaoka , Shinya Sasagawa , Sho Nagamatsu
IPC分类号： H01L21/302
CPC分类号： H01L21/02422 , H01L21/02488 , H01L21/02554 , H01L21/02565 , H01L21/02658 , H01L21/02661 , H01L21/3105 , H01L29/66969 , H01L29/78636 , H01L29/7869
摘要： An object is to provide a semiconductor device having excellent characteristics, in which a channel layer includes an oxide semiconductor with high crystallinity. In addition, a semiconductor device including a base film with improved planarity is provided. CMP treatment is performed on the base film of the transistor and plasma treatment is performed thereon after the CMP treatment, whereby the base film can have a center line average roughness Ra75 of less than 0.1 nm. The oxide semiconductor layer with high crystallinity is formed over the base film having planarity, which is obtained by the combination of the plasma treatment and the CMP treatment, thereby improving the characteristics of the semiconductor device.
摘要翻译：目的在于提供具有优异特性的半导体器件，其中沟道层包括具有高结晶度的氧化物半导体。此外，提供了包括具有改善的平面度的基膜的半导体器件。在晶体管的基膜上进行CMP处理，在CMP处理之后进行等离子体处理，由此基膜的中心线平均粗糙度Ra75可以小于0.1nm。在通过等离子体处理和CMP处理的组合获得的具有平坦度的基膜上形成具有高结晶度的氧化物半导体层，从而提高半导体器件的特性。

8. 发明授权

US08436403B2 Semiconductor device including transistor provided with sidewall and electronic appliance 有权
标题翻译：包括设置有侧壁和电子设备的晶体管的半导体器件
公开(公告)号：US08436403B2
公开(公告)日：2013-05-07
申请号：US13014081
申请日：2011-01-26
申请人： Shunpei Yamazaki , Hiromichi Godo , Hideomi Suzawa , Shinya Sasagawa , Motomu Kurata , Mayumi Mikami
发明人： Shunpei Yamazaki , Hiromichi Godo , Hideomi Suzawa , Shinya Sasagawa , Motomu Kurata , Mayumi Mikami
IPC分类号： H01L21/84
CPC分类号： H01L29/7869 , H01L29/41733 , H01L29/45 , H01L29/66969 , Y10T428/24421
摘要： One object is to provide a semiconductor device that includes an oxide semiconductor and is reduced in size with favorable characteristics maintained. The semiconductor device includes an oxide semiconductor layer, a source electrode and a drain electrode in contact with the oxide semiconductor layer, a gate electrode overlapping with the oxide semiconductor layer; and a gate insulating layer between the oxide semiconductor layer and the gate electrode. The source electrode or the drain electrode includes a first conductive layer and a second conductive layer having a region extended in a channel length direction from an end face of the first conductive layer. The sidewall insulating layer has a length of a bottom surface in the channel length direction smaller than a length in the channel length direction of the extended region of the second conductive layer and is provided over the extended region.
摘要翻译：一个目的是提供一种包括氧化物半导体的半导体器件，并且尺寸减小，并保持良好的特性。半导体器件包括与氧化物半导体层接触的氧化物半导体层，源电极和漏电极，与氧化物半导体层重叠的栅电极; 以及在氧化物半导体层和栅电极之间的栅极绝缘层。源电极或漏极包括第一导电层和具有从第一导电层的端面在沟道长度方向上延伸的区域的第二导电层。侧壁绝缘层的沟道长度方向的底面的长度小于第二导电层的延伸区域的沟道长度方向的长度，并且设置在延伸区域上。

9. 发明授权

US07998801B2 Manufacturing method of thin film transistor having altered semiconductor layer 有权
标题翻译：具有改变的半导体层的薄膜晶体管的制造方法
公开(公告)号：US07998801B2
公开(公告)日：2011-08-16
申请号：US12424563
申请日：2009-04-16
申请人： Shinya Sasagawa , Motomu Kurata , Sho Osada
发明人： Shinya Sasagawa , Motomu Kurata , Sho Osada
IPC分类号： H01L21/00 , H01L21/302
CPC分类号： H01L27/1288 , H01L27/1214 , H01L29/04 , H01L29/40 , H01L29/41733 , H01L29/66765 , H01L29/78669 , H01L29/78678 , H01L29/78696
摘要： Decrease of the off-state current, increase of the on-state current, and reduction of variations of electrical characteristics. A method for manufacturing a channel-etched inversed staggered thin film transistor includes the following steps: removing, by first dry-etching, a part of a semiconductor layer including an impurity element which imparts one conductivity type, which is exposed from the source and drain electrodes, and partially a part of an amorphous semiconductor layer just below and in contact with the part of the semiconductor layer; removing, by second dry-etching, partially the part of the amorphous semiconductor layer which is exposed by the first dry-etching; and performing plasma treatment on the surface of the part of the amorphous semiconductor layer which is exposed by the second dry-etching so that an altered layer is formed.
摘要翻译：关闭状态电流的减小，导通电流的增加以及电特性变化的减小。用于制造通道蚀刻反向交错薄膜晶体管的方法包括以下步骤：通过首先干蚀刻除去包括从源极和漏极暴露的赋予一种导电类型的杂质元素的半导体层的一部分电极，以及半导体层的正下方并与半导体层的一部分接触的部分非晶半导体层的一部分; 通过第二干法蚀刻部分地除去通过第一干法蚀刻暴露的部分非晶半导体层; 并且通过第二干蚀刻曝光的非晶半导体层的部分的表面进行等离子体处理，从而形成改变的层。

10. 发明申请

US20100096637A1 THIN FILM TRANSISTOR AND MANUFACTURING METHOD THEREOF 有权
标题翻译：薄膜晶体管及其制造方法
公开(公告)号：US20100096637A1
公开(公告)日：2010-04-22
申请号：US12423829
申请日：2009-04-15
申请人： Shunpei Yamazaki , Yuji Egi , Shinya Sasagawa , Motomu Kurata
发明人： Shunpei Yamazaki , Yuji Egi , Shinya Sasagawa , Motomu Kurata
IPC分类号： H01L29/786 , H01L21/336
CPC分类号： H01L27/1288 , H01L27/1214 , H01L29/04 , H01L29/41733 , H01L29/78696
摘要： Off current of a thin film transistor is reduced, and on current of the thin film transistor is increased, and variation in electric characteristics is reduced. As a structure of semiconductor layers which form a channel formation region of a thin film transistor, a first semiconductor layer including a plurality of crystalline regions is provided on a gate insulating layer side; a second semiconductor layer having an amorphous structure is provided on a source region and drain region side; an insulating layer with a thickness small enough to allow carrier travel is provided between the first semiconductor layer and the second semiconductor layer. The first semiconductor layer is in contact with the gate insulating layer. The second semiconductor layer is provided on an opposite side to a face of the first semiconductor layer which is in contact with the gate insulating layer.
摘要翻译：薄膜晶体管的截止电流减小，薄膜晶体管的导通电流增大，电特性的变化也降低。作为形成薄膜晶体管的沟道形成区域的半导体层的结构，在栅极绝缘层侧设置包括多个结晶区域的第一半导体层，在源区和漏区侧设置具有非晶结构的第二半导体层; 在第一半导体层和第二半导体层之间设置具有足够小以允许载流子行进的厚度的绝缘层。第一半导体层与栅极绝缘层接触。第二半导体层设置在与栅极绝缘层接触的与第一半导体层的面相反的一侧。

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