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1. 发明申请

US20100302884A1 Method of preventing coupling noises for a non-volatile semiconductor memory device 有权
标题翻译：防止非易失性半导体存储器件耦合噪声的方法
公开(公告)号：US20100302884A1
公开(公告)日：2010-12-02
申请号：US12662247
申请日：2010-04-07
申请人： Kwang-Jin Lee , Yong-Jun Lee , Du-Eung Kim , Woo-Yeong Cho , Joon-Yong Choi
发明人： Kwang-Jin Lee , Yong-Jun Lee , Du-Eung Kim , Woo-Yeong Cho , Joon-Yong Choi
IPC分类号： G11C7/00
CPC分类号： G11C7/04 , G11C7/18 , G11C7/22 , G11C16/32 , G11C2207/002
摘要： Disclosed is a method of preventing coupling noises for a non-volatile semiconductor memory device. According to the method, if an edge of a write operation signal overlaps an activated period of a read operation signal a check result is generated. The write operation signal is modified based on the check result.
摘要翻译：公开了一种防止用于非易失性半导体存储器件的耦合噪声的方法。根据该方法，如果写入操作信号的边缘与读取操作信号的激活时段重叠，则产生检查结果。基于检查结果修改写操作信号。

2. 发明授权

US08102704B2 Method of preventing coupling noises for a non-volatile semiconductor memory device 有权
标题翻译：防止非易失性半导体存储器件耦合噪声的方法
公开(公告)号：US08102704B2
公开(公告)日：2012-01-24
申请号：US12662247
申请日：2010-04-07
申请人： Kwang-Jin Lee , Yong-Jun Lee , Du-Eung Kim , Woo-Yeong Cho , Joon-Yong Choi
发明人： Kwang-Jin Lee , Yong-Jun Lee , Du-Eung Kim , Woo-Yeong Cho , Joon-Yong Choi
IPC分类号： G11C16/32
CPC分类号： G11C7/04 , G11C7/18 , G11C7/22 , G11C16/32 , G11C2207/002
摘要： Disclosed is a method of preventing coupling noises for a non-volatile semiconductor memory device. According to the method, if an edge of a write operation signal overlaps an activated period of a read operation signal a check result is generated. The write operation signal is modified based on the check result.
摘要翻译：公开了一种防止用于非易失性半导体存储器件的耦合噪声的方法。根据该方法，如果写入操作信号的边缘与读取操作信号的激活时段重叠，则产生检查结果。基于检查结果修改写操作信号。

3. 发明授权

US08194492B2 Variable resistance memory device and system 有权
标题翻译：可变电阻存储器件和系统
公开(公告)号：US08194492B2
公开(公告)日：2012-06-05
申请号：US12693005
申请日：2010-01-25
申请人： Qi Wang , Kwang-Jin Lee , Woo-Yeong Cho , Taek-Sung Kim , Kwang-Ho Kim , Hyun-Ho Choi , Yong-Jun Lee , Hye-Jin Kim
发明人： Qi Wang , Kwang-Jin Lee , Woo-Yeong Cho , Taek-Sung Kim , Kwang-Ho Kim , Hyun-Ho Choi , Yong-Jun Lee , Hye-Jin Kim
IPC分类号： G11C8/00
CPC分类号： G11C8/12 , G11C11/005 , G11C11/56 , G11C11/5678 , G11C13/0004 , G11C13/0023 , G11C13/0028 , G11C13/0069 , G11C16/0483 , G11C2013/0078 , G11C2213/71
摘要： Disclosed is a semiconductor memory device including a memory cell array having a plurality of variable resistance memory cells divided into first and second areas. An I/O circuit is configured to access the memory cell array under the control of control logic so as to access the first or second area in response to an external command. The I/O circuit accesses the first area using a memory cell unit and the second area using a page unit.
摘要翻译：公开了一种半导体存储器件，包括具有分成第一和第二区域的多个可变电阻存储器单元的存储单元阵列。 I / O电路被配置为在控制逻辑的控制下访问存储单元阵列，以响应于外部命令访问第一或第二区域。 I / O电路使用存储单元单元访问第一区域，并且使用页面单元访问第二区域。

4. 发明授权

US08218379B2 Semiconductor device having resistance based memory array, method of operation, and systems associated therewith 有权
标题翻译：具有基于电阻的存储器阵列，操作方法和与其相关联的系统的半导体器件
公开(公告)号：US08218379B2
公开(公告)日：2012-07-10
申请号：US12318241
申请日：2008-12-23
申请人： Yong-Jun Lee , Kwang-Jin Lee , Taek-Sung Kim , Kwang-Ho Kim , Woo-Yeong Cho , Hyun-Ho Choi , Hye Jin Kim
发明人： Yong-Jun Lee , Kwang-Jin Lee , Taek-Sung Kim , Kwang-Ho Kim , Woo-Yeong Cho , Hyun-Ho Choi , Hye Jin Kim
IPC分类号： G11C16/04
CPC分类号： G11C13/0069 , G11C13/0004 , G11C13/0023 , G11C13/0026 , G11C13/0064 , G11C13/0097 , G11C2013/0078 , G11C2213/72
摘要： In one embodiment, the semiconductor device includes a non-volatile memory cell array, a write circuit configured to write to the non-volatile memory cell array, and a control circuit. The control circuit is configured to store at least one erase indicator. The erase indicator is associated with at least a portion of the non-volatile memory cell array and indicates a logic state. The control circuit is configured to control the write circuit to write the logic state indicated by the erase indicator in the non-volatile memory cell array during an erase operation of the associated portion of the non-volatile memory cell array.
摘要翻译：在一个实施例中，半导体器件包括非易失性存储单元阵列，被配置为写入非易失性存储单元阵列的写入电路和控制电路。控制电路被配置为存储至少一个擦除指示符。擦除指示符与非易失性存储单元阵列的至少一部分相关联并且指示逻辑状态。控制电路被配置为在非易失性存储单元阵列的相关部分的擦除操作期间，控制写入电路将由擦除指示符指示的逻辑状态写入非易失性存储单元阵列。

5. 发明申请

US20090168494A1 Semiconductor device having resistance based memory array, method of operation, and systems associated therewith 有权
标题翻译：具有基于电阻的存储器阵列，操作方法和与其相关联的系统的半导体器件
公开(公告)号：US20090168494A1
公开(公告)日：2009-07-02
申请号：US12318241
申请日：2008-12-23
申请人： Yong-Jun Lee , Kwang-Jin Lee , Taek-Sung Kim , Kwang-Ho Kim , Woo-Yeong Cho , Hyun-Ho Choi , Hye Jin Kim
发明人： Yong-Jun Lee , Kwang-Jin Lee , Taek-Sung Kim , Kwang-Ho Kim , Woo-Yeong Cho , Hyun-Ho Choi , Hye Jin Kim
IPC分类号： G11C11/00 , G11C7/00 , G11C8/00
CPC分类号： G11C13/0069 , G11C13/0004 , G11C13/0023 , G11C13/0026 , G11C13/0064 , G11C13/0097 , G11C2013/0078 , G11C2213/72
摘要： In one embodiment, the semiconductor device includes a non-volatile memory cell array, a write circuit configured to write to the non-volatile memory cell array, and a control circuit. The control circuit is configured to store at least one erase indicator. The erase indicator is associated with at least a portion of the non-volatile memory cell array and indicates a logic state. The control circuit is configured to control the write circuit to write the logic state indicated by the erase indicator in the non-volatile memory cell array during an erase operation of the associated portion of the non-volatile memory cell array.
摘要翻译：在一个实施例中，半导体器件包括非易失性存储单元阵列，被配置为写入非易失性存储单元阵列的写入电路和控制电路。控制电路被配置为存储至少一个擦除指示符。擦除指示符与非易失性存储单元阵列的至少一部分相关联并且指示逻辑状态。控制电路被配置为在非易失性存储单元阵列的相关部分的擦除操作期间，控制写入电路将由擦除指示符指示的逻辑状态写入非易失性存储单元阵列。

6. 发明申请

US20100329057A1 Method of discharging bit-lines for a non-volatile semiconductor memory device performing a read-while-write operation 有权
标题翻译：对执行读写操作的非易失性半导体存储器件的位线进行放电的方法
公开(公告)号：US20100329057A1
公开(公告)日：2010-12-30
申请号：US12662512
申请日：2010-04-21
申请人： Yong-Jun Lee , Byung-Gil Choi , Du-Eung Kim
发明人： Yong-Jun Lee , Byung-Gil Choi , Du-Eung Kim
IPC分类号： G11C7/00
CPC分类号： G11C7/12 , G11C13/0004 , G11C13/0026 , G11C2213/72 , G11C2213/79
摘要： In a method of discharging bit-lines for a non-volatile semiconductor memory device performing a read-while-write operation. The method include discharging a global write bit-line to a ground voltage based on a write command within a first period. the method also includes maintaining the discharged voltage of the global write bit-line in the ground voltage during a second period.
摘要翻译：在执行读写操作的非易失性半导体存储器件的放电位线的方法中。该方法包括在第一周期内基于写入命令将全局写入位线放电到接地电压。该方法还包括在第二周期期间将全局写入位线的放电电压维持在接地电压中。

7. 发明授权

US08254159B2 Method of discharging bit-lines for a non-volatile semiconductor memory device performing a read-while-write operation 有权
标题翻译：对执行读写操作的非易失性半导体存储器件的位线进行放电的方法
公开(公告)号：US08254159B2
公开(公告)日：2012-08-28
申请号：US12662512
申请日：2010-04-21
申请人： Yong-Jun Lee , Byung-Gil Choi , Du-Eung Kim
发明人： Yong-Jun Lee , Byung-Gil Choi , Du-Eung Kim
IPC分类号： G11C11/00
CPC分类号： G11C7/12 , G11C13/0004 , G11C13/0026 , G11C2213/72 , G11C2213/79
摘要： In a method of discharging bit-lines for a non-volatile semiconductor memory device performing a read-while-write operation. The method include discharging a global write bit-line to a ground voltage based on a write command within a first period. The method also includes maintaining the discharged voltage of the global write bit-line in the ground voltage during a second period.
摘要翻译：在执行读写操作的非易失性半导体存储器件的放电位线的方法中。该方法包括在第一周期内基于写入命令将全局写入位线放电到接地电压。该方法还包括在第二周期期间将全局写入位线的放电电压保持在接地电压中。

8. 发明申请

US20100284221A1 Nonvolatile memory device and method for controlling word line or bit line thereof 有权
标题翻译：用于控制字线或其位线的非易失性存储器件和方法
公开(公告)号：US20100284221A1
公开(公告)日：2010-11-11
申请号：US12659690
申请日：2010-03-17
申请人： Joon-Yong Choi , Byunggil Choi , Yu Hwan Ro , Yong-Jun Lee
发明人： Joon-Yong Choi , Byunggil Choi , Yu Hwan Ro , Yong-Jun Lee
IPC分类号： G11C16/04
CPC分类号： G11C16/08
摘要： A nonvolatile memory device includes global selection lines, local selection lines, a first selection circuit, and a second selection circuit. The local lines correspond respectively to the global selection lines. The first selection circuit is configured to connect to the global selection lines to select the global selection lines. The second selection circuit is connected between the global selection lines and the local selection lines and is configured to select the local selection lines. The first selection circuit is configured to select at least one global selection line, and the second selection circuit is configured to select the local selection lines corresponding to the selected global selection line while the at least one global selection line is continuously activated.
摘要翻译：非易失性存储器件包括全局选择线，局部选择线，第一选择电路和第二选择电路。本地线分别对应于全局选择线。第一选择电路被配置为连接到全局选择线以选择全局选择线。第二选择电路连接在全局选择线和本地选择线之间，并被配置为选择本地选择线。第一选择电路被配置为选择至少一个全局选择线，并且第二选择电路被配置为在连续激活至少一个全局选择线的同时选择与所选择的全局选择线对应的本地选择线。

9. 发明授权

US08305806B2 Nonvolatile memory device and method for controlling word line or bit line thereof 有权
标题翻译：用于控制字线或其位线的非易失性存储器件和方法
公开(公告)号：US08305806B2
公开(公告)日：2012-11-06
申请号：US12659690
申请日：2010-03-17
申请人： Joon-Yong Choi , Byunggil Choi , Yu Hwan Ro , Yong-Jun Lee
发明人： Joon-Yong Choi , Byunggil Choi , Yu Hwan Ro , Yong-Jun Lee
IPC分类号： G11C16/04
CPC分类号： G11C16/08
摘要： A nonvolatile memory device includes global selection lines, local selection lines, a first selection circuit, and a second selection circuit. The local lines correspond respectively to the global selection lines. The first selection circuit is configured to connect to the global selection lines to select the global selection lines. The second selection circuit is connected between the global selection lines and the local selection lines and is configured to select the local selection lines. The first selection circuit is configured to select at least one global selection line, and the second selection circuit is configured to select the local selection lines corresponding to the selected global selection line while the at least one global selection line is continuously activated.
摘要翻译：非易失性存储器件包括全局选择线，局部选择线，第一选择电路和第二选择电路。本地线分别对应于全局选择线。第一选择电路被配置为连接到全局选择线以选择全局选择线。第二选择电路连接在全局选择线和本地选择线之间，并被配置为选择本地选择线。第一选择电路被配置为选择至少一个全局选择线，并且第二选择电路被配置为在连续激活至少一个全局选择线的同时选择与所选择的全局选择线对应的本地选择线。

10. 发明授权

US08547724B2 Nonvolatile memory device comprising one-time-programmable lock bit register 有权
标题翻译：非易失性存储器件包括一次性可编程锁定位寄存器
公开(公告)号：US08547724B2
公开(公告)日：2013-10-01
申请号：US13032848
申请日：2011-02-23
申请人： Yong-Jun Lee , Kwang Jin Lee , Joon Min Park , Huik Won Seo
发明人： Yong-Jun Lee , Kwang Jin Lee , Joon Min Park , Huik Won Seo
IPC分类号： G11C17/00
CPC分类号： G11C17/18 , G11C11/005 , G11C13/0004 , G11C13/0059 , G11C2211/5641 , G11C2211/5646
摘要： A nonvolatile memory device comprises a one-time-programmable (OTP) lock bit register. The nonvolatile memory device comprises a variable-resistance memory cell array comprising an OTP block that store data and a register that stores OTP lock state information indicating whether the data is changeable. The register comprises a variable memory cell. An initial value of the OTP lock state information is set to a program protection state.
摘要翻译：非易失性存储器件包括一次性可编程（OTP）锁定位寄存器。非易失性存储器件包括可变电阻存储单元阵列，其包括存储数据的OTP块和存储指示数据是否可更改的OTP锁定状态信息的寄存器。寄存器包括可变存储单元。 OTP锁定状态信息的初始值被设置为程序保护状态。

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