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1. 发明授权

US08174878B2 Nonvolatile memory, memory system, and method of driving 有权
标题翻译：非易失性存储器，存储器系统和驾驶方法
公开(公告)号：US08174878B2
公开(公告)日：2012-05-08
申请号：US13053471
申请日：2011-03-22
申请人： Joon-Min Park , Kwang-Jin Lee , Du-Eung Kim , Woo-Yeong Cho , Hui-Kwon Seo
发明人： Joon-Min Park , Kwang-Jin Lee , Du-Eung Kim , Woo-Yeong Cho , Hui-Kwon Seo
IPC分类号： G11C11/00
CPC分类号： G11C13/0069 , G11C13/0004 , G11C2213/72
摘要： Provided are a nonvolatile memory and related method of programming same. The nonvolatile memory includes a memory cell array with a plurality of nonvolatile memory cells and a write circuit. The write circuit is configured to write first logic state data to a first group of memory cells during a first program operation using an internally generated step-up voltage, and second logic state data to a second group of memory cells during a second program operation using an externally supplied step-up voltage.
摘要翻译：提供了一种非易失性存储器及其相关编程方法。非易失性存储器包括具有多个非易失性存储单元和写入电路的存储单元阵列。写电路被配置为在第一程序操作期间使用内部产生的升压电压将第一逻辑状态数据写入第一组存储器单元，并且在第二程序操作期间将第二逻辑状态数据写入第二组存储器单元外部提供的升压电压。

2. 发明授权

US07907467B2 Resistance semiconductor memory device having three-dimensional stack and word line decoding method thereof 有权
标题翻译：具有三维堆叠和字线解码方法的电阻半导体存储器件
公开(公告)号：US07907467B2
公开(公告)日：2011-03-15
申请号：US12873836
申请日：2010-09-01
申请人： Joon-Min Park , Sang-Beom Kang , Hyung-Rok Oh , Woo-Yeong Cho
发明人： Joon-Min Park , Sang-Beom Kang , Hyung-Rok Oh , Woo-Yeong Cho
IPC分类号： G11C8/00
CPC分类号： G11C8/08 , G11C8/14 , G11C11/16 , G11C13/00 , G11C13/0004 , G11C13/0023 , G11C13/0028 , G11C2213/71 , G11C2213/72
摘要： A resistance semiconductor memory device of a three-dimensional stack structure, and a word line decoding method thereof, are provided. In the resistance semiconductor memory device of a three-dimensional stack structure, in which a plurality of word line layers and a plurality of bit line layers are disposed alternately and perpendicularly, and in which a plurality of memory cell layers are disposed between the word line layers and the bit line layers; the resistance semiconductor memory device includes a plurality of bit lines disposed on each of the bit line layers in a first direction as a length direction; a plurality of sub word lines disposed on each of the word line layers in a second direction as a length direction, intersected to the first direction; a plurality of memory cells disposed on the memory cell layers; and a plurality of main word lines individually disposed on a main word line layer specifically adapted over the bit line layers and the word line layers, in the second direction as a length direction, each one of the plurality of main word lines being shared by a predetermined number of sub word lines. An efficient word line decoding adequate to high integration can be achieved.
摘要翻译：提供三维堆栈结构的电阻半导体存储器件及其字线解码方法。在三维堆叠结构的电阻半导体存储器件中，其中多个字线层和多个位线层交替和垂直地布置，并且其中多个存储单元层设置在字线层和位线层; 电阻半导体存储器件包括沿着第一方向设置在每个位线层上的多个位线作为长度方向; 在与第一方向相交的长度方向的第二方向上设置在每个字线层上的多个子字线; 设置在所述存储单元层上的多个存储单元; 以及多个主字线分别设置在主字线层上，特别适用于位线层和字线层，在第二方向上作为长度方向，多个主字线中的每一条由预定数量的子字线。可以实现足够高集成度的有效的字线解码。

3. 发明授权

US07881145B2 Semiconductor device and semiconductor system having the same 有权
标题翻译：半导体器件和具有该半导体器件的半导体系统
公开(公告)号：US07881145B2
公开(公告)日：2011-02-01
申请号：US12453872
申请日：2009-05-26
申请人： Kwang Jin Lee , Joon Min Park , Hye-Jin Kim
发明人： Kwang Jin Lee , Joon Min Park , Hye-Jin Kim
IPC分类号： G11C8/00
CPC分类号： G11C13/0069 , G11C7/22 , G11C8/12 , G11C13/0004 , G11C2013/0076 , G11C2207/2209
摘要： A semiconductor device according to example embodiments may be configured so that, when a read command for performing a read operation is input while a write operation is performed, and when a memory bank accessed by a write address during the write operation is the same as a memory bank accessed by a read address during the read operation, the semiconductor device may suspend the write operation automatically or in response to an internal signal until the read operation is finished and performs the write operation after the read operation is finished.
摘要翻译：根据示例实施例的半导体器件可以被配置为使得当执行写入操作时输入用于执行读取操作的读取命令，并且当在写入操作期间由写入地址访问的存储体组与存储体在读取操作期间由读取地址访问，半导体器件可以自动暂停写入操作或响应于内部信号直到读取操作完成，并且在读取操作完成之后执行写入操作。

4. 发明申请

US20100329070A1 Resistance Semiconductor Memory Device Having Three-Dimensional Stack and Word Line Decoding Method Thereof 有权
标题翻译：具有三维堆栈和字线解码方法的电阻半导体存储器件
公开(公告)号：US20100329070A1
公开(公告)日：2010-12-30
申请号：US12873836
申请日：2010-09-01
申请人： Joon Min Park , Sang-Beom Kang , Hyung-Rok Oh , Woo-Yeong Cho
发明人： Joon Min Park , Sang-Beom Kang , Hyung-Rok Oh , Woo-Yeong Cho
IPC分类号： G11C8/10
CPC分类号： G11C8/08 , G11C8/14 , G11C11/16 , G11C13/00 , G11C13/0004 , G11C13/0023 , G11C13/0028 , G11C2213/71 , G11C2213/72
摘要： A resistance semiconductor memory device of a three-dimensional stack structure, and a word line decoding method thereof, are provided. In the resistance semiconductor memory device of a three-dimensional stack structure, in which a plurality of word line layers and a plurality of bit line layers are disposed alternately and perpendicularly, and in which a plurality of memory cell layers are disposed between the word line layers and the bit line layers; the resistance semiconductor memory device includes a plurality of bit lines disposed on each of the bit line layers in a first direction as a length direction; a plurality of sub word lines disposed on each of the word line layers in a second direction as a length direction, intersected to the first direction; a plurality of memory cells disposed on the memory cell layers; and a plurality of main word lines individually disposed on a main word line layer specifically adapted over the bit line layers and the word line layers, in the second direction as a length direction, each one of the plurality of main word lines being shared by a predetermined number of sub word lines. An efficient word line decoding adequate to high integration can be achieved.
摘要翻译：提供三维堆栈结构的电阻半导体存储器件及其字线解码方法。在三维堆叠结构的电阻半导体存储器件中，其中多个字线层和多个位线层交替和垂直地布置，并且其中多个存储单元层设置在字线层和位线层; 电阻半导体存储器件包括沿着第一方向设置在每个位线层上的多个位线作为长度方向; 在与第一方向相交的长度方向的第二方向上配置在每个字线层上的多个子字线; 设置在所述存储单元层上的多个存储单元; 以及多个主字线分别设置在主字线层上，特别适用于位线层和字线层，在第二方向上作为长度方向，多个主字线中的每一条由预定数量的子字线。可以实现足够高集成度的有效的字线解码。

5. 发明授权

US07843716B2 Nonvolatile memory device having memory and reference cells 有权
标题翻译：具有存储器和参考单元的非易失性存储器件
公开(公告)号：US07843716B2
公开(公告)日：2010-11-30
申请号：US12031085
申请日：2008-02-14
申请人： Sang-beom Kang , Woo-yeong Cho , Hyung-rok Oh , Joon-min Park
发明人： Sang-beom Kang , Woo-yeong Cho , Hyung-rok Oh , Joon-min Park
IPC分类号： G11C5/02
CPC分类号： G11C7/067 , G11C5/025 , G11C5/04 , G11C7/062 , G11C8/10 , G11C8/14 , G11C11/16 , G11C13/00 , G11C13/0004 , G11C13/0028 , G11C13/004 , G11C2013/0054 , G11C2207/063 , G11C2213/71 , G11C2213/72
摘要： A nonvolatile memory device includes a stack-type memory cell array, a selection circuit and a read circuit. The memory cell array includes multiple memory cell layers and a reference cell layer, which are vertically laminated. Each of the memory cell layers includes multiple nonvolatile memory cells for storing data, and the reference cell layer includes multiple reference cells for storing reference data. The selection circuit selects a nonvolatile memory cell from the memory cell layers and at least one reference cell, corresponding to the selected nonvolatile memory cell, from the reference cell layer. The read circuit supplies a read bias to the selected nonvolatile memory cell and the selected reference cell corresponding to the selected nonvolatile memory cell, and reads data from the selected nonvolatile memory cell.
摘要翻译：非易失性存储器件包括堆叠型存储单元阵列，选择电路和读取电路。存储单元阵列包括垂直层叠的多个存储单元层和参考单元层。每个存储单元层包括用于存储数据的多个非易失性存储单元，参考单元层包括用于存储参考数据的多个参考单元。选择电路从参考单元层从存储单元层和对应于所选择的非易失性存储单元的至少一个参考单元选择非易失性存储单元。读取电路向所选择的非易失性存储单元和与所选择的非易失性存储单元相对应的所选择的参考单元提供读偏置，并从所选择的非易失性存储单元读取数据。

6. 发明申请

US20100131708A1 Semiconductor device having resistance based memory array, method of reading and writing, and systems associated therewith 审中-公开
标题翻译：具有基于电阻的存储器阵列，读取和写入方法以及与其相关联的系统的半导体器件
公开(公告)号：US20100131708A1
公开(公告)日：2010-05-27
申请号：US12292896
申请日：2008-11-28
申请人： Joon-Min Park , Kwang Jin Lee , Beak-Hyung Cho
发明人： Joon-Min Park , Kwang Jin Lee , Beak-Hyung Cho
IPC分类号： G06F12/00
CPC分类号： G11C13/0069 , G11C15/046 , G11C2013/0076
摘要： In one embodiment, the semiconductor device includes a non-volatile memory cell array, a write buffer configured to store data being written into the non-volatile memory cell array, and a write address buffer configured to store a write address associated with each data stored in the write buffer. An output circuit is configured to selectively output one of data read from the non-volatile memory array and data from the write buffer. A by-pass control circuit is configured to control the output circuit based on whether an input read address matches a valid write address stored in the write address buffer. An invalidation unit is configured to invalidate an address stored in the write address buffer if the stored write address matches an input write address.
摘要翻译：在一个实施例中，半导体器件包括非易失性存储器单元阵列，被配置为存储被写入非易失性存储单元阵列的数据的写入缓冲器，以及写入地址缓冲器，被配置为存储与存储的每个数据相关联的写入地址在写缓冲区。输出电路被配置为选择性地输出从非易失性存储器阵列读取的数据和来自写入缓冲器的数据之一。旁路控制电路被配置为基于输入读取地址是否匹配存储在写入地址缓冲器中的有效写入地址来控制输出电路。如果所存储的写入地址与输入写入地址相匹配，则无效单元被配置为使存储在写入地址缓冲器中的地址无效。

7. 发明授权

US07724560B2 Nonvolatile memory device having twin memory cells 有权
标题翻译：具有双存储单元的非易失性存储器件
公开(公告)号：US07724560B2
公开(公告)日：2010-05-25
申请号：US12107985
申请日：2008-04-23
申请人： Sang-Beom Kang , Woo-Yeong Cho , Hyung-Rok Oh , Joon-Min Park
发明人： Sang-Beom Kang , Woo-Yeong Cho , Hyung-Rok Oh , Joon-Min Park
IPC分类号： G11C5/06
CPC分类号： G11C13/003 , G11C11/14 , G11C11/22 , G11C13/0004 , G11C13/0007 , G11C13/004 , G11C2013/0054 , G11C2213/31 , G11C2213/71 , G11C2213/72 , G11C2213/74 , G11C2213/76
摘要： A nonvolatile memory device includes multiple first bit lines extending in a first direction, multiple word lines formed on the first bit lines and extending in a second direction different from the first direction, and multiple second bit lines, formed on the word lines and extending in the first direction. The nonvoliative memory device also includes multiple twin memory cells, each of which includes a first memory cell coupled between a first bit line and a word line and a second memory cell coupled between the word line and a second bit line. The first and second memory cells store different data.
摘要翻译：非易失性存储器件包括沿第一方向延伸的多个第一位线，形成在第一位线上并在与第一方向不同的第二方向上延伸的多个字线以及形成在字线上并在字线上延伸的多个第二位线第一个方向。非易失性存储器件还包括多个双存储器单元，每个存储单元包括耦合在第一位线和字线之间的第一存储器单元和耦合在字线和第二位线之间的第二存储单元。第一和第二存储单元存储不同的数据。

8. 发明申请

US20080212352A1 MULTI-LAYER SEMICONDUCTOR MEMORY DEVICE COMPRISING ERROR CHECKING AND CORRECTION (ECC) ENGINE AND RELATED ECC METHOD 有权
标题翻译：包含错误检查和校正（ECC）发动机和相关ECC方法的多层半导体存储器件
公开(公告)号：US20080212352A1
公开(公告)日：2008-09-04
申请号：US12036414
申请日：2008-02-25
申请人： Hyung-rok OH , Sang-beom KANG , Woo-yeong CHO , Joon-min PARK
发明人： Hyung-rok OH , Sang-beom KANG , Woo-yeong CHO , Joon-min PARK
IPC分类号： G11C5/02 , G11C7/00 , G11C11/00
CPC分类号： G06F11/1008 , G11C5/02
摘要： Embodiments of the invention provide a multi-layer semiconductor memory device and a related error checking and correction (ECC) method. The multi-layer semiconductor memory device includes first and second memory cell array layers, wherein the first memory cell array layer stores first payload data. The multi-layer semiconductor memory device also includes an ECC engine selectively connected to the second memory cell array layer and configured to receive the first payload data, generate first parity data corresponding to the first payload data, and store the first parity data exclusively in the second memory cell array layer.
摘要翻译：本发明的实施例提供了一种多层半导体存储器件和相关的错误检查和校正（ECC）方法。多层半导体存储器件包括第一和第二存储单元阵列层，其中第一存储单元阵列层存储第一有效载荷数据。多层半导体存储器件还包括选择性地连接到第二存储单元阵列层并被配置为接收第一有效载荷数据的ECC引擎，生成与第一有效载荷数据相对应的第一奇偶校验数据，并将第一奇偶校验数据专门存储在第二存储单元阵列层。

9. 发明授权

US07221611B2 Semiconductor memory device for low power consumption 有权
标题翻译：用于低功耗的半导体存储器件
公开(公告)号：US07221611B2
公开(公告)日：2007-05-22
申请号：US11146513
申请日：2005-06-07
申请人： Gong-Heum Han , Choong-Keun Kwak , Joon-Min Park
发明人： Gong-Heum Han , Choong-Keun Kwak , Joon-Min Park
IPC分类号： G11C5/14 , G11C7/00
CPC分类号： G11C11/417 , G11C5/147
摘要： A semiconductor memory device, which has an array of memory cells connected with a plurality of bit line pairs and a plurality of word lines, to perform a read or write operation of data, having low power consumption is provided. The device includes a first power supply for supplying a first power source voltage. Also, a second power supply supplies a second power source voltage having a lower voltage level than the first power source voltage. Further, the device includes a standard ground. An elevated ground circuit provides an elevated ground voltage having a higher voltage level than that of the standard ground. A first power circuit is connected with the first power supply and the standard ground, and operates in response to the first power source voltage. A second power circuit is connected with the second power supply and the elevated ground circuit, and operates in response to the second power source voltage. Thereby, power and chip size can be reduced.
摘要翻译：提供具有与多个位线对和多个字线连接的存储单元的阵列以执行具有低功耗的数据的读取或写入操作的半导体存储器件。该装置包括用于提供第一电源电压的第一电源。此外，第二电源提供具有比第一电源电压低的电压电平的第二电源电压。此外，该装置包括标准接地。提升的接地电路提供比标准接地电压高的电压电平的升高的接地电压。第一电源电路与第一电源和标准接地相连接，并响应于第一电源电压而工作。第二电源电路与第二电源和升高的接地电路连接，并且响应于第二电源电压而工作。从而可以降低功率和芯片尺寸。

10. 发明申请

US20130308370A1 MEMORY DEVICE AND SYSTEM WITH IMPROVED ERASE OPERATION 有权
标题翻译：具有改进的擦除操作的存储器件和系统
公开(公告)号：US20130308370A1
公开(公告)日：2013-11-21
申请号：US13948138
申请日：2013-07-22
申请人： Kwang-Jin Lee , Chang-Soo Lee , Joon-Min Park , Hui-Kwon Seo , Qi Wang
发明人： Kwang-Jin Lee , Chang-Soo Lee , Joon-Min Park , Hui-Kwon Seo , Qi Wang
IPC分类号： G11C13/00
CPC分类号： G11C13/0097 , G11C13/0004 , G11C13/0069 , G11C2013/0088 , G11C2211/5646
摘要： A memory device includes a memory cell array including a plurality of memory blocks, each memory block including a plurality of memory cells, a plurality of word lines coupled to rows of the plurality of memory cells, a plurality of bit lines coupled to columns of the plurality of memory cells, and a control unit controlling an erase operation so that erase data is simultaneously written in the plurality of memory cells corresponding to an erase unit. A first erase mode may include a first erase unit and a first erase data pattern. A second erase mode may include a second erase unit and a second erase pattern. At least one of the first and second erase units and the first and second erase data patterns are different.
摘要翻译：存储器件包括存储单元阵列，该存储单元阵列包括多个存储器块，每个存储器块包括多个存储器单元，耦合到多个存储器单元中的行的多个字线，耦合到多个存储器单元的列的多个位线多个存储单元，以及控制擦除操作的控制单元，使得擦除数据被同时写入与擦除单元对应的多个存储单元中。第一擦除模式可以包括第一擦除单元和第一擦除数据模式。第二擦除模式可以包括第二擦除单元和第二擦除模式。第一和第二擦除单元以及第一和第二擦除数据模式中的至少一个是不同的。

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