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1. 发明授权

US08305806B2 Nonvolatile memory device and method for controlling word line or bit line thereof 有权
标题翻译：用于控制字线或其位线的非易失性存储器件和方法
公开(公告)号：US08305806B2
公开(公告)日：2012-11-06
申请号：US12659690
申请日：2010-03-17
申请人： Joon-Yong Choi , Byunggil Choi , Yu Hwan Ro , Yong-Jun Lee
发明人： Joon-Yong Choi , Byunggil Choi , Yu Hwan Ro , Yong-Jun Lee
IPC分类号： G11C16/04
CPC分类号： G11C16/08
摘要： A nonvolatile memory device includes global selection lines, local selection lines, a first selection circuit, and a second selection circuit. The local lines correspond respectively to the global selection lines. The first selection circuit is configured to connect to the global selection lines to select the global selection lines. The second selection circuit is connected between the global selection lines and the local selection lines and is configured to select the local selection lines. The first selection circuit is configured to select at least one global selection line, and the second selection circuit is configured to select the local selection lines corresponding to the selected global selection line while the at least one global selection line is continuously activated.
摘要翻译：非易失性存储器件包括全局选择线，局部选择线，第一选择电路和第二选择电路。本地线分别对应于全局选择线。第一选择电路被配置为连接到全局选择线以选择全局选择线。第二选择电路连接在全局选择线和本地选择线之间，并被配置为选择本地选择线。第一选择电路被配置为选择至少一个全局选择线，并且第二选择电路被配置为在连续激活至少一个全局选择线的同时选择与所选择的全局选择线对应的本地选择线。

2. 发明申请

US20100284221A1 Nonvolatile memory device and method for controlling word line or bit line thereof 有权
标题翻译：用于控制字线或其位线的非易失性存储器件和方法
公开(公告)号：US20100284221A1
公开(公告)日：2010-11-11
申请号：US12659690
申请日：2010-03-17
申请人： Joon-Yong Choi , Byunggil Choi , Yu Hwan Ro , Yong-Jun Lee
发明人： Joon-Yong Choi , Byunggil Choi , Yu Hwan Ro , Yong-Jun Lee
IPC分类号： G11C16/04
CPC分类号： G11C16/08
摘要： A nonvolatile memory device includes global selection lines, local selection lines, a first selection circuit, and a second selection circuit. The local lines correspond respectively to the global selection lines. The first selection circuit is configured to connect to the global selection lines to select the global selection lines. The second selection circuit is connected between the global selection lines and the local selection lines and is configured to select the local selection lines. The first selection circuit is configured to select at least one global selection line, and the second selection circuit is configured to select the local selection lines corresponding to the selected global selection line while the at least one global selection line is continuously activated.
摘要翻译：非易失性存储器件包括全局选择线，局部选择线，第一选择电路和第二选择电路。本地线分别对应于全局选择线。第一选择电路被配置为连接到全局选择线以选择全局选择线。第二选择电路连接在全局选择线和本地选择线之间，并被配置为选择本地选择线。第一选择电路被配置为选择至少一个全局选择线，并且第二选择电路被配置为在连续激活至少一个全局选择线的同时选择与所选择的全局选择线对应的本地选择线。

3. 发明授权

US07499316B2 Phase change memory devices and program methods 有权
标题翻译：相变存储器件和程序方法
公开(公告)号：US07499316B2
公开(公告)日：2009-03-03
申请号：US11723354
申请日：2007-03-19
申请人： Byung-Gil Choi , Du-Eung Kim , Yu-Hwan Ro , Joon-Yong Choi , Beak-Hyung Cho , Woo-Yeong Cho
发明人： Byung-Gil Choi , Du-Eung Kim , Yu-Hwan Ro , Joon-Yong Choi , Beak-Hyung Cho , Woo-Yeong Cho
IPC分类号： G11C11/00
CPC分类号： G11C13/0069 , G11C13/0004 , G11C2013/0078 , G11C2213/72
摘要： A phase change memory device is disclosed. It includes a memory cell array including a plurality of memory cells programmed in relation to a phase change material, and a write driver circuit configured to provide a set current and a reset current to a selected memory cell. The write driver circuit includes a set current driver configured to provide the set current and a reset current driver configured to provide the reset current.
摘要翻译：公开了一种相变存储器件。其包括存储单元阵列，其包括相对于相变材料编程的多个存储器单元，以及写入驱动器电路，其被配置为向所选存储单元提供置位电流和复位电流。写驱动器电路包括配置成提供设定电流的设定电流驱动器和被配置为提供复位电流的复位电流驱动器。

4. 发明申请

US20070230239A1 Phase change memory devices and program methods 有权
标题翻译：相变存储器件和程序方法
公开(公告)号：US20070230239A1
公开(公告)日：2007-10-04
申请号：US11723354
申请日：2007-03-19
申请人： Byung-Gil Choi , Du-Eung Kim , Yu-Hwan Ro , Joon-Yong Choi , Beak-Hyung Cho , Woo-Yeong Cho
发明人： Byung-Gil Choi , Du-Eung Kim , Yu-Hwan Ro , Joon-Yong Choi , Beak-Hyung Cho , Woo-Yeong Cho
IPC分类号： G11C11/00
CPC分类号： G11C13/0069 , G11C13/0004 , G11C2013/0078 , G11C2213/72
摘要： A phase change memory device is disclosed. It includes a memory cell array including a plurality of memory cells programmed in relation to a phase change material, and a write driver circuit configured to provide a set current and a reset current to a selected memory cell. The write driver circuit includes a set current driver configured to provide the set current and a reset current driver configured to provide the reset current.
摘要翻译：公开了一种相变存储器件。其包括存储单元阵列，其包括相对于相变材料编程的多个存储器单元，以及写入驱动器电路，其被配置为向所选存储单元提供置位电流和复位电流。写驱动器电路包括配置成提供设定电流的设定电流驱动器和被配置为提供复位电流的复位电流驱动器。

5. 发明申请

US20100302884A1 Method of preventing coupling noises for a non-volatile semiconductor memory device 有权
标题翻译：防止非易失性半导体存储器件耦合噪声的方法
公开(公告)号：US20100302884A1
公开(公告)日：2010-12-02
申请号：US12662247
申请日：2010-04-07
申请人： Kwang-Jin Lee , Yong-Jun Lee , Du-Eung Kim , Woo-Yeong Cho , Joon-Yong Choi
发明人： Kwang-Jin Lee , Yong-Jun Lee , Du-Eung Kim , Woo-Yeong Cho , Joon-Yong Choi
IPC分类号： G11C7/00
CPC分类号： G11C7/04 , G11C7/18 , G11C7/22 , G11C16/32 , G11C2207/002
摘要： Disclosed is a method of preventing coupling noises for a non-volatile semiconductor memory device. According to the method, if an edge of a write operation signal overlaps an activated period of a read operation signal a check result is generated. The write operation signal is modified based on the check result.
摘要翻译：公开了一种防止用于非易失性半导体存储器件的耦合噪声的方法。根据该方法，如果写入操作信号的边缘与读取操作信号的激活时段重叠，则产生检查结果。基于检查结果修改写操作信号。

6. 发明授权

US08102704B2 Method of preventing coupling noises for a non-volatile semiconductor memory device 有权
标题翻译：防止非易失性半导体存储器件耦合噪声的方法
公开(公告)号：US08102704B2
公开(公告)日：2012-01-24
申请号：US12662247
申请日：2010-04-07
申请人： Kwang-Jin Lee , Yong-Jun Lee , Du-Eung Kim , Woo-Yeong Cho , Joon-Yong Choi
发明人： Kwang-Jin Lee , Yong-Jun Lee , Du-Eung Kim , Woo-Yeong Cho , Joon-Yong Choi
IPC分类号： G11C16/32
CPC分类号： G11C7/04 , G11C7/18 , G11C7/22 , G11C16/32 , G11C2207/002
摘要： Disclosed is a method of preventing coupling noises for a non-volatile semiconductor memory device. According to the method, if an edge of a write operation signal overlaps an activated period of a read operation signal a check result is generated. The write operation signal is modified based on the check result.
摘要翻译：公开了一种防止用于非易失性半导体存储器件的耦合噪声的方法。根据该方法，如果写入操作信号的边缘与读取操作信号的激活时段重叠，则产生检查结果。基于检查结果修改写操作信号。

7. 发明申请

US20100142254A1 Nonvolatile Memory Device Using Variable Resistive Element 有权
标题翻译：使用可变电阻元件的非易失性存储器件
公开(公告)号：US20100142254A1
公开(公告)日：2010-06-10
申请号：US12630484
申请日：2009-12-03
申请人： Byung-Gil Choi , Joon-Yong Choi
发明人： Byung-Gil Choi , Joon-Yong Choi
IPC分类号： G11C11/00
CPC分类号： G11C5/063 , G11C8/10 , G11C8/14 , G11C13/00 , G11C13/0004 , G11C13/0028 , G11C13/004 , G11C2013/0045 , G11C2213/72
摘要： A nonvolatile memory device using a variable resistive element is provided. The nonvolatile memory device includes first and second nonvolatile memory cells. Word lines are coupled to the first and second nonvolatile memory cells. First and second bit lines are coupled to the first and second nonvolatile memory cells, respectively. A read circuit reads resistance levels of the first and second nonvolatile memory cells by providing first and second read bias currents of different levels to the first and second bit lines, respectively.
摘要翻译：提供了使用可变电阻元件的非易失性存储器件。非易失性存储器件包括第一和第二非易失性存储单元。字线耦合到第一和第二非易失性存储单元。第一和第二位线分别耦合到第一和第二非易失性存储器单元。读取电路通过分别向第一和第二位线提供不同电平的第一和第二读取偏置电流来读取第一和第二非易失性存储器单元的电阻电平。

8. 发明申请

US20090122600A1 NONVOLATILE MEMORY USING RESISTANCE MATERIAL 有权
标题翻译：使用电阻材料的非易失性存储器
公开(公告)号：US20090122600A1
公开(公告)日：2009-05-14
申请号：US12243578
申请日：2008-10-01
申请人： Joon-Yong Choi , Byung-Gil Choi
发明人： Joon-Yong Choi , Byung-Gil Choi
IPC分类号： G11C11/00 , G11C8/00 , G11C7/00
CPC分类号： G11C13/0069 , G11C7/18 , G11C8/14 , G11C13/0004 , G11C13/0023 , G11C13/0026 , G11C13/0028 , G11C2013/0078
摘要： A nonvolatile memory using a resistance material includes first and second memory-cell blocks having different block address information and each including a plurality of nonvolatile memory cells; a global bitline common to the first and second memory-cell blocks; first and second local bitlines corresponding to the first and second memory-cell blocks, respectively, and coupled to each other; and a common bitline selection circuit interposed between the first and second memory-cell blocks and coupled between the first and second local bitlines and the global bitline.
摘要翻译：使用电阻材料的非易失性存储器包括具有不同块地址信息并且各自包括多个非易失性存储单元的第一和第二存储单元块; 第一和第二存储单元块共同的全局位线; 分别对应于第一和第二存储单元块的第一和第二局部位线并彼此耦合; 以及插入在第一和第二存储单元块之间并耦合在第一和第二本地位线与全局位线之间的公共位线选择电路。

9. 发明授权

US08310891B2 Resistance variable memory device for protecting coupling noise 有权
标题翻译：用于保护耦合噪声的电阻可变存储器件
公开(公告)号：US08310891B2
公开(公告)日：2012-11-13
申请号：US12574227
申请日：2009-10-06
申请人： HoJung Kim , Joon-Yong Choi
发明人： HoJung Kim , Joon-Yong Choi
IPC分类号： G11C7/00
CPC分类号： G11C13/004 , G11C7/02 , G11C7/12 , G11C13/0004 , G11C13/0026 , G11C2013/0054 , G11C2213/72
摘要： The present invention relates to a resistance variable memory device, and more particularly, to a resistance variable memory device capable of preventing an effect of coupling noise. The resistance variable memory device includes: a memory cell connected to a bit line; a precharge circuit precharging the bit line in response to a precharge signal; a bias circuit providing a bias voltage to the bit line in response to a bias signal; and a control logic controlling the precharge signal and the bias signal. The control logic provides the bias signal to the bias circuit at a precharge interval. Accordingly, the resistance variable memory device according to the present invention can prevent an effect coupling noise.
摘要翻译：电阻变化存储装置技术领域本发明涉及一种电阻可变存储装置，更具体地，涉及一种能够防止耦合噪声影响的电阻变化存储装置。电阻变化存储装置包括：连接到位线的存储单元; 预充电电路响应于预充电信号预充电所述位线; 偏置电路，响应于偏置信号向位线提供偏置电压; 以及控制逻辑来控制预充电信号和偏置信号。控制逻辑以预充电间隔将偏置信号提供给偏置电路。因此，根据本发明的电阻变化存储装置可以防止耦合噪声的影响。

10. 发明授权

US08107275B2 Nonvolatile memory device using variable resistive element 有权
标题翻译：使用可变电阻元件的非易失性存储器件
公开(公告)号：US08107275B2
公开(公告)日：2012-01-31
申请号：US12630484
申请日：2009-12-03
申请人： Byung-Gil Choi , Joon-Yong Choi
发明人： Byung-Gil Choi , Joon-Yong Choi
IPC分类号： G11C11/00
CPC分类号： G11C5/063 , G11C8/10 , G11C8/14 , G11C13/00 , G11C13/0004 , G11C13/0028 , G11C13/004 , G11C2013/0045 , G11C2213/72
摘要： A nonvolatile memory device using a variable resistive element is provided. The nonvolatile memory device includes first and second nonvolatile memory cells. Word lines are coupled to the first and second nonvolatile memory cells. First and second bit lines are coupled to the first and second nonvolatile memory cells, respectively. A read circuit reads resistance levels of the first and second nonvolatile memory cells by providing first and second read bias currents of different levels to the first and second bit lines, respectively.
摘要翻译：提供了使用可变电阻元件的非易失性存储器件。非易失性存储器件包括第一和第二非易失性存储单元。字线耦合到第一和第二非易失性存储单元。第一和第二位线分别耦合到第一和第二非易失性存储器单元。读取电路通过分别向第一和第二位线提供不同电平的第一和第二读取偏置电流来读取第一和第二非易失性存储器单元的电阻电平。

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