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1. 发明授权

US10741571B2 Vertical memory devices and methods of manufacturing the same 有权
公开(公告)号：US10741571B2
公开(公告)日：2020-08-11
申请号：US15401486
申请日：2017-01-09
申请人： Young-Bae Yoon , Joong-Shik Shin , Kwang-Ho Kim , Hyun-Mog Park
发明人： Young-Bae Yoon , Joong-Shik Shin , Kwang-Ho Kim , Hyun-Mog Park
IPC分类号： H01L27/11565 , H01L27/11568 , H01L27/11578 , H01L27/11582 , H01L27/11575
摘要： A vertical memory device includes a channel, gate lines, and a cutting pattern, respectively, on a substrate. The channel extends in a first direction substantially perpendicular to an upper surface of the substrate. The gate lines are spaced apart from each other in the first direction. Each of the gate lines surrounds the channel and extends in a second direction substantially parallel to the upper surface of the substrate. The cutting pattern includes a first cutting portion extending in the first direction and cutting the gate lines, and a second cutting portion crossing the first cutting portion and merged with the first cutting portion.

2. 发明授权

US09223355B2 Latch system 有权
标题翻译：锁系统
公开(公告)号：US09223355B2
公开(公告)日：2015-12-29
申请号：US13201857
申请日：2009-02-28
申请人： Kwang Ho Kim
发明人： Kwang Ho Kim
IPC分类号： E05C1/02 , G06F1/16 , E05C1/08 , E05C1/12 , H05K5/00 , H05K7/00
CPC分类号： G06F1/1679 , E05C1/08 , Y10T292/096
摘要： A latch system employs momentum exchange impact damping. A latch is slideably arranged within a housing so that the latch can slide between a latch position and a release position. A damper spring urges a damper against a wedge of the latch. When a mechanical impact urges said latch toward the release position, the latch wedge impacts the damper so as to exchange momentum from the latch to the damper so that the latch remains in the latch position.
摘要翻译：闩锁系统采用动量交换冲击阻尼。闩锁可滑动地布置在壳体内，使得闩锁可以在闩锁位置和释放位置之间滑动。阻尼弹簧将阻尼器推向闩锁的楔形件。当机械冲击促使所述闩锁朝向释放位置时，闩锁楔撞击阻尼器，以便将动量从闩锁转换到阻尼器，使得闩锁保持在闩锁位置。

3. 发明授权

US08557629B1 Semiconductor device having overlapped via apertures 有权
公开(公告)号：US08557629B1
公开(公告)日：2013-10-15
申请号：US12959911
申请日：2010-12-03
申请人： Jin Seong Kim , Dong Joo Park , Kwang Ho Kim , Hee Yeoul Yoo , Jeong Wung Jeong
发明人： Jin Seong Kim , Dong Joo Park , Kwang Ho Kim , Hee Yeoul Yoo , Jeong Wung Jeong
IPC分类号： H01L21/00 , H01L31/0232 , H01L23/28
CPC分类号： H01L23/3128 , H01L23/49816 , H01L23/5386 , H01L24/14 , H01L24/17 , H01L25/105 , H01L2224/16225 , H01L2224/16235 , H01L2224/16238 , H01L2225/1023 , H01L2225/1058 , H01L2225/1076 , H01L2924/15311 , H01L2924/15331 , H01L2924/1815 , H01L2924/182 , H01L2924/18301
摘要： Disclosed is a semiconductor device having overlapped via apertures formed in an encapsulant to outwardly expose solder balls. When different types of semiconductor devices are electrically connected to the solder balls through the overlapped via apertures, flux or solder paste is unlikely to contact sidewall portions of the overlapped via apertures. Therefore, different types of semiconductor devices can be mounted with improved efficiency.

4. 发明申请

US20110299233A1 LATCH SYSTEM 有权
标题翻译：锁定系统
公开(公告)号：US20110299233A1
公开(公告)日：2011-12-08
申请号：US13201857
申请日：2009-02-28
申请人： Kwang Ho Kim
发明人： Kwang Ho Kim
IPC分类号： H05K5/02 , E05C1/08
CPC分类号： G06F1/1679 , E05C1/08 , Y10T292/096
摘要： A latch system employs momentum exchange impact damping. A latch is slicleably arranged within a housing so that the latch can slide between a latch position and a release position. A damper spring urges a damper against a wedge of the latch. When a mechanical impact urges said latch toward the release position, the latch wedge impacts the damper so as to exchange momentum from the latch to the damper so that the latch remains in the latch position.
摘要翻译：闩锁系统采用动量交换冲击阻尼。闩锁可拆卸地布置在壳体内，使得闩锁可以在闩锁位置和释放位置之间滑动。阻尼弹簧将阻尼器推向闩锁的楔形件。当机械冲击促使所述闩锁朝向释放位置时，闩锁楔撞击阻尼器，以便将动量从闩锁转换到阻尼器，使得闩锁保持在闩锁位置。

5. 发明申请

US20110276812A1 System On Chip, Devices Having The Same, and Method For Power Control of the SOC 有权
标题翻译：片上系统，具有相同功能的器件以及SOC功率控制方法
公开(公告)号：US20110276812A1
公开(公告)日：2011-11-10
申请号：US13103535
申请日：2011-05-09
申请人： Jae Gon Lee , Jang Ho Cho , Bong II Park , Kwang Ho Kim , Taek Kyun Shin , Dong Keun Kim , Jae Young Lee , Yung Hei Lee
发明人： Jae Gon Lee , Jang Ho Cho , Bong II Park , Kwang Ho Kim , Taek Kyun Shin , Dong Keun Kim , Jae Young Lee , Yung Hei Lee
IPC分类号： G06F1/26
CPC分类号： G06F1/26 , G06F1/3203 , G06F1/3287 , Y02D10/171
摘要： Disclosed is an integrated circuit device including a plurality of power domain blocks, which includes a core power domain block. A power control circuit is configured to control power supplied to each of the plurality of power domain blocks independently responsive to control communication from the core power domain block. The power control circuit includes a plurality of power clusters corresponding to the plurality of power domain blocks, respectively. The plurality of power clusters control power supplied to the plurality of power domain blocks, respectively, independently responsive to the control communication from the core power domain block.
摘要翻译：公开了一种包括多个功率域块的集成电路装置，其包括核心功率域块。功率控制电路被配置为独立地响应于来自核心功率域块的控制通信来控制提供给多个功率域块中的每一个的功率。功率控制电路分别包括与多个功率域块相对应的多个功率簇。多个功率群分别独立地响应于来自核心功率域块的控制通信来控制提供给多个功率域块的功率。

6. 发明申请

US20110276777A1 DATA STORAGE DEVICE AND RELATED METHOD OF OPERATION 有权
标题翻译：数据存储装置及相关操作方法
公开(公告)号：US20110276777A1
公开(公告)日：2011-11-10
申请号：US13096036
申请日：2011-04-28
申请人： Kyoung Lae CHO , Kwang Ho KIM , Jun Jin KONG , Jaehong KIM , Hong Rak SON
发明人： Kyoung Lae CHO , Kwang Ho KIM , Jun Jin KONG , Jaehong KIM , Hong Rak SON
IPC分类号： G06F12/10
CPC分类号： H03M7/30
摘要： A method of storing data in a storage medium of a data storage device comprises storing input data in the storage medium, and reading the input data from the storage medium and compressing the read data during a background operation of the data storage device.
摘要翻译：一种在数据存储装置的存储介质中存储数据的方法包括将输入数据存储在存储介质中，并且在数据存储装置的后台操作期间从存储介质读取输入数据并压缩读取的数据。

7. 发明授权

US08023320B2 Resistance-change random access memory device including memory cells connected to discharge elements 有权
标题翻译：电阻变化随机存取存储器件包括连接到放电元件的存储单元
公开(公告)号：US08023320B2
公开(公告)日：2011-09-20
申请号：US12591238
申请日：2009-11-13
申请人： Hye-jin Kim , Kwang-ho Kim , Young-kug Moon , Byung-gil Choi
发明人： Hye-jin Kim , Kwang-ho Kim , Young-kug Moon , Byung-gil Choi
IPC分类号： G11C11/00
CPC分类号： G11C13/0023 , G11C7/12 , G11C8/12 , G11C13/00 , G11C13/0004 , G11C13/0026 , G11C13/0028
摘要： A resistance-change random access memory device includes a resistance-change memory cell array having a plurality of resistance-change memory cells, where a plurality of word lines are connected to respective first terminals of the plurality of resistance-change memory cells. A plurality of bit lines are disposed perpendicular to the word lines and connected to respective second terminals of the plurality of resistance-change memory cells. The device also includes a plurality of discharge elements that are capable of connecting or disconnecting respective bit lines from a discharge voltage, where the discharge elements connect the respective bit lines to the discharge voltage before write and read operations.
摘要翻译：电阻变化随机存取存储器件包括具有多个电阻变化存储单元的电阻变化存储单元阵列，其中多个字线连接到多个电阻变化存储单元的相应第一端子。多个位线垂直于字线布置并连接到多个电阻变化存储单元的相应的第二端子。该装置还包括能够将各个位线与放电电压连接或断开的多个放电元件，其中放电元件在写入和读取操作之前将各个位线连接到放电电压。

8. 发明申请

US20110002169A1 Bad Column Management with Bit Information in Non-Volatile Memory Systems 审中-公开
标题翻译：在非易失性存储器系统中具有位信息的错误列管理
公开(公告)号：US20110002169A1
公开(公告)日：2011-01-06
申请号：US12498220
申请日：2009-07-06
申请人： Yan Li , Kwang-ho Kim , Frank W. Tsai , Aldo Bottelli
发明人： Yan Li , Kwang-ho Kim , Frank W. Tsai , Aldo Bottelli
IPC分类号： G11C16/06 , G11C29/00 , G11C7/10 , G11C16/04
CPC分类号： G11C29/00 , G11C16/10 , G11C29/808
摘要： Column based defect management techniques are presented. Each column of the memory has an associated isolation latch or register whose value indicates whether the column is defective, but in addition to this information, for columns marked as defective, additional information is used to indicate whether the column as a whole is to be treated as defective, or whether just individual bits of the column are defective. The defective elements can then be re-mapped to a redundant element at either the appropriate bit or column level based on the data. When a column is bad, but only on the bit level, the good bits can still be used for data, although this may be done at a penalty of under programming for some bits, as is described further below. A self contained Built In Self Test (BIST) flow constructed to collect the bit information through a set of column tests is also described. Based on this information, the bad bits can be extracted and re-grouped into bytes by the controller or on the memory to more efficiently use the column redundancy area.
摘要翻译：介绍了基于列的缺陷管理技术。存储器的每一列都有一个相关联的隔离锁存器或寄存器，其值表示列是否有缺陷，但是除了该信息之外，对于标记为有缺陷的列，还使用附加信息来指示是否要对列进行整体处理作为缺陷，或者列的单个位是否有缺陷。然后，可以基于该数据将有缺陷的元素重新映射到适当位或列级的冗余元件。当列是坏的但是仅在位电平时，好的位仍然可以用于数据，尽管这可以在对于某些位的编程的惩罚下完成，如下面进一步描述的。还描述了通过一组列测试来构建的用于收集位信息的自建内置自检（BIST）流程。基于该信息，可以通过控制器或存储器提取坏位并将其重新分组为字节，以更有效地使用列冗余区域。

9. 发明申请

US20100124105A1 VARIABLE RESISTANCE MEMORY DEVICE AND SYSTEM 有权
标题翻译：可变电阻存储器件和系统
公开(公告)号：US20100124105A1
公开(公告)日：2010-05-20
申请号：US12693005
申请日：2010-01-25
申请人： Qi WANG , Kwang-Jin LEE , Woo-Yeong CHO , Taek-Sung KIM , Kwang-Ho KIM , Hyun-Ho CHOI , Yong-Jun LEE , Hye-Jin KIM
发明人： Qi WANG , Kwang-Jin LEE , Woo-Yeong CHO , Taek-Sung KIM , Kwang-Ho KIM , Hyun-Ho CHOI , Yong-Jun LEE , Hye-Jin KIM
IPC分类号： G11C11/00 , G11C8/00
CPC分类号： G11C8/12 , G11C11/005 , G11C11/56 , G11C11/5678 , G11C13/0004 , G11C13/0023 , G11C13/0028 , G11C13/0069 , G11C16/0483 , G11C2013/0078 , G11C2213/71
摘要： Disclosed is a semiconductor memory device including a memory cell array having a plurality of variable resistance memory cells divided into first and second areas. An I/O circuit is configured to access the memory cell array under the control of control logic so as to access the first or second area in response to an external command. The I/O circuit accesses the first area using a memory cell unit and the second area using a page unit.
摘要翻译：公开了一种半导体存储器件，包括具有分成第一和第二区域的多个可变电阻存储器单元的存储单元阵列。 I / O电路被配置为在控制逻辑的控制下访问存储单元阵列，以响应于外部命令访问第一或第二区域。 I / O电路使用存储单元单元访问第一区域，并且使用页面单元访问第二区域。

10. 发明授权

US07711340B2 Phase locked loop and method thereof 有权
标题翻译：锁相环及其方法
公开(公告)号：US07711340B2
公开(公告)日：2010-05-04
申请号：US11656472
申请日：2007-01-23
申请人： Kwang-ho Kim , Je-kook Kim
发明人： Kwang-ho Kim , Je-kook Kim
IPC分类号： H04B1/06 , H04Q7/20
CPC分类号： H03L7/099 , H03L7/0891 , H03L7/10 , H03L7/18 , H03L2207/06
摘要： A phase locked loop and method thereof are provided. The example phase locked loop may include a loop filter filtering a charge pump output signal to generate a voltage signal and a voltage-controlled oscillator configured to operate in a given one of a plurality of frequency zones, the given frequency zone within which the voltage-controller oscillator is operating in being based on a voltage level of the voltage signal, the voltage-controlled oscillator outputting an oscillator signal at a frequency corresponding to the voltage level of the voltage signal output from the loop filter. The example method may include filtering a charge pump output signal to generate a voltage signal and outputting an oscillator signal at a frequency corresponding to a voltage level of the voltage signal, the frequency of the oscillator signal based on which of a plurality of frequency zones is currently selected, the currently selected frequency zone being selected based on the voltage level of the voltage signal.
摘要翻译：提供了一种锁相环及其方法。示例性锁相环可以包括滤波电荷泵输出信号以产生电压信号的环路滤波器，以及被配置为在多个频率区域中给定的一个频率区域中工作的压控振荡器，该给定频率区域中的电压 - 控制振荡器基于电压信号的电压电平工作，压控振荡器以与从环路滤波器输出的电压信号的电压电平相对应的频率输出振荡器信号。示例性方法可以包括过滤电荷泵输出信号以产生电压信号，并以与电压信号的电压电平对应的频率输出振荡器信号，基于多个频率区域中的哪个频率区域的振荡器信号的频率当前选择的，当前选择的频率区域是基于电压信号的电压电平被选择的。

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