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    • 1. 发明申请
    • Method of fabricating ridge type waveguide integrated semiconductor optical device
    • 脊型波导集成半导体光器件的制造方法
    • US20060104583A1
    • 2006-05-18
    • US11122998
    • 2005-05-06
    • Jong KimHyun KimKang KimOh KwonEun SimKwang Oh
    • Jong KimHyun KimKang KimOh KwonEun SimKwang Oh
    • G02B6/10
    • G02B6/136G02B6/122G02B2006/12097
    • Provided is a method of fabricating a ridge type waveguide integrated semiconductor optical device. The method includes: separating a substrate into an active waveguide region and a passive waveguide region and selectively epitaxial-growing an active layer and a passive layer in the active waveguide region and the passive waveguide region, respectively, such that the active layer and the passive layer are vertically aligned with each other; sequentially forming a capping layer and an electrode connection layer on the active layer and the passive layer; forming a first insulating layer pattern on a predetermined region of the electrode connection layer disposed in the active waveguide region and simultaneously, forming a second insulating layer pattern on a predetermined region of the electrode connection layer disposed in the passive waveguide region; forming a shallow ridge type active waveguide and a shallow ridge type passive waveguide by performing an etching process using the first and second insulating layer patterns as etch masks until the capping layer is etched to a predetermined depth; and forming a passivation pattern on the entire surface of the shallow ridge type active waveguide and forming a deep ridge type passive waveguide by performing an etching process using the second insulating layer pattern as an etch mask until the substrate is etched to a predetermined depth.
    • 提供了一种制造脊型波导集成半导体光学器件的方法。 该方法包括:将衬底分离成有源波导区域和无源波导区域,并分别在有源波导区域和无源波导区域中选择性地外延生长有源层和无源层,使得有源层和被动 层彼此垂直对准; 在有源层和被动层上依次形成覆盖层和电极连接层; 在设置在有源波导区域中的电极连接层的预定区域上形成第一绝缘层图案,并同时在布置在无源波导区域中的电极连接层的预定区域上形成第二绝缘层图案; 通过使用第一和第二绝缘层图案作为蚀刻掩模进行蚀刻处理,直到将覆盖层蚀刻到预定深度来形成浅脊型有源波导和浅脊型无源波导; 并且在浅脊型有源波导的整个表面上形成钝化图案,并通过使用第二绝缘层图案作为蚀刻掩模进行蚀刻处理形成深脊型无源波导,直到基板被蚀刻到预定深度。
    • 2. 发明申请
    • Tunable external cavity laser diode using variable optical deflector
    • 可调谐外腔激光二极管使用可变光学偏转器
    • US20060029119A1
    • 2006-02-09
    • US11029784
    • 2004-12-21
    • Kwang OhOh KwonKang KimJong KimHyun Kim
    • Kwang OhOh KwonKang KimJong KimHyun Kim
    • H01S3/08
    • H01S5/141G02B6/29308G02B6/2931G02B6/29313H01S5/005H01S5/026H01S5/101H01S5/143
    • Provided is a tunable external cavity laser diode using a variable optical deflector wherein the variable optical deflector, in which a refractive index varies according to an electrical signal, is arranged in a triangular shape between a concave diffraction grating and a reflective mirror. Since a resonant frequency is changed using the electrical signal rather than the mechanical movement, the stable operation and continuous high-speed tenability may be enabled. In addition, when the tunable external cavity laser diode according to the present invention is implemented in an InP/InGaAsP/InP slab waveguide, a variable time determined by the carrier lifetime may be reduced to several nanoseconds or less, the miniaturization is enabled, and the manufacturing costs are significantly reduced due to the process simplification. Moreover, when the concave diffraction grating is designed based on a silica (or polymer) based slab waveguide, the fabrication may be performed even by a lithography process having low resolution, thereby enhancing reproducibility and uniformity of the diffraction grating, and accordingly reducing the manufacturing costs.
    • 提供了一种可调谐的外腔激光二极管,其使用可变光学偏转器,其中折射率根据电信号变化的可变光学偏转器在凹面衍射光栅和反射镜之间布置成三角形。 由于使用电信号而不是机械运动来改变谐振频率,因此可以实现稳定的运行和连续的高速可靠性。 此外,当根据本发明的可调谐外腔激光二极管在InP / InGaAsP / InP平板波导中实现时,由载流子寿命确定的可变时间可以减少到几纳秒或更小,可实现小型化,并且 由于过程简化,制造成本显着降低。 此外,当基于基于二氧化硅(或聚合物)的平板波导设计凹面衍射光栅时,即使通过具有低分辨率的光刻工艺也可以进行制造,从而提高衍射光栅的再现性和均匀性,并因此降低制造 费用
    • 9. 发明申请
    • DLL phase detection using advanced phase equal
    • DLL相位检测使用高级相位相等
    • US20050262373A1
    • 2005-11-24
    • US10848261
    • 2004-05-18
    • Kang Kim
    • Kang Kim
    • H03L7/081H03L7/085G06F1/12
    • H03L7/0814H03L7/085
    • A system and method are disclosed to generate and terminate clock shift modes during initialization of a synchronous circuit (e.g., a delay-locked loop or DLL). Upon initialization, the DLL is entered into a ForceSL (Force Shift Left) mode and an On1x mode (i.e., left shifting on each clock cycle). The feedback clock that tracks the phase of the reference clock (which, in turn, is derived from the system clock) is initially delayed in a coarse phase detector prior to applying it to the coarse phase detection window. Two delayed versions of the feedback clock are sampled by the reference clock to generate a pair of phase information signals, which are then used to establish an advanced phase equal (APHEQ) signal. The APHEQ signal advances onset of the PHEQ (phase equalization) phase and is used to terminate the ForceSL and On1x modes, thereby preventing wrong ForceSL exit due to clock jitter or feedback path overshooting during On1x exit. The avoidance of wrong ForceSL exit and On1x overshooting problems further results in faster DLL locking time.
    • 公开了一种在同步电路(例如延迟锁定环或DLL)的初始化期间产生和终止时钟移位模式的系统和方法。 在初始化时,DLL进入ForceSL(左移强制)模式和一个1 x模式(即在每个时钟周期左移)。 在将粗略相位检测器应用于粗略相位检测窗口之前,跟踪基准时钟的相位(反过来来自系统时钟)的反馈时钟最初在粗略相位检测器中被延迟。 反馈时钟的两个延迟版本由参考时钟采样,以产生一对相位信息信号,然后将其用于建立高级相位相等(APHEQ)信号。 APHEQ信号提前启动PHEQ(相位均衡)阶段,并用于终止ForceSL和On 1 x模式,从而防止在On 1 x退出时由于时钟抖动或反馈路径过冲引起的错误的ForceSL退出。 避免错误的ForceSL退出和On 1 x超调问题进一步导致更快的DLL锁定时间。