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1. 发明授权

US5706228A Method for operating a memory array 失效
标题翻译：操作存储器阵列的方法
公开(公告)号：US5706228A
公开(公告)日：1998-01-06
申请号：US603939
申请日：1996-02-20
申请人： Kuo-Tung Chang , Craig A. Cavins , Ko-Min Chang , Bruce L. Morton , George L. Espinor
发明人： Kuo-Tung Chang , Craig A. Cavins , Ko-Min Chang , Bruce L. Morton , George L. Espinor
IPC分类号： G11C16/04 , G11C16/10 , G11C11/40
CPC分类号： G11C16/3427 , G11C16/0433 , G11C16/10
摘要： A memory array (25) having a selected memory cell (10) and an unselected memory cell (30) is programmed and read. Each memory cell in the memory array (25) contains an isolation transistor (22) and a floating gate transistor (23). To program the selected memory cell (10), programming voltages are applied to a control gate line (21), a drain line (14), an isolation line (19), and a source line (12). To reduce the effects of the drain disturb problem, a gate terminal (32) of the unselected memory cell (30) is held at a positive voltage. To read selected memory cell (10), a read voltage is applied to an isolation gate line (31) of unselected memory cell (30) which insures that the unselected memory cell (30) does not conduct or contribute to leakage current and power consumption during the read operation.
摘要翻译：具有选定的存储单元（10）和未选择的存储单元（30）的存储器阵列（25）被编程和读取。存储器阵列（25）中的每个存储单元包含隔离晶体管（22）和浮动栅极晶体管（23）。为了对所选择的存储单元（10）进行编程，将编程电压施加到控制栅极线（21），漏极线（14），隔离线（19）和源极线（12）。为了减小漏极干扰问题的影响，未选择的存储单元（30）的栅极端子（32）被保持在正电压。为了读取所选择的存储单元（10），读取电压被施加到未选择存储单元（30）的隔离栅极线（31），其确保未选择的存储单元（30）不导通或有助于漏电流和功耗在读操作期间。

2. 发明授权

US5646060A Method for making an EEPROM cell with isolation transistor 失效
标题翻译：用隔离晶体管制造EEPROM单元的方法
公开(公告)号：US5646060A
公开(公告)日：1997-07-08
申请号：US471619
申请日：1995-05-30
申请人： Ko-Min Chang , Danny Pak-Chum Shum , Kuo-Tung Chang
发明人： Ko-Min Chang , Danny Pak-Chum Shum , Kuo-Tung Chang
IPC分类号： G11C17/00 , G11C16/04 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L27/115 , H01L29/7883
摘要： An EEPROM cell (40) includes a floating gate transistor (47) and an isolation transistor (45). Both a floating gate (48) and an isolation gate (46) are formed on a tunnel dielectric (44) within the cell. The isolation gate is coupled to a doped source region (52) of the floating gate transistor. The isolation transistor is not biased during a program operation of the cell, enabling a thin tunnel dielectric (less than 120 angstroms) to be used beneath all portions of both gates within the cell. Thus, the need for both a conventional tunnel dielectric and a gate dielectric is eliminated. The cell tolerates over-erasure, can be programmed at low programming voltages, and has good current drive due to the thin tunnel dielectric throughout the cell.
摘要翻译： EEPROM单元（40）包括浮栅晶体管（47）和隔离晶体管（45）。浮动栅极（48）和隔离栅极（46）均形成在电池内的隧道电介质（44）上。隔离栅极耦合到浮栅晶体管的掺杂源极区（52）。在单元的编程操作期间，隔离晶体管不被偏置，使得能够在单元内的两个栅极的所有部分下方使用薄的隧道电介质（小于120埃）。因此，消除了对常规隧道电介质和栅极电介质的需要。电池容忍过度擦除，可以在低编程电压下编程，并且由于整个电池中的薄隧道电介质而具有良好的电流驱动。

3. 发明授权

US5422846A Nonvolatile memory having overerase protection 失效
标题翻译：非易失性存储器具有过度保护
公开(公告)号：US5422846A
公开(公告)日：1995-06-06
申请号：US222066
申请日：1994-04-04
申请人： Kuo-Tung Chang , Bruce L. Morton , Ko-Min Chang
发明人： Kuo-Tung Chang , Bruce L. Morton , Ko-Min Chang
IPC分类号： G11C16/16 , G11C11/40
CPC分类号： G11C16/16
摘要： A nonvolatile memory (20) includes an array of floating gate transistors (22) organized as rows and columns. Word lines of adjacent rows are coupled together to form shared word lines. In one embodiment, a coupling transistor (56-61) is used to couple the sources of the floating gate transistors (36, 39-55) of a row to a predetermined potential in response to the shared word line being selected. The sources of the unselected floating gate transistors of the array (22) are isolated. In another embodiment, an inverter (113, 114, and 115) couples the sources to zero volts in response to the shared word line being selected. The conductivity of the floating gate transistors (36, 39-55) is controlled in response to the logic state of the shared word lines to ensure that unselected cells do not adversely affect the operation of the nonvolatile memory.
摘要翻译：非易失性存储器（20）包括以行和列组织的浮栅晶体管阵列（22）。相邻行的字线被耦合在一起以形成共享字线。在一个实施例中，耦合晶体管（56-61）用于响应于所选择的共享字线将行的浮置栅晶体管（36,39-55）的源耦合到预定电位。阵列（22）的未选择的浮栅晶体管的源极被隔离。在另一个实施例中，响应于所选择的共享字线，反相器（113,114和115）将源耦合到零伏特。响应于共享字线的逻辑状态来控制浮栅晶体管（36,39-55）的电导率，以确保未选择的单元不会不利地影响非易失性存储器的操作。

4. 发明授权

US5467308A Cross-point eeprom memory array 失效
标题翻译：交叉点eeprom存储器阵列
公开(公告)号：US5467308A
公开(公告)日：1995-11-14
申请号：US223354
申请日：1994-04-05
申请人： Kuo-Tung Chang , Ko-Min Chang
发明人： Kuo-Tung Chang , Ko-Min Chang
IPC分类号： G11C16/04 , H01L21/8246 , H01L27/115 , G11C11/40
CPC分类号： H01L27/11568 , G11C16/0491 , H01L27/115
摘要： A cross-point EEPROM memory array includes a semiconductor substrate (10) having first and second bit-lines (32, 34) spaced apart by a channel region (36). A control gate electrode (24) is formed by a portion of a control gate line, which overlies a first portion of the channel region (36) and is separated therefrom by an ONO layer (17). A select gate electrode (40) is formed by a portion of a select gate line disposed on the substrate (10) perpendicular to the control gate line. Individual cells in the array are programmed by injecting electrons using source-side injection into trapping sites (19) in the silicon nitride layer (14) of the ONO layer (17). The cells in the array are erased by electron tunneling through the top silicon dioxide layer (16) of the ONO layer (17), and are dissipated in the control gate electrode (24). Improved operating performance is obtained, in part, by fabricating the first silicon dioxide layer (12) of the ONO layer (17) to a greater thickness than the top silicon dioxide layer (16) of the ONO layer (17).
摘要翻译：交叉点EEPROM存储器阵列包括具有由沟道区域（36）间隔开的第一和第二位线（32,34）的半导体衬底（10）。控制栅电极（24）由控制栅极线的一部分形成，该部分覆盖在沟道区（36）的第一部分上并由ONO层（17）分离。选择栅极（40）由垂直于控制栅线的基板（10）上的选择栅线的一部分形成。通过使用源侧注入将电子注入到ONO层（17）的氮化硅层（14）中的捕获位点（19）中来编程阵列中的各个单元。通过电子隧道穿过ONO层（17）的顶部二氧化硅层（16）擦除阵列中的电池，并在控制栅电极（24）中消散。部分地通过将ONO层（17）的第一二氧化硅层（12）制造成比ONO层（17）的顶部二氧化硅层（16）更大的厚度来获得改进的操作性能。

5. 发明授权

US5969383A Split-gate memory device and method for accessing the same 失效
标题翻译：分闸存储器件及其访问方法
公开(公告)号：US5969383A
公开(公告)日：1999-10-19
申请号：US876576
申请日：1997-06-16
申请人： Kuo-Tung Chang , Ko-Min Chang , Wei-Ming Chen , Keith Forbes , Douglas R. Roberts
发明人： Kuo-Tung Chang , Ko-Min Chang , Wei-Ming Chen , Keith Forbes , Douglas R. Roberts
IPC分类号： G11C16/04 , H01L21/28 , H01L21/8247 , H01L27/115 , H01L29/423 , H01L29/788 , H01L29/792
CPC分类号： H01L21/28282 , H01L29/42324 , H01L29/7885 , H01L29/792
摘要： An EEPROM device includes a split-gate FET (10) having a source (36), a drain (22), a select gate (16) adjacent the drain (22), and a control gate (32) adjacent the source (36). When programming the split-gate FET (10), electrons are accelerated in a portion of a channel region (38) between the select gate (16) and the control gate (32), and then injected into a nitride layer (24) of an ONO stack (25) underlying the control gate (32). The split-gate FET (10) is erased by injecting holes from the channel region (38) into the charge nitride layer (24). When reading data from the split-gate FET (10), a reading voltage is applied to the drain (22) adjacent the select gate (16). Data is then read from the split-gate FET (10) by sensing a current flowing in a bit line coupled to the drain (22).
摘要翻译： EEPROM器件包括具有源极（36），漏极（22），与漏极（22）相邻的选择栅极（16））和邻近源极（36）的控制栅极（32）的分离栅极FET（10））。当对分离栅极FET（10）进行编程时，在选择栅极（16）和控制栅极（32）之间的沟道区域（38）的一部分中电子被加速，然后注入氮化物层（24）位于控制门（32）下方的ONO堆叠（25）。通过从沟道区（38）将空穴注入到电荷氮化物层（24）中，分裂栅FET（10）被擦除。当从分离栅极FET（10）读取数据时，读取电压被施加到与选择栅极（16）相邻的漏极（22）。然后通过感测在耦合到漏极（22）的位线中流动的电流，从分离栅极FET（10）读取数据。

6. 发明授权

US5471422A EEPROM cell with isolation transistor and methods for making and operating the same 失效
标题翻译：具有隔离晶体管的EEPROM单元及其制造和操作的方法
公开(公告)号：US5471422A
公开(公告)日：1995-11-28
申请号：US225868
申请日：1994-04-11
申请人： Ko-Min Chang , Danny P. Shum , Kuo-Tung Chang
发明人： Ko-Min Chang , Danny P. Shum , Kuo-Tung Chang
IPC分类号： G11C17/00 , G11C16/04 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792 , G11C11/34 , H01L29/68
CPC分类号： H01L27/115 , H01L29/7883
摘要： An EEPROM cell (40) includes a floating gate transistor (47) and an isolation transistor (45). Both a floating gate (48) and an isolation gate (46) are formed on a tunnel dielectric (44) within the cell. The isolation gate is coupled to a doped source region (52) of the floating gate transistor. The isolation transistor is not biased during a program operation of the cell, enabling a thin tunnel dielectric (less than 120 angstroms) to be used beneath all portions of both gates within the cell. Thus, the need for both a conventional tunnel dielectric and a gate dielectric is eliminated. The cell tolerates over-erasure, can be programmed at low programming voltages, and has good current drive due to the thin tunnel dielectric throughout the cell.
摘要翻译： EEPROM单元（40）包括浮栅晶体管（47）和隔离晶体管（45）。浮动栅极（48）和隔离栅极（46）均形成在电池内的隧道电介质（44）上。隔离栅极耦合到浮栅晶体管的掺杂源极区（52）。在单元的编程操作期间，隔离晶体管不被偏置，使得能够在单元内的两个栅极的所有部分之下使用薄的隧道电介质（小于120埃）。因此，消除了对常规隧道电介质和栅极电介质的需要。电池容忍过度擦除，可以在低编程电压下编程，并且由于整个电池中的薄隧道电介质而具有良好的电流驱动。

7. 发明授权

US08921155B2 Resistive random access memory (RAM) cell and method for forming 有权
标题翻译：电阻随机存取存储器（RAM）单元及其形成方法
公开(公告)号：US08921155B2
公开(公告)日：2014-12-30
申请号：US13085217
申请日：2011-04-12
申请人： Feng Zhou , Ko-Min Chang , Cheong Min Hong
发明人： Feng Zhou , Ko-Min Chang , Cheong Min Hong
IPC分类号： H01L21/027 , H01L45/00
CPC分类号： H01L45/08 , H01L45/1233 , H01L45/146 , H01L45/1633 , H01L45/1675
摘要： A resistive random access memory cell uses a substrate and includes a gate stack over the substrate. The gate stack includes a first copper layer over the substrate, a copper oxide layer over the first copper layer, and a second copper layer over the copper oxide layer.
摘要翻译：电阻式随机存取存储器单元使用衬底并且在衬底上包括栅极堆叠。栅极堆叠包括在衬底上的第一铜层，在第一铜层上方的氧化铜层和氧化铜层上的第二铜层。

8. 发明授权

US06791883B2 Program and erase in a thin film storage non-volatile memory 有权
标题翻译：在薄膜存储非易失性存储器中编程和擦除
公开(公告)号：US06791883B2
公开(公告)日：2004-09-14
申请号：US10178658
申请日：2002-06-24
申请人： Craig T. Swift , Jane A. Yater , Alexander B. Hoefler , Ko-Min Chang , Erwin J. Prinz , Bruce L. Morton
发明人： Craig T. Swift , Jane A. Yater , Alexander B. Hoefler , Ko-Min Chang , Erwin J. Prinz , Bruce L. Morton
IPC分类号： G11C1600
CPC分类号： G11C16/0466
摘要： A non-volatile memory having a thin film dielectric storage element is programmed by hot carrier injection (HCI) and erased by tunneling. The typical structure for the memory cells for this type of memory is silicon, oxide, nitride, oxide, and silicon (SONOS). The hot carrier injection provides relatively fast programming for SONOS, while the tunneling provides for erase that avoids the difficulties with the hot hole erase (HHE) type erase that generally accompanies hot carrier injection for programming. HHE is significantly more damaging to dielectrics leading to reliability issues. HHE also has a relatively narrow area of erasure that may not perfectly match the pattern for the HCI programming leaving an incomplete erasure. The tunnel erase effectively covers the entire area so there is no concern about incomplete erase. Although tunnel erase is slower than HHE, erase time is generally less critical in a system operation than is programming time.
摘要翻译：具有薄膜电介质存储元件的非易失性存储器通过热载流子注入（HCI）编程并通过隧道擦除。这种存储器的存储单元的典型结构是硅，氧化物，氮化物，氧化物和硅（SONOS）。热载波注入为SONOS提供相对快速的编程，而隧道提供擦除，避免了通常伴随热载流子注入进行编程的热孔擦除（HHE）类型擦除的困难。 HHE对电介质的破坏性更大，导致可靠性问题。 HHE还具有相对较窄的擦除区域，可能不完全匹配HCI编程的模式，从而导致不完整的擦除。隧道擦除有效地覆盖整个区域，所以不用担心不完全擦除。虽然隧道擦除比HHE慢，但擦除时间在系统操作中通常不如编程时间那么重要。

9. 发明授权

US5605855A Process for fabricating a graded-channel MOS device 失效
标题翻译：用于制造渐变通道MOS器件的工艺
公开(公告)号：US5605855A
公开(公告)日：1997-02-25
申请号：US395339
申请日：1995-02-28
申请人： Ko-Min Chang , Marius Orlowski , Craig Swift , Shih-Wei Sun , Shiang-Chyong Luo
发明人： Ko-Min Chang , Marius Orlowski , Craig Swift , Shih-Wei Sun , Shiang-Chyong Luo
IPC分类号： H01L29/78 , H01L21/265 , H01L21/336 , H01L29/10 , H01L21/8234
CPC分类号： H01L29/66583 , H01L21/2652 , H01L29/1045 , H01L29/1083 , H01L29/66537 , H01L29/66553
摘要： A process for fabricating a graded-channel MOS device includes the formation of a masking layer (16) on the surface of a semiconductor substrate (10) and separated from the surface by a gate oxide layer (12). A first doped region (22) is formed in a channel region (20) of the semiconductor substrate (10) using the masking layer (16) as a doping mask. A second doped region (24) is formed in the channel region (20) and extends from the principal surface (14) of the semiconductor substrate (10) to the first doped region (22). A gate electrode (34) is formed within an opening (18) in the masking layer (16) and aligned to the channel region (20). Upon removal of the masking layer (16) source and drain regions (36, 38) are formed in the semiconductor substrate (10) and aligned to the gate electrode (34).
摘要翻译：用于制造渐变沟道MOS器件的工艺包括在半导体衬底（10）的表面上形成掩模层（16），并通过栅氧化层（12）从表面分离。使用掩模层（16）作为掺杂掩模，在半导体衬底（10）的沟道区（20）中形成第一掺杂区（22）。第二掺杂区域（24）形成在沟道区域（20）中并且从半导体衬底（10）的主表面（14）延伸到第一掺杂区域（22）。栅极电极（34）形成在掩模层（16）的开口（18）内，并与沟道区域（20）对准。在去除掩模层（16）时，源极和漏极区（36,38）形成在半导体衬底（10）中并与栅电极（34）对齐。

10. 发明授权

US5258949A Nonvolatile memory with enhanced carrier generation and method for programming the same 失效
标题翻译：具有增强载波生成的非易失性存储器和用于编程的方法
公开(公告)号：US5258949A
公开(公告)日：1993-11-02
申请号：US620813
申请日：1990-12-03
申请人： Ko-Min Chang , Ming-Bing Chang
发明人： Ko-Min Chang , Ming-Bing Chang
IPC分类号： G11C17/00 , G11C16/04 , G11C16/12 , H01L21/8246 , H01L21/8247 , H01L27/112 , H01L29/788 , H01L29/792 , G11C13/00
CPC分类号： G11C16/12 , H01L29/7885
摘要： Programming speed of a nonvolatile memory is improved by enhancing carrier generation. In one form, a nonvolatile memory has a control gate which overlies a channel region in a substrate. A floating gate overlies a portion of the channel region and is positioned between the substrate and the control gate. A source and a drain are formed in the substrate, being displaced by the channel region. A first programming voltage is applied to the drain to create an electric field at a junction between the drain and channel region. Current is forced into the source and through the substrate in order to enhance carrier generation at the junction between the drain and channel region, thereby increasing an electric field at the junction. A second programming voltage, having a ramp shaped leading edge, is applied to the control gate to increase the electrical field and to program the memory to a predetermined logic state.
摘要翻译：通过增强载体生成来提高非易失性存储器的编程速度。在一种形式中，非易失性存储器具有覆盖在衬底中的沟道区域的控制栅极。浮动栅极覆盖沟道区的一部分并位于衬底和控制栅之间。源极和漏极形成在衬底中，被沟道区域置换。将第一编程电压施加到漏极，以在漏极和沟道区域之间的结处产生电场。电流被迫进入源极并通过衬底，以便增强在漏极和沟道区域之间的结处的载流子产生，从而增加了结处的电场。具有斜坡形状的前沿的第二编程电压被施加到控制栅极以增加电场并将存储器编程到预定的逻辑状态。

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