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1. 发明申请

US20160172199A1 NANOCRYSTAL MEMORY AND METHODS FOR FORMING SAME 有权
标题翻译：纳米晶体存储器及其形成方法
公开(公告)号：US20160172199A1
公开(公告)日：2016-06-16
申请号：US14568155
申请日：2014-12-12
申请人： Cheong Min Hong , Euhngi Lee
发明人： Cheong Min Hong , Euhngi Lee
IPC分类号： H01L21/28
CPC分类号： H01L21/28282 , H01L21/28273 , H01L27/11517 , H01L27/11563 , H01L29/42328 , H01L29/42332 , H01L29/7881
摘要： A charge-storing device includes a charge-storing layer including nanocrystals. The nanocrystals are formed by a deposition technique incorporating deuterated hydrides. The deuterated hydride can be used to form an amorphous semiconductor material that is annealed to form nanoparticles to be incorporated into the charge-storing layer.
摘要翻译：电荷存储装置包括具有纳米晶体的电荷存储层。纳米晶体通过结合氘代氢化物的沉积技术形成。氘代氢化物可用于形成非晶半导体材料，其被退火以形成要并入电荷存储层的纳米颗粒。

2. 发明申请

US20160035848A1 METHOD OF FORMING SPLIT GATE MEMORY WITH IMPROVED RELIABILITY 有权
标题翻译：形成具有改进的可靠性的分离器存储器的方法
公开(公告)号：US20160035848A1
公开(公告)日：2016-02-04
申请号：US14446796
申请日：2014-07-30
申请人： Cheong Min Hong , Konstantin V. Loiko , Jane A. Yater
发明人： Cheong Min Hong , Konstantin V. Loiko , Jane A. Yater
IPC分类号： H01L29/423 , H01L29/792 , H01L29/08 , H01L21/265 , H01L29/10 , H01L29/788 , H01L29/66
CPC分类号： H01L29/42328 , H01L21/26513 , H01L21/26586 , H01L29/0847 , H01L29/1033 , H01L29/42344 , H01L29/66825 , H01L29/66833 , H01L29/788 , H01L29/7881 , H01L29/792 , H01L29/7923
摘要： A first doped region extends from a top surface of a substrate to a first depth. Implanting into the first doped region forms a second doped region of a second conductivity type. The second doped region extends from the top surface to a second depth that is less than the first depth. A split gate NVM structure has select and control gates over the second doped region. A drain region of the second conductivity type is formed adjacent to the select gate. A source region of the second conductivity type is formed adjacent to the control gate. Angled implants into the second doped region form a third doped region of the first conductivity type under a portion of the select gate and a fourth doped region of the first conductivity type under a portion of the control gate. The drain and source regions adjoin the third and fourth regions.
摘要翻译：第一掺杂区域从衬底的顶表面延伸到第一深度。植入第一掺杂区域形成第二导电类型的第二掺杂区域。第二掺杂区域从顶表面延伸到小于第一深度的第二深度。分裂门NVM结构在第二掺杂区域上具有选择和控制栅极。形成与选择栅极相邻的第二导电类型的漏极区域。第二导电类型的源极区域形成为与控制栅极相邻。进入第二掺杂区域的倾斜植入物形成在选择栅极的一部分下的第一导电类型的第三掺杂区域和在控制栅极的一部分下的第一导电类型的第四掺杂区域。漏极和源极区域与第三和第四区域相邻。

3. 发明授权

US09082650B2 Integrated split gate non-volatile memory cell and logic structure 有权
标题翻译：集成分离门非易失性存储单元和逻辑结构
公开(公告)号：US09082650B2
公开(公告)日：2015-07-14
申请号：US13971987
申请日：2013-08-21
申请人： Asanga H. Perera , Cheong Min Hong , Sung-Taeg Kang , Byoung W. Min , Jane A. Yater
发明人： Asanga H. Perera , Cheong Min Hong , Sung-Taeg Kang , Byoung W. Min , Jane A. Yater
IPC分类号： H01L21/336 , H01L27/115 , H01L29/66 , H01L21/28 , H01L29/423
CPC分类号： H01L27/11517 , H01L21/28273 , H01L27/11534 , H01L29/42332 , H01L29/66545 , H01L29/66825
摘要： A method of making a semiconductor structure includes forming a select gate and a charge storage layer in an NVM region. A spacer select gate is formed by depositing a conformal layer followed by an etch back. A patterned etch results in leaving a portion of the charge storage layer over the select gate. A dummy gate structure formed in a logic region has a dummy gate surrounded by an insulating layer. Performing chemical polishing results in the top surface of the charge storage layer being coplanar with top surface of the dummy gate structure. Replacing a portion of the dummy gate structure with a metal logic gate which includes a further chemical mechanical polishing results in the top surface of the charge storage layer being coplanar with the metal logic gate.
摘要翻译：制造半导体结构的方法包括在NVM区域中形成选择栅极和电荷存储层。间隔选择栅极通过沉积保形层，随后进行回蚀而形成。图案化蚀刻导致将电荷存储层的一部分留在选择栅上。形成在逻辑区域中的虚拟栅极结构具有由绝缘层包围的虚拟栅极。执行化学抛光导致电荷存储层的顶表面与虚拟栅极结构的顶表面共面。用包括另外的化学机械抛光的金属逻辑门来替代虚拟栅极结构的一部分导致电荷存储层的顶表面与金属逻辑门共面。

4. 发明授权

US09054208B2 Methods for forming contact landing regions in split-gate non-volatile memory (NVM) cell arrays 有权
标题翻译：在分闸门非易失性存储器（NVM）单元阵列中形成接触着陆区域的方法
公开(公告)号：US09054208B2
公开(公告)日：2015-06-09
申请号：US14022646
申请日：2013-09-10
申请人： Jane A. Yater , Cheong Min Hong , Sung-Taeg Kang
发明人： Jane A. Yater , Cheong Min Hong , Sung-Taeg Kang
IPC分类号： H01L21/3205 , H01L29/788 , H01L29/66 , H01L27/115
CPC分类号： H01L27/11568 , H01L27/11524 , H01L27/11565 , H01L27/1157 , H01L29/42344 , H01L29/66825 , H01L29/7881 , H01L29/792
摘要： Methods and related structures are disclosed for forming contact landing regions in split-gate NVM (non-volatile memory) systems. A dummy select gate structure is formed while also forming select gates for split-gate NVM cells. A control gate layer is formed over the select gates and the dummy select gate structure, as well as an intervening charge storage layer. The control gate material will fill in gaps between the select gate material and the dummy select gate material. A non-patterned spacer etch is then used to etch the control gate layer to form a contact landing region associated with the dummy select gate structure while also forming spacer control gates for the split-gate NVM cells. The disclosed embodiments provide improved (e.g., more planar) contact landing regions without requiring additional processing steps and without increasing the pitch of the resulting NVM cell array.
摘要翻译：公开了用于在分闸NVM（非易失性存储器）系统中形成接触着陆区域的方法和相关结构。形成虚拟选择栅结构，同时形成分闸NVM单元的选择栅极。在选择栅极和虚拟选择栅极结构上形成控制栅极层，以及中间电荷存储层。控制栅极材料将填充选择栅极材料和虚拟选择栅极材料之间的间隙。然后使用非图案化间隔物蚀刻来蚀刻控制栅极层以形成与虚拟选择栅极结构相关联的接触着色区域，同时还形成用于分离栅极NVM单元的间隔物控制栅极。所公开的实施例提供改进的（例如更平坦的）接触着陆区域，而不需要额外的处理步骤，而不增加所得到的NVM单元阵列的间距。

5. 发明申请

US20150054050A1 INTEGRATED SPLIT GATE NON-VOLATILE MEMORY CELL AND LOGIC DEVICE 有权
标题翻译：集成分离栅非易失性存储单元和逻辑器件
公开(公告)号：US20150054050A1
公开(公告)日：2015-02-26
申请号：US13972372
申请日：2013-08-21
申请人： ASANGA H. PERERA , Cheong Min Hong , Sung-Taeg Kang , Janes A. Yater
发明人： ASANGA H. PERERA , Cheong Min Hong , Sung-Taeg Kang , Janes A. Yater
IPC分类号： H01L27/115 , H01L29/66
CPC分类号： H01L29/66825 , H01L21/28273 , H01L27/11534 , H01L29/42332
摘要： A method of making a semiconductor structure includes forming a select gate and a charge storage layer in an NVM region. A control gate is formed by depositing a conformal layer followed by an etch back. A patterned etch results in leaving a portion of the charge storage layer over the select gate and under the control gate and to remove the charge storage layer from the logic region. A logic gate structure formed in a logic region has a metal work function surrounded by an insulating layer.
摘要翻译：制造半导体结构的方法包括在NVM区域中形成选择栅极和电荷存储层。通过沉积保形层，接着进行回蚀而形成控制栅极。图案化的蚀刻导致将电荷存储层的一部分留在选择栅极上并在控制栅极之下并且从逻辑区域去除电荷存储层。形成在逻辑区域中的逻辑门结构具有被绝缘层包围的金属功函数。

6. 发明授权

US08953378B2 Split gate programming 有权
标题翻译：分割门编程
公开(公告)号：US08953378B2
公开(公告)日：2015-02-10
申请号：US13536307
申请日：2012-06-28
申请人： Cheong Min Hong , Sung-Taeg Kang
发明人： Cheong Min Hong , Sung-Taeg Kang
IPC分类号： G11C11/34
CPC分类号： G11C16/0466 , G11C16/10 , G11C16/3459
摘要： A method for programming a split gate memory cell includes performing a first programming of the split gate memory cell in a first programming cycle of the split gate memory cell; and, subsequent to the performing the first programming of the split gate memory cell, performing a second programming of the split gate memory cell in the first programming cycle, wherein the first programming is characterized as one of source-side injection (SSI) programming and channel-initiated secondary electron (CHISEL) programming, and the second programming is characterized as the other of SSI programming and CHISEL programming.
摘要翻译：用于对分割门存储器单元进行编程的方法包括在分离栅极存储单元的第一编程周期中执行分离栅极存储单元的第一编程; 并且在执行所述分离栅极存储器单元的第一编程之后，在所述第一编程周期中执行所述分离栅极存储单元的第二编程，其中所述第一编程被表征为源侧注入（SSI）编程之一，通道启动的二次电子（CHISEL）编程，第二个编程被表征为SSI编程和CHISEL编程中的另一个。

7. 发明授权

US08932925B1 Split-gate non-volatile memory (NVM) cell and device structure integration 有权
标题翻译：分离门非易失性存储器（NVM）单元和器件结构集成
公开(公告)号：US08932925B1
公开(公告)日：2015-01-13
申请号：US13973549
申请日：2013-08-22
申请人： Cheong Min Hong , Karthik Ramanan
发明人： Cheong Min Hong , Karthik Ramanan
IPC分类号： H01L29/792 , H01L27/06 , H01L29/78 , H01L29/66 , H01L21/02
CPC分类号： H01L29/792 , H01L21/02601 , H01L21/28273 , H01L27/0629 , H01L27/11541 , H01L29/42328 , H01L29/42332 , H01L29/66181 , H01L29/66825 , H01L29/66833
摘要： A method includes forming a first conductive layer over a substrate in a first region and second region of the substrate; patterning the first conductive layer to form a select gate in the first region and to remove the first conductive layer from the second region; forming a charge storage layer over the select gate and the substrate in the first region and over the substrate in the second region; forming a second conductive layer over the charge storage layer in the first and second regions; and patterning the second conductive layer and charge storage layer to form a control gate overlapping the select gate in the first region, wherein a first portion of the charge storage layer remains between the select gate and control gate, and to form an electrode in the second region, wherein a second portion of the charge storage layer remains between the electrode and substrate.
摘要翻译：一种方法包括在衬底的第一区域和第二区域中在衬底上形成第一导电层; 图案化第一导电层以在第一区域中形成选择栅极并从第二区域去除第一导电层; 在所述第一区域中的所述选择栅极和所述衬底上方并在所述第二区域中的所述衬底上方形成电荷存储层; 在第一和第二区域中的电荷存储层上形成第二导电层; 以及图案化所述第二导电层和电荷存储层以形成与所述第一区域中的所述选择栅极重叠的控制栅极，其中所述电荷存储层的第一部分保留在所述选择栅极和控制栅极之间，并且在所述第二区域中形成电极区域，其中电荷存储层的第二部分保留在电极和衬底之间。

8. 发明申请

US20150001606A1 METHODS AND STRUCTURES FOR A SPLIT GATE MEMORY CELL STRUCTURE 有权
标题翻译：一种分离栅细胞结构的方法和结构
公开(公告)号：US20150001606A1
公开(公告)日：2015-01-01
申请号：US13929924
申请日：2013-06-28
申请人： Cheong Min Hong , Sung-Taeg Kang
发明人： Cheong Min Hong , Sung-Taeg Kang
IPC分类号： H01L29/423 , H01L29/788 , H01L29/49 , H01L29/66 , H01L29/792
CPC分类号： H01L29/42328 , H01L21/28273 , H01L21/28282 , H01L21/28518 , H01L27/105 , H01L27/11536 , H01L29/42332 , H01L29/45 , H01L29/66825 , H01L29/66833 , H01L29/7881 , H01L29/7882
摘要： A method of forming a split gate memory cell structure using a substrate includes forming a gate stack comprising a select gate and a dielectric portion overlying the select gate. A charge storage layer is formed over the substrate including over the gate stack. A first sidewall spacer of conductive material is formed along a first sidewall of the gate stack extending past a top of the select gate. A second sidewall spacer of dielectric material is formed along the first sidewall on the first sidewall spacer. A portion of the first sidewall spacer is silicided using the second sidewall spacer as a mask whereby silicide does not extend to the charge storage layer.
摘要翻译：使用衬底形成分离栅极存储单元结构的方法包括形成包括选择栅极和覆盖在选择栅极上的电介质部分的栅极堆叠。电荷存储层形成在包括在栅叠层上的衬底上。导电材料的第一侧壁间隔物沿着延伸经过选择栅极的顶部的栅极堆叠的第一侧壁形成。电介质材料的第二侧壁间隔物沿着第一侧壁间隔件上的第一侧壁形成。使用第二侧壁间隔物作为掩模使第一侧壁间隔物的一部分硅化，由此硅化物不延伸到电荷存储层。

9. 发明申请

US20130320285A1 FIELD FOCUSING FEATURES IN A RERAM CELL 有权
标题翻译： RERAM细胞中的场聚焦特征
公开(公告)号：US20130320285A1
公开(公告)日：2013-12-05
申请号：US13486690
申请日：2012-06-01
申请人： Feng Zhou , Frank K. Baker, JR. , Ko-Min Chang , Cheong Min Hong
发明人： Feng Zhou , Frank K. Baker, JR. , Ko-Min Chang , Cheong Min Hong
IPC分类号： H01L45/00
CPC分类号： H01L45/16 , H01L45/04 , H01L45/1233 , H01L45/1246 , H01L45/1273 , H01L45/146 , H01L45/1675
摘要： A resistive random access memory (ReRAM) cell comprising a first conductive electrode and a dielectric storage material layer over the first conductive electrode. The dielectric storage material layer is conducive to the formation of conductive filaments during the application of a filament forming voltage to the cell. The cell includes a second conductive electrode over the dielectric storage material layer and a layer of conductive nanoclusters (911, 1211) including a plurality of nanoclusters in contact with the dielectric storage material layer and in contact with the first conductive electrode or the second conductive electrode.
摘要翻译：一种电阻随机存取存储器（ReRAM）单元，包括在第一导电电极上的第一导电电极和介电存储材料层。电介质存储材料层有利于在将细丝形成电压施加到电池时形成导电细丝。电池包括位于介电存储材料层上的第二导电电极和包括与电介质存储材料层接触并与第一导电电极或第二导电电极接触的多个纳米团簇的导电纳米团簇（911,1211）。

10. 发明申请

US20120261636A1 RESISTIVE RANDOM ACCESS MEMORY (RAM) CELL AND METHOD FOR FORMING 有权
标题翻译：电容随机访问存储器（RAM）单元和形成方法
公开(公告)号：US20120261636A1
公开(公告)日：2012-10-18
申请号：US13085217
申请日：2011-04-12
申请人： Feng Zhou , Ko-Min Chang , Cheong Min Hong
发明人： Feng Zhou , Ko-Min Chang , Cheong Min Hong
IPC分类号： H01L45/00 , H01L21/02
CPC分类号： H01L45/08 , H01L45/1233 , H01L45/146 , H01L45/1633 , H01L45/1675
摘要： A resistive random access memory cell uses a substrate and includes a gate stack over the substrate. The gate stack includes a first copper layer over the substrate, a copper oxide layer over the first copper layer, and a second copper layer over the copper oxide layer.
摘要翻译：电阻式随机存取存储器单元使用衬底并且在衬底上包括栅极堆叠。栅极堆叠包括在衬底上的第一铜层，在第一铜层上方的氧化铜层和氧化铜层上的第二铜层。

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