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1. 发明授权

US06493276B2 Word line boost circuit 有权
标题翻译：字线升压电路
公开(公告)号：US06493276B2
公开(公告)日：2002-12-10
申请号：US09355653
申请日：1999-08-02
申请人： Yu Shen Lin , Chun-Hsiung Hung , Ray-Lin Wan
发明人： Yu Shen Lin , Chun-Hsiung Hung , Ray-Lin Wan
IPC分类号： G11C700
CPC分类号： G11C8/08 , G11C5/145
摘要： An improved word line boost circuit suitable for use on integrated circuits such as flash memory devices includes a two step boosting circuit with a floating circuit node. A first circuit provides an initial boost of the output voltage from a precharged voltage. Part of the first circuit is floated, lessening a load on a second circuit. Then, the second circuit provides a second boost of the output voltage with increased power efficiency. A time delay separates the onset of the second boosting operation from the onset of the first boosting operation so as to define a two-step boost.
摘要翻译：适用于诸如闪存器件的集成电路的改进的字线升压电路包括具有浮动电路节点的两级升压电路。第一电路从预充电电压提供输出电压的初始升压。第一个电路的一部分浮起来，减轻了第二个电路的负载。然后，第二电路以提高的功率效率提供输出电压的第二升压。时间延迟将第二升压操作的开始与第一升压操作的开始分开，以便定义两步升压。

2. 发明授权

US06573780B2 Four-phase charge pump with lower peak current 有权
标题翻译：具有较低峰值电流的四相电荷泵
公开(公告)号：US06573780B2
公开(公告)日：2003-06-03
申请号：US09355654
申请日：1999-08-02
申请人： Yu Shen Lin , Chun-Hsiung Hung , Ray-Lin Wan
发明人： Yu Shen Lin , Chun-Hsiung Hung , Ray-Lin Wan
IPC分类号： G05F110
CPC分类号： H02M3/073 , H02M2003/075
摘要： A four-phase charge pump circuit suitable for use on integrated circuits, such as flash memory devices, includes circuitry that drives charge pump nodes in two components separated by a time delay. The two components can be triggered by edges from the clocks that control the timing of the charge pump. Driving the charge pump nodes in two components separated by a delay decreases the peak current of the charge pump and improves noise characteristics of a voltage supply or ground line connected to the charge pump.
摘要翻译：适用于集成电路（例如闪存器件）的四相电荷泵电路包括驱动由时间延迟分开的两个部件中的电荷泵节点的电路。这两个组件可以由控制电荷泵定时的时钟边沿触发。驱动由延迟分开的两个部件中的电荷泵节点会降低电荷泵的峰值电流，并改善连接到电荷泵的电源或接地线的噪声特性。

3. 发明授权

US07595682B2 Multi-stage charge pump without threshold drop with frequency modulation between embedded mode operations 有权
标题翻译：多级电荷泵，无嵌入式模式操作之间的频率调制门限下降
公开(公告)号：US07595682B2
公开(公告)日：2009-09-29
申请号：US11064920
申请日：2005-02-24
申请人： Yufe Feng Lin , Yu Shen Lin , Roger Chen , Chun Hsiung Hung
发明人： Yufe Feng Lin , Yu Shen Lin , Roger Chen , Chun Hsiung Hung
IPC分类号： G05F1/10
CPC分类号： H02M3/073 , H02M2003/075
摘要： A multimode charge pump circuit has a single charge pump that is responsive to a set of clock signals. The set of clock signals is provided in a first mode with a variable frequency according to a first function of the supply potential and temperature, and in a second mode with a variable frequency according to a second function of the supply potential and temperature. Circuitry configures all of the plurality of stages in series during the first mode in order to produce a higher voltage output, and configures a subset of the plurality of stages in series, while disabling the other stages, during the second mode in order to produce a lower voltage output. A precharge circuit is provided that operates as a supply node in the second mode, and as a precharge/clamp in the first mode.
摘要翻译：多模电荷泵电路具有响应于一组时钟信号的单个电荷泵。根据电源电位和温度的第一功能，在第一模式下以一个可变频率提供一组时钟信号，并且根据电源电位和温度的第二功能以第二种可变频率提供时钟信号。电路在第一模式期间配置串联的所有多个级，以便产生较高的电压输出，并且在第二模式期间在禁用其它级的同时，在多个级的串联中配置子集，以产生较低的电压输出。提供预充电电路，其在第二模式中作为供电节点工作，并且作为第一模式中的预充电/钳位。

4. 发明授权

US07339846B2 Method and apparatus for reading data from nonvolatile memory 有权
标题翻译：从非易失性存储器读取数据的方法和装置
公开(公告)号：US07339846B2
公开(公告)日：2008-03-04
申请号：US11457686
申请日：2006-07-14
申请人： Yung Feng Lin , Yu Shen Lin
发明人： Yung Feng Lin , Yu Shen Lin
IPC分类号： G11C7/00
CPC分类号： G11C7/12 , G11C7/22 , G11C16/24 , G11C16/28
摘要： Roughly described, a memory includes first and second target memory cells in a plurality of electrically adjacent memory cells all sharing a word line. The two target memory cells are separated from each other by at least one additional memory cell, and first current path terminals of the target memory cells bracket second current path terminals of the target memory cells electrically along the word line. The two target memory cells are read by connecting the first current path terminals of the two target memory cells to ground, precharging the second current path terminals of the two target memory cells to respective precharged states, and while both second current path terminals are in their respective precharged states, initiating a sense operation to read both the first and second target memory cells substantially simultaneously.
摘要翻译：粗略地描述，存储器包括在多个电相邻的存储器单元中的共享字线的第一和第二目标存储器单元。两个目标存储器单元由至少一个附加存储器单元彼此分离，并且目标存储器单元的第一电流路径端子沿着字线电连接目标存储器单元的第二电流路径端子。通过将两个目标存储器单元的第一电流路径端子连接到地来读取两个目标存储器单元，将两个目标存储器单元的第二电流路径端子预充电到各自的预充电状态，并且当第二电流路径端子处于它们相应的预充电状态，开始基本上同时读取第一和第二目标存储器单元的感测操作。

5. 发明授权

US07218563B1 Method and apparatus for reading data from nonvolatile memory 有权
标题翻译：从非易失性存储器读取数据的方法和装置
公开(公告)号：US07218563B1
公开(公告)日：2007-05-15
申请号：US11282541
申请日：2005-11-18
申请人： Yung Feng Lin , Yu Shen Lin
发明人： Yung Feng Lin , Yu Shen Lin
IPC分类号： G11C7/00
CPC分类号： G11C7/12 , G11C16/24 , G11C16/26
摘要： Various embodiments address the problem of efficiently reading data from nonvolatile memory. Nonvolatile memory circuit, method, and manufacturing method embodiments relate to a virtual ground array of nonvolatile memory cells which are read by precharging the drains of multiple nonvolatile memory cells and measuring the resulting currents. Power consumption and read margins are improved by reading multiple cells. Unnecessary bit line precharging can be avoided.
摘要翻译：各种实施例解决了从非易失性存储器有效读取数据的问题。非易失性存储器电路，方法和制造方法实施例涉及通过预充电多个非易失性存储器单元的漏极并测量所得到的电流来读取的非易失性存储单元的虚拟接地阵列。通过读取多个单元可以提高功耗和读取边距。可以避免不必要的位线预充电。

6. 发明申请

US20080013379A1 METHOD AND APPARATUS FOR READING DATA FROM NONVOLATILE MEMORY 有权
标题翻译：从非易失性存储器读取数据的方法和装置
公开(公告)号：US20080013379A1
公开(公告)日：2008-01-17
申请号：US11457686
申请日：2006-07-14
申请人： Yung Feng Lin , Yu Shen Lin
发明人： Yung Feng Lin , Yu Shen Lin
IPC分类号： G11C11/34 , G11C16/06 , G11C7/02 , G11C7/00
CPC分类号： G11C7/12 , G11C7/22 , G11C16/24 , G11C16/28
摘要： Roughly described, a memory includes first and second target memory cells in a plurality of electrically adjacent memory cells all sharing a word line. The two target memory cells are separated from each other by at least one additional memory cell, and first current path terminals of the target memory cells bracket second current path terminals of the target memory cells electrically along the word line. The two target memory cells are read by connecting the first current path terminals of the two target memory cells to ground, precharging the second current path terminals of the two target memory cells to respective precharged states, and while both second current path terminals are in their respective precharged states, initiating a sense operation to read both the first and second target memory cells substantially simultaneously.
摘要翻译：粗略地描述，存储器包括在多个电相邻的存储器单元中的共享字线的第一和第二目标存储器单元。两个目标存储器单元由至少一个附加存储器单元彼此分离，并且目标存储器单元的第一电流路径端子沿着字线电连接目标存储器单元的第二电流路径端子。通过将两个目标存储器单元的第一电流路径端子连接到地来读取两个目标存储器单元，将两个目标存储器单元的第二电流路径端子预充电到各自的预充电状态，并且当第二电流路径端子处于它们相应的预充电状态，开始基本上同时读取第一和第二目标存储器单元的感测操作。

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