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1. 发明授权

US5273923A Process for fabricating an EEPROM cell having a tunnel opening which overlaps field isolation regions 失效
标题翻译：用于制造具有与场隔离区重叠的隧道开口的EEPROM单元的工艺
公开(公告)号：US5273923A
公开(公告)日：1993-12-28
申请号：US773791
申请日：1991-10-09
申请人： Ko-Min Chang , Clinton C. K. Kuo , Ming-Bing Chang
发明人： Ko-Min Chang , Clinton C. K. Kuo , Ming-Bing Chang
IPC分类号： G11C17/00 , H01L21/8247 , H01L29/788 , H01L29/792 , H01L21/302 , H01L21/38 , H01L27/115
CPC分类号： H01L27/11521 , H01L27/11524 , H01L29/7883
摘要： An EEPROM cell (10) has a tunnel opening (28) which overlaps both an active region (12) and field isolation regions (14). A tunnel area (30), which is that portion of the cell in which electrons tunnel through a tunnel dielectric (32) to charge or discharge a floating gate (22) during device operation, is defined as the overlapped portion of the tunnel opening (28) and the active region (12). By having the tunnel opening (28) larger than the tunnel area (30), etch processes used to pattern the opening in a gate dielectric (26) are more easily controlled and the active region area beneath the floating gate is reduced. The EEPROM cell (10) has a tunnel area which is limited in size by lithographic resolution capabilities rather than by limitations in dielectric etch processes. The tunnel features increase a capacitance coupling ratio of the cell.
摘要翻译： EEPROM单元（10）具有与有源区域（12）和场隔离区域（14）重叠的隧道开口（28）。隧道区域（30）是在设备操作期间电子穿过隧道电介质（32）充电或放电浮动栅极（22）的电池部分被定义为隧道开口的重叠部分（30） 28）和有源区（12）。通过使隧道开口（28）大于隧道区域（30），更容易控制用于对栅极电介质（26）中的开口进行图案化的蚀刻工艺，并且浮动栅极下方的有源区域面积减小。 EEPROM单元（10）具有通过光刻分辨能力限制尺寸的隧道区域，而不是通过电介质蚀刻工艺的限制。隧道特征增加了电池的电容耦合比。

2. 发明授权

US5130769A Nonvolatile memory cell 失效
标题翻译：非易失性存储单元
公开(公告)号：US5130769A
公开(公告)日：1992-07-14
申请号：US700837
申请日：1991-05-16
申请人： Clinton C. K. Kuo , Ko-Min Chang
发明人： Clinton C. K. Kuo , Ko-Min Chang
IPC分类号： G11C17/00 , H01L21/8247 , H01L29/423 , H01L29/788 , H01L29/792
CPC分类号： H01L29/42368 , H01L29/7885
摘要： A floating gate is utilized which has two portions. A first portion overlies the channel region formed between the source and drain. The control gate overlies this portion of the floating gate and the remaining portion of the channel region forming an enhancement transistor. The second portion of the floating gate extends from the first portion over a thin oxide tunnel area of the source. An additional diode implant forming a junction with the drain region is provided to regulate the current flow through the drain, particularly during erasure.
摘要翻译：使用一个浮动栅极，它有两个部分。第一部分覆盖形成在源极和漏极之间的沟道区域。控制栅极覆盖浮置栅极的该部分，并且沟道区域的剩余部分形成增强晶体管。浮动栅极的第二部分从源极的薄氧化物隧道区域上的第一部分延伸。提供形成与漏极区的结的另外的二极管注入，以调节通过漏极的电流，特别是在擦除期间。

3. 发明授权

US5474947A Nonvolatile memory process 失效
标题翻译：非易失性存储过程
公开(公告)号：US5474947A
公开(公告)日：1995-12-12
申请号：US172984
申请日：1993-12-27
申请人： Ko-Min Chang , Bruce L. Morton , Henry Y. Choe , Clinton C. K. Kuo
发明人： Ko-Min Chang , Bruce L. Morton , Henry Y. Choe , Clinton C. K. Kuo
IPC分类号： H01L21/8247
CPC分类号： H01L27/11517
摘要： A process for fabricating an improved nonvolatile memory device includes the formation of a control gate electrode (70) which overlies a floating gate electrode (42) and is separated therefrom by an inter-level-dielectric layer (62). The control gate electrode (70) and the underlying floating gate electrode (42) form a stacked gate structure (72) located in the active region (44) of a semiconductor substrate (40). An electrically insulating sidewall spacer (54) is formed at the edges of the floating gate electrode (42) and electrically isolates the control gate (70) from the semiconductor substrate (40). During the fabrication process, implanted memory regions (56, 58) are formed in the active region (44) prior to the formation of control gate electrode (70). A word-line (68) and the control gate (70) are formed by anisotropic etching of a semiconductor layer (66), which is deposited to overlie inter-level-dielectric layer (62). During the etching process, inter-level-dielectric layer (62) prevents the removal of surface portions of semiconductor substrate (40).
摘要翻译：一种用于制造改进的非易失性存储器件的方法包括形成覆盖在浮栅电极（42）上的控制栅电极（70），并通过层间电介质层（62）与其分开。控制栅电极（70）和底层浮栅电极（42）形成位于半导体衬底（40）的有源区（44）中的层叠栅结构（72）。在浮栅电极（42）的边缘处形成电绝缘的侧壁间隔物（54），并将控制栅极（70）与半导体衬底（40）电隔离。在制造过程中，在形成控制栅电极（70）之前，在有源区（44）中形成植入的存储区（56,58）。通过各向异性蚀刻形成字线（68）和控制栅极（70），半导体层（66）沉积到层间电介质层（62）上。在蚀刻过程中，层间电介质层（62）防止去除半导体衬底（40）的表面部分。

4. 发明授权

US5357476A Apparatus and method for erasing a flash EEPROM 失效
标题翻译：擦除闪存EEPROM的装置和方法
公开(公告)号：US5357476A
公开(公告)日：1994-10-18
申请号：US69327
申请日：1993-06-01
申请人： Clinton C. K. Kuo , Ko-Min Chang , Henry Y. Choe
发明人： Clinton C. K. Kuo , Ko-Min Chang , Henry Y. Choe
IPC分类号： G11C16/16 , G11C16/34 , G11C11/34
CPC分类号： G11C16/3409 , G11C16/16 , G11C16/3404
摘要： A flash EEPROM array (22) is erased and a threshold voltage distribution of the erased flash EEPROM cells (36, 39-46) is converged to within a predetermined voltage range by using a two-step erasing procedure. In the first step, flash EEPROM array (22) is electrically bulk erased using a conventional bulk erase procedure. Electrons are tunneled from the floating gate (38) to the source, causing cells (36, 39-46) to have a relatively low threshold voltage. In the second step, the threshold voltage distribution of the array (22) is converged to within the predetermined voltage range by grounding the source and drain of each cell (36, 39-46), while concurrently applying a high positive voltage to the control gate (27) of each cell (36, 39-46). Some electrons are tunneled back to the floating gate (38), thus converging the threshold voltage distribution to within a predetermined range.
摘要翻译：闪存EEPROM阵列（22）被擦除，并且擦除的快闪EEPROM单元（36,39-46）的阈值电压分布通过使用两步擦除过程而被收敛到预定电压范围内。在第一步中，使用传统的大容量擦除程序，电子体积擦除快闪EEPROM阵列（22）。电子从浮动栅极（38）隧穿到源极，导致电池（36,39-46）具有相对低的阈值电压。在第二步骤中，通过使每个单元（36,39-46）的源极和漏极接地而将阵列（22）的阈值电压分布收敛到预定电压范围内，同时向控制器施加高正电压（36,39-46）的门（27）。一些电子被隧穿回到浮动栅极（38），从而将阈值电压分布会聚到预定范围内。

5. 发明授权

US5949706A Static random access memory cell having a thin film transistor (TFT) pass gate connection to a bit line 有权
标题翻译：具有薄膜晶体管（TFT）的静态随机存取存储器单元将栅极连接到位线
公开(公告)号：US5949706A
公开(公告)日：1999-09-07
申请号：US236914
申请日：1999-01-26
申请人： Ko-Min Chang , Bruce L. Morton , Clinton C. K. Kuo , Keith E. Witek , Kent J. Cooper
发明人： Ko-Min Chang , Bruce L. Morton , Clinton C. K. Kuo , Keith E. Witek , Kent J. Cooper
IPC分类号： G11C7/12 , G11C8/08 , G11C11/404 , G11C11/412 , G11C16/04 , H01L21/8242 , H01L21/8247 , H01L27/06 , H01L27/108 , H01L27/115 , G11C11/00 , H01L27/11
CPC分类号： H01L27/10873 , G11C11/404 , G11C11/412 , G11C16/0433 , G11C7/12 , G11C8/08 , H01L27/0688 , H01L27/115 , H01L27/11517 , H01L27/11551 , H01L27/108 , H01L27/10891 , Y10S257/903
摘要： A memory circuit and method of formation uses a transmission gate (24) as a select gate. The transmission gate (24) contains a transistor (30) which is an N-channel transistor and a transistor (28) which is a P-channel transistor. The transistors (28 and 30) are electrically connected in parallel. The use of the transmission gate (24) as a select gate allows reads and writes to occur to a memory cell storage device (i.e. a capacitor (32), a floating gate (22), etc.) without a significant voltage drop occurring across the transmission gate. In addition, EEPROM technology is more compatible with EPROM/flash technology when using a transmission gate as a select gate within EEPROM devices.
摘要翻译：存储电路和形成方法使用传输门（24）作为选择栅极。传输门（24）包含作为N沟道晶体管的晶体管（30）和作为P沟道晶体管的晶体管（28）。晶体管（28和30）并联电连接。传输门（24）作为选择栅极的使用允许对存储器单元存储设备（即，电容器（32），浮动栅极（22）等））进行读取和写入，而不会发生跨越显着的电压降传输门。此外，当EEPROM设备中使用传输门作为选择门时，EEPROM技术更能兼容EPROM /闪存技术。

6. 发明授权

US5898619A Memory cell having a plural transistor transmission gate and method of formation 失效
标题翻译：具有多个晶体管传输门的存储单元和形成方法
公开(公告)号：US5898619A
公开(公告)日：1999-04-27
申请号：US242993
申请日：1994-05-16
申请人： Ko-Min Chang , Bruce L. Morton , Clinton C. K. Kuo , Keith E. Witek , Kent J. Cooper
发明人： Ko-Min Chang , Bruce L. Morton , Clinton C. K. Kuo , Keith E. Witek , Kent J. Cooper
IPC分类号： G11C7/12 , G11C8/08 , G11C11/404 , G11C11/412 , G11C16/04 , H01L21/8242 , H01L21/8247 , H01L27/06 , H01L27/108 , H01L27/115 , G11C11/22 , G11C11/24
CPC分类号： H01L27/10873 , G11C11/404 , G11C11/412 , G11C16/0433 , G11C7/12 , G11C8/08 , H01L27/0688 , H01L27/115 , H01L27/11517 , H01L27/11551 , H01L27/108 , H01L27/10891 , Y10S257/903
摘要： A memory circuit and method of formation uses a transmission gate (24) as a select gate. The transmission gate (24) contains a transistor (30) which is an N-channel transistor and a transistor (28) which is a P-channel transistor. The transistors (28 and 30) are electrically connected in parallel. The use of the transmission gate (24) as a select gate allows reads and writes to occur to a memory cell storage device (i.e. a capacitor (32), a floating gate (22), etc.) without a significant voltage drop occurring across the transmission gate. In addition, EEPROM technology is more compatible with EPROM/flash technology when using a transmission gate as a select gate within EEPROM devices.
摘要翻译：存储电路和形成方法使用传输门（24）作为选择栅极。传输门（24）包含作为N沟道晶体管的晶体管（30）和作为P沟道晶体管的晶体管（28）。晶体管（28和30）并联电连接。传输门（24）作为选择栅极的使用允许对存储器单元存储设备（即，电容器（32），浮动栅极（22）等））进行读取和写入，而不会发生跨越显着的电压降传输门。此外，当EEPROM设备中使用传输门作为选择门时，EEPROM技术更能兼容EPROM /闪存技术。

7. 发明授权

US5258949A Nonvolatile memory with enhanced carrier generation and method for programming the same 失效
标题翻译：具有增强载波生成的非易失性存储器和用于编程的方法
公开(公告)号：US5258949A
公开(公告)日：1993-11-02
申请号：US620813
申请日：1990-12-03
申请人： Ko-Min Chang , Ming-Bing Chang
发明人： Ko-Min Chang , Ming-Bing Chang
IPC分类号： G11C17/00 , G11C16/04 , G11C16/12 , H01L21/8246 , H01L21/8247 , H01L27/112 , H01L29/788 , H01L29/792 , G11C13/00
CPC分类号： G11C16/12 , H01L29/7885
摘要： Programming speed of a nonvolatile memory is improved by enhancing carrier generation. In one form, a nonvolatile memory has a control gate which overlies a channel region in a substrate. A floating gate overlies a portion of the channel region and is positioned between the substrate and the control gate. A source and a drain are formed in the substrate, being displaced by the channel region. A first programming voltage is applied to the drain to create an electric field at a junction between the drain and channel region. Current is forced into the source and through the substrate in order to enhance carrier generation at the junction between the drain and channel region, thereby increasing an electric field at the junction. A second programming voltage, having a ramp shaped leading edge, is applied to the control gate to increase the electrical field and to program the memory to a predetermined logic state.
摘要翻译：通过增强载体生成来提高非易失性存储器的编程速度。在一种形式中，非易失性存储器具有覆盖在衬底中的沟道区域的控制栅极。浮动栅极覆盖沟道区的一部分并位于衬底和控制栅之间。源极和漏极形成在衬底中，被沟道区域置换。将第一编程电压施加到漏极，以在漏极和沟道区域之间的结处产生电场。电流被迫进入源极并通过衬底，以便增强在漏极和沟道区域之间的结处的载流子产生，从而增加了结处的电场。具有斜坡形状的前沿的第二编程电压被施加到控制栅极以增加电场并将存储器编程到预定的逻辑状态。

8. 发明授权

US08921155B2 Resistive random access memory (RAM) cell and method for forming 有权
标题翻译：电阻随机存取存储器（RAM）单元及其形成方法
公开(公告)号：US08921155B2
公开(公告)日：2014-12-30
申请号：US13085217
申请日：2011-04-12
申请人： Feng Zhou , Ko-Min Chang , Cheong Min Hong
发明人： Feng Zhou , Ko-Min Chang , Cheong Min Hong
IPC分类号： H01L21/027 , H01L45/00
CPC分类号： H01L45/08 , H01L45/1233 , H01L45/146 , H01L45/1633 , H01L45/1675
摘要： A resistive random access memory cell uses a substrate and includes a gate stack over the substrate. The gate stack includes a first copper layer over the substrate, a copper oxide layer over the first copper layer, and a second copper layer over the copper oxide layer.
摘要翻译：电阻式随机存取存储器单元使用衬底并且在衬底上包括栅极堆叠。栅极堆叠包括在衬底上的第一铜层，在第一铜层上方的氧化铜层和氧化铜层上的第二铜层。

9. 发明授权

US06791883B2 Program and erase in a thin film storage non-volatile memory 有权
标题翻译：在薄膜存储非易失性存储器中编程和擦除
公开(公告)号：US06791883B2
公开(公告)日：2004-09-14
申请号：US10178658
申请日：2002-06-24
申请人： Craig T. Swift , Jane A. Yater , Alexander B. Hoefler , Ko-Min Chang , Erwin J. Prinz , Bruce L. Morton
发明人： Craig T. Swift , Jane A. Yater , Alexander B. Hoefler , Ko-Min Chang , Erwin J. Prinz , Bruce L. Morton
IPC分类号： G11C1600
CPC分类号： G11C16/0466
摘要： A non-volatile memory having a thin film dielectric storage element is programmed by hot carrier injection (HCI) and erased by tunneling. The typical structure for the memory cells for this type of memory is silicon, oxide, nitride, oxide, and silicon (SONOS). The hot carrier injection provides relatively fast programming for SONOS, while the tunneling provides for erase that avoids the difficulties with the hot hole erase (HHE) type erase that generally accompanies hot carrier injection for programming. HHE is significantly more damaging to dielectrics leading to reliability issues. HHE also has a relatively narrow area of erasure that may not perfectly match the pattern for the HCI programming leaving an incomplete erasure. The tunnel erase effectively covers the entire area so there is no concern about incomplete erase. Although tunnel erase is slower than HHE, erase time is generally less critical in a system operation than is programming time.
摘要翻译：具有薄膜电介质存储元件的非易失性存储器通过热载流子注入（HCI）编程并通过隧道擦除。这种存储器的存储单元的典型结构是硅，氧化物，氮化物，氧化物和硅（SONOS）。热载波注入为SONOS提供相对快速的编程，而隧道提供擦除，避免了通常伴随热载流子注入进行编程的热孔擦除（HHE）类型擦除的困难。 HHE对电介质的破坏性更大，导致可靠性问题。 HHE还具有相对较窄的擦除区域，可能不完全匹配HCI编程的模式，从而导致不完整的擦除。隧道擦除有效地覆盖整个区域，所以不用担心不完全擦除。虽然隧道擦除比HHE慢，但擦除时间在系统操作中通常不如编程时间那么重要。

10. 发明授权

US5646060A Method for making an EEPROM cell with isolation transistor 失效
标题翻译：用隔离晶体管制造EEPROM单元的方法
公开(公告)号：US5646060A
公开(公告)日：1997-07-08
申请号：US471619
申请日：1995-05-30
申请人： Ko-Min Chang , Danny Pak-Chum Shum , Kuo-Tung Chang
发明人： Ko-Min Chang , Danny Pak-Chum Shum , Kuo-Tung Chang
IPC分类号： G11C17/00 , G11C16/04 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L27/115 , H01L29/7883
摘要： An EEPROM cell (40) includes a floating gate transistor (47) and an isolation transistor (45). Both a floating gate (48) and an isolation gate (46) are formed on a tunnel dielectric (44) within the cell. The isolation gate is coupled to a doped source region (52) of the floating gate transistor. The isolation transistor is not biased during a program operation of the cell, enabling a thin tunnel dielectric (less than 120 angstroms) to be used beneath all portions of both gates within the cell. Thus, the need for both a conventional tunnel dielectric and a gate dielectric is eliminated. The cell tolerates over-erasure, can be programmed at low programming voltages, and has good current drive due to the thin tunnel dielectric throughout the cell.
摘要翻译： EEPROM单元（40）包括浮栅晶体管（47）和隔离晶体管（45）。浮动栅极（48）和隔离栅极（46）均形成在电池内的隧道电介质（44）上。隔离栅极耦合到浮栅晶体管的掺杂源极区（52）。在单元的编程操作期间，隔离晶体管不被偏置，使得能够在单元内的两个栅极的所有部分下方使用薄的隧道电介质（小于120埃）。因此，消除了对常规隧道电介质和栅极电介质的需要。电池容忍过度擦除，可以在低编程电压下编程，并且由于整个电池中的薄隧道电介质而具有良好的电流驱动。

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