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1. 发明授权

US5273923A Process for fabricating an EEPROM cell having a tunnel opening which overlaps field isolation regions 失效
标题翻译：用于制造具有与场隔离区重叠的隧道开口的EEPROM单元的工艺
公开(公告)号：US5273923A
公开(公告)日：1993-12-28
申请号：US773791
申请日：1991-10-09
申请人： Ko-Min Chang , Clinton C. K. Kuo , Ming-Bing Chang
发明人： Ko-Min Chang , Clinton C. K. Kuo , Ming-Bing Chang
IPC分类号： G11C17/00 , H01L21/8247 , H01L29/788 , H01L29/792 , H01L21/302 , H01L21/38 , H01L27/115
CPC分类号： H01L27/11521 , H01L27/11524 , H01L29/7883
摘要： An EEPROM cell (10) has a tunnel opening (28) which overlaps both an active region (12) and field isolation regions (14). A tunnel area (30), which is that portion of the cell in which electrons tunnel through a tunnel dielectric (32) to charge or discharge a floating gate (22) during device operation, is defined as the overlapped portion of the tunnel opening (28) and the active region (12). By having the tunnel opening (28) larger than the tunnel area (30), etch processes used to pattern the opening in a gate dielectric (26) are more easily controlled and the active region area beneath the floating gate is reduced. The EEPROM cell (10) has a tunnel area which is limited in size by lithographic resolution capabilities rather than by limitations in dielectric etch processes. The tunnel features increase a capacitance coupling ratio of the cell.
摘要翻译： EEPROM单元（10）具有与有源区域（12）和场隔离区域（14）重叠的隧道开口（28）。隧道区域（30）是在设备操作期间电子穿过隧道电介质（32）充电或放电浮动栅极（22）的电池部分被定义为隧道开口的重叠部分（30） 28）和有源区（12）。通过使隧道开口（28）大于隧道区域（30），更容易控制用于对栅极电介质（26）中的开口进行图案化的蚀刻工艺，并且浮动栅极下方的有源区域面积减小。 EEPROM单元（10）具有通过光刻分辨能力限制尺寸的隧道区域，而不是通过电介质蚀刻工艺的限制。隧道特征增加了电池的电容耦合比。

2. 发明授权

US5130769A Nonvolatile memory cell 失效
标题翻译：非易失性存储单元
公开(公告)号：US5130769A
公开(公告)日：1992-07-14
申请号：US700837
申请日：1991-05-16
申请人： Clinton C. K. Kuo , Ko-Min Chang
发明人： Clinton C. K. Kuo , Ko-Min Chang
IPC分类号： G11C17/00 , H01L21/8247 , H01L29/423 , H01L29/788 , H01L29/792
CPC分类号： H01L29/42368 , H01L29/7885
摘要： A floating gate is utilized which has two portions. A first portion overlies the channel region formed between the source and drain. The control gate overlies this portion of the floating gate and the remaining portion of the channel region forming an enhancement transistor. The second portion of the floating gate extends from the first portion over a thin oxide tunnel area of the source. An additional diode implant forming a junction with the drain region is provided to regulate the current flow through the drain, particularly during erasure.
摘要翻译：使用一个浮动栅极，它有两个部分。第一部分覆盖形成在源极和漏极之间的沟道区域。控制栅极覆盖浮置栅极的该部分，并且沟道区域的剩余部分形成增强晶体管。浮动栅极的第二部分从源极的薄氧化物隧道区域上的第一部分延伸。提供形成与漏极区的结的另外的二极管注入，以调节通过漏极的电流，特别是在擦除期间。

3. 发明授权

US5474947A Nonvolatile memory process 失效
标题翻译：非易失性存储过程
公开(公告)号：US5474947A
公开(公告)日：1995-12-12
申请号：US172984
申请日：1993-12-27
申请人： Ko-Min Chang , Bruce L. Morton , Henry Y. Choe , Clinton C. K. Kuo
发明人： Ko-Min Chang , Bruce L. Morton , Henry Y. Choe , Clinton C. K. Kuo
IPC分类号： H01L21/8247
CPC分类号： H01L27/11517
摘要： A process for fabricating an improved nonvolatile memory device includes the formation of a control gate electrode (70) which overlies a floating gate electrode (42) and is separated therefrom by an inter-level-dielectric layer (62). The control gate electrode (70) and the underlying floating gate electrode (42) form a stacked gate structure (72) located in the active region (44) of a semiconductor substrate (40). An electrically insulating sidewall spacer (54) is formed at the edges of the floating gate electrode (42) and electrically isolates the control gate (70) from the semiconductor substrate (40). During the fabrication process, implanted memory regions (56, 58) are formed in the active region (44) prior to the formation of control gate electrode (70). A word-line (68) and the control gate (70) are formed by anisotropic etching of a semiconductor layer (66), which is deposited to overlie inter-level-dielectric layer (62). During the etching process, inter-level-dielectric layer (62) prevents the removal of surface portions of semiconductor substrate (40).
摘要翻译：一种用于制造改进的非易失性存储器件的方法包括形成覆盖在浮栅电极（42）上的控制栅电极（70），并通过层间电介质层（62）与其分开。控制栅电极（70）和底层浮栅电极（42）形成位于半导体衬底（40）的有源区（44）中的层叠栅结构（72）。在浮栅电极（42）的边缘处形成电绝缘的侧壁间隔物（54），并将控制栅极（70）与半导体衬底（40）电隔离。在制造过程中，在形成控制栅电极（70）之前，在有源区（44）中形成植入的存储区（56,58）。通过各向异性蚀刻形成字线（68）和控制栅极（70），半导体层（66）沉积到层间电介质层（62）上。在蚀刻过程中，层间电介质层（62）防止去除半导体衬底（40）的表面部分。

4. 发明授权

US5357476A Apparatus and method for erasing a flash EEPROM 失效
标题翻译：擦除闪存EEPROM的装置和方法
公开(公告)号：US5357476A
公开(公告)日：1994-10-18
申请号：US69327
申请日：1993-06-01
申请人： Clinton C. K. Kuo , Ko-Min Chang , Henry Y. Choe
发明人： Clinton C. K. Kuo , Ko-Min Chang , Henry Y. Choe
IPC分类号： G11C16/16 , G11C16/34 , G11C11/34
CPC分类号： G11C16/3409 , G11C16/16 , G11C16/3404
摘要： A flash EEPROM array (22) is erased and a threshold voltage distribution of the erased flash EEPROM cells (36, 39-46) is converged to within a predetermined voltage range by using a two-step erasing procedure. In the first step, flash EEPROM array (22) is electrically bulk erased using a conventional bulk erase procedure. Electrons are tunneled from the floating gate (38) to the source, causing cells (36, 39-46) to have a relatively low threshold voltage. In the second step, the threshold voltage distribution of the array (22) is converged to within the predetermined voltage range by grounding the source and drain of each cell (36, 39-46), while concurrently applying a high positive voltage to the control gate (27) of each cell (36, 39-46). Some electrons are tunneled back to the floating gate (38), thus converging the threshold voltage distribution to within a predetermined range.
摘要翻译：闪存EEPROM阵列（22）被擦除，并且擦除的快闪EEPROM单元（36,39-46）的阈值电压分布通过使用两步擦除过程而被收敛到预定电压范围内。在第一步中，使用传统的大容量擦除程序，电子体积擦除快闪EEPROM阵列（22）。电子从浮动栅极（38）隧穿到源极，导致电池（36,39-46）具有相对低的阈值电压。在第二步骤中，通过使每个单元（36,39-46）的源极和漏极接地而将阵列（22）的阈值电压分布收敛到预定电压范围内，同时向控制器施加高正电压（36,39-46）的门（27）。一些电子被隧穿回到浮动栅极（38），从而将阈值电压分布会聚到预定范围内。

5. 发明授权

US5949706A Static random access memory cell having a thin film transistor (TFT) pass gate connection to a bit line 有权
标题翻译：具有薄膜晶体管（TFT）的静态随机存取存储器单元将栅极连接到位线
公开(公告)号：US5949706A
公开(公告)日：1999-09-07
申请号：US236914
申请日：1999-01-26
申请人： Ko-Min Chang , Bruce L. Morton , Clinton C. K. Kuo , Keith E. Witek , Kent J. Cooper
发明人： Ko-Min Chang , Bruce L. Morton , Clinton C. K. Kuo , Keith E. Witek , Kent J. Cooper
IPC分类号： G11C7/12 , G11C8/08 , G11C11/404 , G11C11/412 , G11C16/04 , H01L21/8242 , H01L21/8247 , H01L27/06 , H01L27/108 , H01L27/115 , G11C11/00 , H01L27/11
CPC分类号： H01L27/10873 , G11C11/404 , G11C11/412 , G11C16/0433 , G11C7/12 , G11C8/08 , H01L27/0688 , H01L27/115 , H01L27/11517 , H01L27/11551 , H01L27/108 , H01L27/10891 , Y10S257/903
摘要： A memory circuit and method of formation uses a transmission gate (24) as a select gate. The transmission gate (24) contains a transistor (30) which is an N-channel transistor and a transistor (28) which is a P-channel transistor. The transistors (28 and 30) are electrically connected in parallel. The use of the transmission gate (24) as a select gate allows reads and writes to occur to a memory cell storage device (i.e. a capacitor (32), a floating gate (22), etc.) without a significant voltage drop occurring across the transmission gate. In addition, EEPROM technology is more compatible with EPROM/flash technology when using a transmission gate as a select gate within EEPROM devices.
摘要翻译：存储电路和形成方法使用传输门（24）作为选择栅极。传输门（24）包含作为N沟道晶体管的晶体管（30）和作为P沟道晶体管的晶体管（28）。晶体管（28和30）并联电连接。传输门（24）作为选择栅极的使用允许对存储器单元存储设备（即，电容器（32），浮动栅极（22）等））进行读取和写入，而不会发生跨越显着的电压降传输门。此外，当EEPROM设备中使用传输门作为选择门时，EEPROM技术更能兼容EPROM /闪存技术。

6. 发明授权

US5898619A Memory cell having a plural transistor transmission gate and method of formation 失效
标题翻译：具有多个晶体管传输门的存储单元和形成方法
公开(公告)号：US5898619A
公开(公告)日：1999-04-27
申请号：US242993
申请日：1994-05-16
申请人： Ko-Min Chang , Bruce L. Morton , Clinton C. K. Kuo , Keith E. Witek , Kent J. Cooper
发明人： Ko-Min Chang , Bruce L. Morton , Clinton C. K. Kuo , Keith E. Witek , Kent J. Cooper
IPC分类号： G11C7/12 , G11C8/08 , G11C11/404 , G11C11/412 , G11C16/04 , H01L21/8242 , H01L21/8247 , H01L27/06 , H01L27/108 , H01L27/115 , G11C11/22 , G11C11/24
CPC分类号： H01L27/10873 , G11C11/404 , G11C11/412 , G11C16/0433 , G11C7/12 , G11C8/08 , H01L27/0688 , H01L27/115 , H01L27/11517 , H01L27/11551 , H01L27/108 , H01L27/10891 , Y10S257/903
摘要： A memory circuit and method of formation uses a transmission gate (24) as a select gate. The transmission gate (24) contains a transistor (30) which is an N-channel transistor and a transistor (28) which is a P-channel transistor. The transistors (28 and 30) are electrically connected in parallel. The use of the transmission gate (24) as a select gate allows reads and writes to occur to a memory cell storage device (i.e. a capacitor (32), a floating gate (22), etc.) without a significant voltage drop occurring across the transmission gate. In addition, EEPROM technology is more compatible with EPROM/flash technology when using a transmission gate as a select gate within EEPROM devices.
摘要翻译：存储电路和形成方法使用传输门（24）作为选择栅极。传输门（24）包含作为N沟道晶体管的晶体管（30）和作为P沟道晶体管的晶体管（28）。晶体管（28和30）并联电连接。传输门（24）作为选择栅极的使用允许对存储器单元存储设备（即，电容器（32），浮动栅极（22）等））进行读取和写入，而不会发生跨越显着的电压降传输门。此外，当EEPROM设备中使用传输门作为选择门时，EEPROM技术更能兼容EPROM /闪存技术。

7. 发明授权

US5428574A Static RAM with test features 失效
标题翻译：具有测试功能的静态RAM
公开(公告)号：US5428574A
公开(公告)日：1995-06-27
申请号：US701536
申请日：1991-03-28
申请人： Clinton C. K. Kuo , Ernest A. Carter
发明人： Clinton C. K. Kuo , Ernest A. Carter
IPC分类号： G11C29/02 , G11C29/50 , G11C7/06
CPC分类号： G11C29/025 , G11C29/02 , G11C29/50 , G11C29/50016 , G11C11/41 , G11C2029/5006
摘要： A static RAM includes test features which provide for the detection of soft defects which may cause a defective SRAM cell to behave as a functional DRAM cell. Provision is made for writing either a high or a low logic state to each bit line of the SRAM while not writing any value to its complementary bit line and for sensing the state of each bit line independently of the state of its complementary bit line. In addition, a current test is provided which detects soft defects by means of the increased inverter leakage current caused thereby. It is possible, by properly combining these tests, to reliably detect all soft defects, thereby assuring the data retention capability of the SRAM. This technique avoids the long hold time and/or high temperature test techniques used in the prior art.
摘要翻译：静态RAM包括提供检测软缺陷的测试特征，这可能导致有缺陷的SRAM单元表现为功能性DRAM单元。提供写入高或低逻辑状态到SRAM的每个位线，而不向其互补位线写入任何值，并且用于独立于其互补位线的状态来感测每个位线的状态。此外，提供了通过由此引起的增加的逆变器漏电流来检测软缺陷的电流测试。通过适当组合这些测试，可以可靠地检测所有的软缺陷，从而保证SRAM的数据保留能力。该技术避免了现有技术中使用的长的保持时间和/或高温测试技术。

8. 发明授权

US4547749A Voltage and temperature compensated FET ring oscillator 失效
标题翻译：电压和温度补偿FET环形振荡器
公开(公告)号：US4547749A
公开(公告)日：1985-10-15
申请号：US566608
申请日：1983-12-29
申请人： Clinton C. K. Kuo
发明人： Clinton C. K. Kuo
IPC分类号： H03K3/011 , H03K3/354 , H03L1/02 , H03B5/00 , H03K3/26 , H03L1/00
CPC分类号： H03K3/011 , H03K3/3545 , H03L1/02
摘要： An oscillator with inverter and delay stages is coupled between first and second reference terminals. In one aspect a depletion transistor is connected between a power supply terminal and the first reference terminal to provide a reference voltage thereat. In another aspect the delay stages each have a control terminal for controlling the delay thereof. A temperature compensation circuit has a control transistor which provides a voltage to the control terminals of the delay stages which is inversely proportional to the threshold voltage of the control transistor.
摘要翻译：具有反相器和延迟级的振荡器耦合在第一和第二参考端子之间。在一个方面，耗尽晶体管连接在电源端子和第一参考端子之间以在其上提供参考电压。在另一方面，延迟级各自具有用于控制其延迟的控制端子。温度补偿电路具有控制晶体管，该控制晶体管向与控制晶体管的阈值电压成反比的延迟级的控制端提供电压。

9. 发明授权

US4459497A Sense amplifier using different threshold MOS devices 失效
标题翻译：感应放大器使用不同的阈值MOS器件
公开(公告)号：US4459497A
公开(公告)日：1984-07-10
申请号：US342040
申请日：1982-01-25
申请人： Clinton C. K. Kuo , Horst Leuschner
发明人： Clinton C. K. Kuo , Horst Leuschner
IPC分类号： G11C11/419 , H03K5/02 , H03K5/24 , G11C7/06
CPC分类号： H03K5/023
摘要： A sense amplifier quickly charges a column line to a first predetermined voltage level with first, second and third transistors and then charges the column to a second predetermined voltage by using only the second and third transistors. The second and third transistors continue charging to the second predetermined voltage by virtue of having a lower threshold voltage than the first transistor. If a selected memory cell in the column is in a conducting state, the column charges to only the first predetermined voltage for detection as a logic "0". If the selected memory cell in the column is in a non-conducting state, the column continues charging to the second predetermined voltage for detection as a logic "1".
摘要翻译：读出放大器利用第一，第二和第三晶体管将列线快速充电到第一预定电压电平，然后仅使用第二和第三晶体管将该列充电至第二预定电压。由于具有比第一晶体管低的阈值电压，第二和第三晶体管继续充电到第二预定电压。如果列中选定的存储单元处于导通状态，则该列仅将第一预定电压充电至逻辑“0”。如果列中所选择的存储单元处于非导通状态，则列继续充电到第二预定电压以作为逻辑“1”。

10. 发明授权

US5991201A Non-volatile memory with over-program protection and method therefor 失效
标题翻译：具有过程编程保护的非易失性存储器及其方法
公开(公告)号：US5991201A
公开(公告)日：1999-11-23
申请号：US067026
申请日：1998-04-27
申请人： Clinton C. K. Kuo , Thomas Jew , David W. Chrudimsky
发明人： Clinton C. K. Kuo , Thomas Jew , David W. Chrudimsky
IPC分类号： G11C16/34 , G11C16/04
CPC分类号： G11C16/3486 , G11C16/3459 , G11C16/3468
摘要： A floating-gate non-volatile memory (30) uses a relatively-low threshold voltage to define a programmed state. The memory (30) compensates for fast program cells by providing program pulses which increase in length and magnitude while the cells are being programmed. Between each program pulse the memory (30) determines whether selected cells have been adequately programmed. The memory (30) ceases applying the series of pulses to each cell when it has been adequately programmed. Thus the memory (30) avoids the over-program condition instead of compensating for it.
摘要翻译：浮栅非易失性存储器（30）使用相对低的阈值电压来定义编程状态。存储器（30）通过提供在单元被编程时增加长度和幅度的编程脉冲来补偿快速编程单元。在每个编程脉冲之间，存储器（30）确定所选择的单元是否已被适当编程。当存储器（30）已被适当地编程时，存储器（30）停止向每个单元施加一系列脉冲。因此，存储器（30）避免了过程编程状态，而不是补偿它。

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