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1. 发明授权

US06465289B1 Method of fabricating monolithic multifunction integrated circuit devices 失效
标题翻译：单片多功能集成电路器件的制造方法
公开(公告)号：US06465289B1
公开(公告)日：2002-10-15
申请号：US08675248
申请日：1996-07-01
申请人： Dwight C. Streit , Donald K. Umemoto , Aaron K. Oki , Kevin W. Kobayashi
发明人： Dwight C. Streit , Donald K. Umemoto , Aaron K. Oki , Kevin W. Kobayashi
IPC分类号： H01L21338
CPC分类号： H01L27/0605 , H01L21/8252
摘要： A method of selective molecular beam epitaxy for fabricating monolithically integrated circuit devices on a common substrate including combinations of PIN diode devices, HBT devices, HEMT devices and MESFET devices. The method includes depositing a profile layer of one of the devices on an appropriate substrate and then depositing a first dielectric layer over the profile layer. The profile layer and the dielectric layer are then etched to define a first device profile. A second profile layer for defining a second device is then deposited over the exposed substrate. The second profile is then selectively etched to define a second device profile. This process can be extended to more than two different device types monolithically integrated on a common substrate as long as the first developed devices are robust enough to handle the temperature cycling involved with developing the subsequent devices.
摘要翻译：一种用于在包括PIN二极管器件，HBT器件，HEMT器件和MESFET器件的组合的公共衬底上制造单片集成电路器件的选择性分子束外延的方法。该方法包括将一个器件的轮廓层沉积在合适的衬底上，然后在轮廓层上沉积第一介电层。然后蚀刻轮廓层和电介质层以限定第一装置轮廓。用于限定第二装置的第二轮廓层然后沉积在暴露的基底上。然后选择性地蚀刻第二轮廓以限定第二装置轮廓。只要第一个开发的设备足够坚固以处理与后续设备相关的温度循环，该过程可以扩展到单个集成在公共基板上的多于两种不同的设备类型。

2. 发明授权

US6072371A Quenchable VCO for switched band synthesizer applications 失效
标题翻译：用于切换频带合成器应用的可淬火VCO
公开(公告)号：US6072371A
公开(公告)日：2000-06-06
申请号：US876275
申请日：1997-06-16
申请人： Kevin W. Kobayashi , Duncan M. Smith , Aaron K. Oki , Arvind K. Sharma , Barry R. Allen
发明人： Kevin W. Kobayashi , Duncan M. Smith , Aaron K. Oki , Arvind K. Sharma , Barry R. Allen
IPC分类号： H03L7/099 , H03B5/02 , H03B5/18 , H03B5/00 , H03B5/12
CPC分类号： H03B5/1847
摘要： A quenchable VCO that is adapted to be used in switched band synthesizer applications. The VCO may be formed from a heterojunction bipolar transistor (HBT) in a common collector configuration. A quenching circuit which includes a p-i-n diode, is electrically coupled in series with the collector of the HBT. The p-i-n diode is adapted to be monolithically integrated with the HBT. Since the p-i-n diode is electrically connected to the collector of the HBT, as opposed to the base and emitter terminals of the HBT, which forms the main oscillator feedback loop, the Q-factor of the p-i-n diode will have relatively less loading on the phase noise of the HBT oscillator. Moreover, since the p-i-n diode is isolated from the base-emitter junction, the configuration will result in reduced frequency pulling and generation of spurious oscillation and transient effects due to the switching of the p-i-n diode quenched circuit. The use of a p-i-n diode for quenching of VCO also provides other inherent advantages over other types of semi-conductor switches, such as FET, Schottky diodes, PN diodes for quenchable VCO applications because p-i-n diodes are relative insensitive to RF and noise modulation. Because the p-i-n diode can be constructed from existing HBT collector-base MBE epitaxy layers, the quenching circuit can be manufactured relatively inexpensively.
摘要翻译：一种适用于切换频带合成器应用的可淬火VCO。 VCO可以由公共集电器配置中的异质结双极晶体管（HBT）形成。包括p-i-n二极管的淬火电路与HBT的集电器串联电耦合。 p-i-n二极管适于与HBT单片集成。由于pin二极管与HBT的集电极电连接，与形成主振荡器反馈环路的HBT的基极和发射极端子相反，因此pin二极管的Q因子在相位上的负载相对较小 HBT振荡器的噪声。此外，由于p-i-n二极管与基极 - 发射极结隔离，所以由于p-i-n二极管骤冷电路的切换，该结构将导致降低的频率拉动和寄生振荡的产生以及瞬态效应。与其他类型的半导体开关（例如FET，肖特基二极管，用于可淬灭的VCO应用的PN二极管）相比，使用p-i-n二极管来淬灭VCO也具有其他固有的优点，因为p-i-n二极管对RF和噪声调制相对不敏感。因为p-i-n二极管可以由现有的HBT集电极基极MBE外延层构成，所以可以相对廉价地制造淬火电路。

3. 发明授权

US5986517A Low-loss air suspended radially combined patch for N-way RF switch 失效
标题翻译：低损耗空气悬挂式径向组合贴片，用于N路RF开关
公开(公告)号：US5986517A
公开(公告)日：1999-11-16
申请号：US3197
申请日：1998-01-06
申请人： Kevin W. Kobayashi , Aaron K. Oki
发明人： Kevin W. Kobayashi , Aaron K. Oki
IPC分类号： H01P1/12 , H01P1/15 , H01P11/00
CPC分类号： H01P1/15 , H01P11/003
摘要： A microstrip switch includes N-input switch arms and an output port formed from a microstrip transmission line. Each input switch arm includes one or more p-i-n diodes. The input switch arms as well as the output port are connected at a radially combined center patch. In order to improve the insertion losses at millimeter wave frequencies, the center patch is air suspended in order to reduce the parasitic shunt capacitance in order to extend the low pass frequency response of the switch.
摘要翻译：微带开关包括N输入开关臂和由微带传输线形成的输出端口。每个输入开关臂包括一个或多个p-i-n二极管。输入开关臂以及输出端口连接在径向组合的中心贴片上。为了提高毫米波频率下的插入损耗，中心贴片为空气悬浮，以减小寄生并联电容，以扩展开关的低通频率响应。

4. 发明授权

US5262335A Method to produce complementary heterojunction bipolar transistors 失效
标题翻译：产生互补异质结双极晶体管的方法
公开(公告)号：US5262335A
公开(公告)日：1993-11-16
申请号：US772809
申请日：1991-10-08
申请人： Dwight C. Streit , Aaron K. Oki , Donald K. Umemoto , James R. Velebir, Jr.
发明人： Dwight C. Streit , Aaron K. Oki , Donald K. Umemoto , James R. Velebir, Jr.
IPC分类号： H01L29/205 , H01L21/331 , H01L21/8228 , H01L21/8252 , H01L27/06 , H01L27/082 , H01L29/73 , H01L29/737 , H01L21/265 , H01L29/70
CPC分类号： H01L21/8252 , H01L27/0605 , H01L27/0826 , Y10S148/072
摘要： Disclosed is a method for fabricating complementary heterojunction bipolar transistors on a common substrate. The method comprises the steps of depositing a PNP profile by molecular beam epitaxy on an appropriate substrate and then depositing a layer of silicon nitride on the PNP profile just deposited. The substrate is then heated in a vacuum in order to densify the silicon nitride. A mask and resist layer are used to produce the desired PNP profile patterns. The NPN profile is deposited on the area of the substrate etched away as well as on the silicon nitride layer protecting the already deposited PNP layers. The NPN profile is then patterned using a resist and masking process. The polycrystalline NPN area on top of the silicon nitride layer and the remaining silicon nitride layer are etched away forming two adjacent complementary NPN and PNP profiles on a common substrate. In the fabrication of the heterojunction bipolar transistor circuits, the P-ohmic contacts on both the NPN and PNP materials is evaporated at the appropriate locations simultaneously. All of the N-ohmic contacts are also deposited simultaneously. By this, the complementary dual heterojunction bipolar transistor device can be effectively fabricated with excellent DC and microwave capabilities.

5. 发明授权

US6037646A High-frequency GaAs substrate based schottky barrier diodes 失效
标题翻译：基于高频GaAs衬底的肖特基势垒二极管
公开(公告)号：US6037646A
公开(公告)日：2000-03-14
申请号：US865890
申请日：1997-05-30
申请人： Aaron K. Oki , Donald K. Umemoto , Liem T. Tran , Dwight C. Streit
发明人： Aaron K. Oki , Donald K. Umemoto , Liem T. Tran , Dwight C. Streit
IPC分类号： H01L21/329 , H01L29/47 , H01L29/872 , H01L27/095
CPC分类号： H01L29/66212 , H01L29/872
摘要： A Schottky barrier diode and a method for fabricating a Schottky barrier diode that utilizes HBT active device layers. The Schottky barrier diode is formed with a vertically integrated profile on a GaAs substrate, with a subcollector layer and a collector layer. A suitable dielectric material is deposited on top of the collector layer. Vias are formed in the collector layer and subcollector layer for the barrier and ohmic contacts. The collector via is relatively deeply etched into the collector layer to lower the series resistance between the barrier and ohmic contacts, which results in relatively higher cut-off frequency performance.
摘要翻译：一种肖特基势垒二极管和一种利用HBT有源器件层制造肖特基势垒二极管的方法。肖特基势垒二极管在GaAs衬底上形成垂直集成的形状，具有子集电极层和集电极层。合适的电介质材料沉积在集电极层的顶部。在集电极层和子集电极层中形成用于屏障和欧姆接触的通孔。集电极通孔相对深度地蚀刻到集电极层中，以降低阻挡层和欧姆接触之间的串联电阻，这导致相对较高的截止频率性能。

6. 发明授权

US5631477A Quaternary collector InAlAs-InGaAlAs heterojunction bipolar transistor 失效
标题翻译：四元收集器InAlAs-InGaAlAs异质结双极晶体管
公开(公告)号：US5631477A
公开(公告)日：1997-05-20
申请号：US490440
申请日：1995-06-02
申请人： Dwight C. Streit , Aaron K. Oki , Liem T. Tran
发明人： Dwight C. Streit , Aaron K. Oki , Liem T. Tran
IPC分类号： H01L29/73 , H01L21/331 , H01L29/08 , H01L29/205 , H01L29/737 , H01L31/0328 , H01L31/0336
CPC分类号： H01L29/0821 , H01L29/7371
摘要： An InAlAs/InGaAlAs heterojunction bipolar transistor that includes a constant quaternary InGaAlAs collector layer. Graded InGaAlAs collector layers are provided on each side of the quaternary collector layer to minimize transitions through the constant collector layer. The InAlAs/InGaAlAs HBT may also include one or more of a graded InGaAlAs emitter-base transition region, a graded-doping InGaAs base layer, and a graded-composition InGaAlAs base layer.
摘要翻译： InAlAs / InGaAlAs异质结双极晶体管，其包括恒定的四元InGaAlAs集电极层。渐变的InGaAlAs集电极层设置在四元集电极层的每一侧，以使通过恒定集电极层的过渡最小化。 InAlAs / InGaAlAs HBT还可以包括渐变的InGaAlAs发射极 - 基极化过渡区，渐变掺杂的InGaAs基层和渐变组成的InGaAlAs基层中的一个或多个。

7. 发明授权

US5448087A Heterojunction bipolar transistor with graded base doping 失效
标题翻译：异质结双极晶体管，具有分级基极掺杂
公开(公告)号：US5448087A
公开(公告)日：1995-09-05
申请号：US876199
申请日：1992-04-30
申请人： Swight C. Streit , Aaron K. Oki
发明人： Swight C. Streit , Aaron K. Oki
IPC分类号： H01L29/10 , H01L29/737 , H01L29/161 , H01L29/205 , H01L29/225
CPC分类号： H01L29/7371 , H01L29/1004
摘要： A heterojunction bipolar transistor with an exponentially graded base doping is disclosed, in addition to a technique for fabricating the transistor. In accordance with the preferred embodiment, the transistor employs a base with an exponentially graded Beryllium doping which varies from 5.times.10.sup.19 cm.sup.-3 at the base-emitter junction to 5.times.10.sup.18 cm.sup.-3 at the base-collector junction. The built-in field due to the exponentially graded doping profile significantly reduces base transit time despite bandgap narrowing associated with high base doping. Compared to devices with the same base thickness and uniform base doping, the cut off frequency is increased and the maximum frequency of oscillation is also increased. Also, consistently higher common emitter current gain results even though the Gummel number is twice as high and the base resistance is reduced by 40%.
摘要翻译：除了制造晶体管的技术之外，还公开了具有指数梯度的基极掺杂的异质结双极晶体管。根据优选实施例，晶体管采用具有指数级渐变的铍掺杂的基极，其在基极 - 集电极结处的基极 - 发射极结处从5×10 19 cm -3变化到5×10 18 cm -3。由于具有指数梯度的掺杂特性，内置场可显着降低基极通过时间，尽管与高基极掺杂相关的带隙变窄。与具有相同基底厚度和均匀基极掺杂的器件相比，截止频率增加，振荡的最大频率也增加。此外，尽管Gummel数量是两倍高，基极电阻降低了40％，但始终更高的公共发射极电流增益。

8. 发明授权

US5162243A Method of producing high reliability heterojunction bipolar transistors 失效
标题翻译：制造高可靠性异质结双极晶体管的方法
公开(公告)号：US5162243A
公开(公告)日：1992-11-10
申请号：US752401
申请日：1991-08-30
申请人： Dwight C. Streit , Aaron K. Oki
发明人： Dwight C. Streit , Aaron K. Oki
IPC分类号： H01L29/205 , H01L21/203 , H01L21/331 , H01L29/207 , H01L29/73 , H01L29/737
CPC分类号： H01L29/66318 , H01L29/207 , H01L29/7371 , Y10S438/936
摘要： A technique for producing high reliability GaAsAlGaAs heterojunction bipolar transistors by Molecular Beam Epitaxy with beryllium base doping. Beryllium incorporation and diffusion, during base-layer deposition, is controlled through a combination of reduced substrate temperature and increase As/Ga flux ratio during MBE growth resulting in extremely stable heterojunction bipolar transistor profiles. In addition, graded InGaAs surface layers with non-alloyed refractory metal contacts are shown to significantly improve ohmic reliability to alloyed AuGe contacts. High gain (DC beta) is achieved by the use of an increased substrate temperature during emitter deposition. The HBTs in accordance with the present invention are useful in a number of important microwave applications such as log amps, a/d converters, and sample and hold circuits where high reliability is desired.

9. 发明授权

US5930636A Method of fabricating high-frequency GaAs substrate-based Schottky barrier diodes 失效
标题翻译：制造高频GaAs衬底的肖特基势垒二极管的方法
公开(公告)号：US5930636A
公开(公告)日：1999-07-27
申请号：US645361
申请日：1996-05-13
申请人： Aaron K. Oki , Donald K. Umemoto , Liem T. Tran , Dwight C. Streit
发明人： Aaron K. Oki , Donald K. Umemoto , Liem T. Tran , Dwight C. Streit
IPC分类号： H01L21/329 , H01L29/47 , H01L29/872 , H01L21/331 , H01L21/00 , H01L21/338 , H01L31/0328
CPC分类号： H01L29/66212 , H01L29/872
摘要： A Schottky barrier diode and a method for fabricating a Schottky barrier diode that utilizes HBT active device layers. The Schottky barrier diode is formed with a vertically integrated profile on a GaAs substrate, with a subcollector layer and a collector layer. A suitable dielectric material is deposited on top of the collector layer. Vias are formed in the collector layer and subcollector layer for the barrier and ohmic contacts. The collector via is relatively deeply etched into the collector layer to lower the series resistance between the barrier and ohmic contacts, which results in relatively higher cut-off frequency performance.
摘要翻译：一种肖特基势垒二极管和一种利用HBT有源器件层制造肖特基势垒二极管的方法。肖特基势垒二极管在GaAs衬底上形成垂直集成的形状，具有子集电极层和集电极层。合适的电介质材料沉积在集电极层的顶部。在集电极层和子集电极层中形成用于屏障和欧姆接触的通孔。集电极通孔相对深度地蚀刻到集电极层中，以降低阻挡层和欧姆接触之间的串联电阻，这导致相对较高的截止频率性能。

10. 发明授权

US5840612A Method of fabricating very high gain heterojunction bipolar transistors 失效
标题翻译：制造超高增益异质结双极晶体管的方法
公开(公告)号：US5840612A
公开(公告)日：1998-11-24
申请号：US911388
申请日：1997-08-14
申请人： Aaron K. Oki , Dwight C. Streit , Donald K. Umemoto , Liem T. Tran
发明人： Aaron K. Oki , Dwight C. Streit , Donald K. Umemoto , Liem T. Tran
IPC分类号： H01L29/73 , H01L21/331 , H01L29/205 , H01L29/737
CPC分类号： H01L29/66318 , H01L29/7371
摘要： A heterojunction bipolar transistor with a vertically integrated profile includes a substrate layer, a collector contact layer, a collector layer, a base layer and an emitter layer, formed from AlGaAs, etched to form an emitter mesa leaving a relatively thin passivating layer, adjacent the emitter mesa. The base metal contacts are formed on the passivating layer, resulting in a wider bandgap, thus minimizing surface recombination velocity at the emitter-base junction and increasing the overall gain (.beta.) of the device. The base metal contacts are formed by evaporating a p-ohmic metal onto the n-type passivation layer. The p-ohmic contacts are annealed, resulting in p-type metal diffusion through the passivating layer and reaction with the base layer, resulting in ohmic contacts.
摘要翻译：具有垂直集成轮廓的异质结双极晶体管包括由AlGaAs形成的衬底层，集电极接触层，集电极层，基极层和发射极层，蚀刻形成离开较薄钝化层的发射极台面，邻近发射台台面贱金属触点形成在钝化层上，导致更宽的带隙，从而最小化发射极 - 基极结处的表面复合速度，并增加器件的总增益（β）。通过将p-欧姆金属蒸发到n型钝化层上而形成基底金属接触。 p欧姆接触被退火，导致p型金属通过钝化层扩散并与基层反应，导致欧姆接触。

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