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1. 发明授权

US06465289B1 Method of fabricating monolithic multifunction integrated circuit devices 失效
标题翻译：单片多功能集成电路器件的制造方法
公开(公告)号：US06465289B1
公开(公告)日：2002-10-15
申请号：US08675248
申请日：1996-07-01
申请人： Dwight C. Streit , Donald K. Umemoto , Aaron K. Oki , Kevin W. Kobayashi
发明人： Dwight C. Streit , Donald K. Umemoto , Aaron K. Oki , Kevin W. Kobayashi
IPC分类号： H01L21338
CPC分类号： H01L27/0605 , H01L21/8252
摘要： A method of selective molecular beam epitaxy for fabricating monolithically integrated circuit devices on a common substrate including combinations of PIN diode devices, HBT devices, HEMT devices and MESFET devices. The method includes depositing a profile layer of one of the devices on an appropriate substrate and then depositing a first dielectric layer over the profile layer. The profile layer and the dielectric layer are then etched to define a first device profile. A second profile layer for defining a second device is then deposited over the exposed substrate. The second profile is then selectively etched to define a second device profile. This process can be extended to more than two different device types monolithically integrated on a common substrate as long as the first developed devices are robust enough to handle the temperature cycling involved with developing the subsequent devices.
摘要翻译：一种用于在包括PIN二极管器件，HBT器件，HEMT器件和MESFET器件的组合的公共衬底上制造单片集成电路器件的选择性分子束外延的方法。该方法包括将一个器件的轮廓层沉积在合适的衬底上，然后在轮廓层上沉积第一介电层。然后蚀刻轮廓层和电介质层以限定第一装置轮廓。用于限定第二装置的第二轮廓层然后沉积在暴露的基底上。然后选择性地蚀刻第二轮廓以限定第二装置轮廓。只要第一个开发的设备足够坚固以处理与后续设备相关的温度循环，该过程可以扩展到单个集成在公共基板上的多于两种不同的设备类型。

2. 发明授权

US5262335A Method to produce complementary heterojunction bipolar transistors 失效
标题翻译：产生互补异质结双极晶体管的方法
公开(公告)号：US5262335A
公开(公告)日：1993-11-16
申请号：US772809
申请日：1991-10-08
申请人： Dwight C. Streit , Aaron K. Oki , Donald K. Umemoto , James R. Velebir, Jr.
发明人： Dwight C. Streit , Aaron K. Oki , Donald K. Umemoto , James R. Velebir, Jr.
IPC分类号： H01L29/205 , H01L21/331 , H01L21/8228 , H01L21/8252 , H01L27/06 , H01L27/082 , H01L29/73 , H01L29/737 , H01L21/265 , H01L29/70
CPC分类号： H01L21/8252 , H01L27/0605 , H01L27/0826 , Y10S148/072
摘要： Disclosed is a method for fabricating complementary heterojunction bipolar transistors on a common substrate. The method comprises the steps of depositing a PNP profile by molecular beam epitaxy on an appropriate substrate and then depositing a layer of silicon nitride on the PNP profile just deposited. The substrate is then heated in a vacuum in order to densify the silicon nitride. A mask and resist layer are used to produce the desired PNP profile patterns. The NPN profile is deposited on the area of the substrate etched away as well as on the silicon nitride layer protecting the already deposited PNP layers. The NPN profile is then patterned using a resist and masking process. The polycrystalline NPN area on top of the silicon nitride layer and the remaining silicon nitride layer are etched away forming two adjacent complementary NPN and PNP profiles on a common substrate. In the fabrication of the heterojunction bipolar transistor circuits, the P-ohmic contacts on both the NPN and PNP materials is evaporated at the appropriate locations simultaneously. All of the N-ohmic contacts are also deposited simultaneously. By this, the complementary dual heterojunction bipolar transistor device can be effectively fabricated with excellent DC and microwave capabilities.

3. 发明授权

US06680494B2 Ultra high speed heterojunction bipolar transistor having a cantilevered base 有权
标题翻译：具有悬臂底座的超高速异质结双极晶体管
公开(公告)号：US06680494B2
公开(公告)日：2004-01-20
申请号：US09776513
申请日：2001-02-02
申请人： Augusto L. Gutierrez-Aitken , Aaron K. Oki , Eric N. Kaneshiro , Dwight C. Streit
发明人： Augusto L. Gutierrez-Aitken , Aaron K. Oki , Eric N. Kaneshiro , Dwight C. Streit
IPC分类号： H01L29732
CPC分类号： H01L29/66318 , H01L29/045 , H01L29/1004 , H01L29/7371
摘要： Reduction in the base to collector capacitance of a heterojunction bipolar transistor, and, improved high frequency performance is achieved using existing materials and processes by undercutting the collector (5) under the base (7) along two parallel sides of the base mesa (7—FIG. 4), and providing a sloped collector edge (5—FIG. 6) along the remaining two parallel sides of the base. The foregoing is accomplished by selective etching and with the four sides of the mesa regions oriented as a non-rectangular parallelogram (7, 9—FIG. 4) in which one pair of sides is in parallel with one of the said [0 0 1] and [0 0 {overscore (1)}] planes of the crystalline structure and the other pair of sides in parallel with one of the [0 1 1] and [0 {overscore (1)} {overscore (1)}] planes of the crystalline structure.
摘要翻译：通过使用现有的材料和工艺，通过在基底（7）下沿基底台面（7）的两个平行边缘切割集电体（5）来实现异质结双极晶体管的基极到集电极电容的减小，以及改进的高频性能。并且沿着底座的剩余的两个平行侧提供倾斜的收集器边缘（5-Fig。6）。前述是通过选择性蚀刻实现的，并且台面区域的四个侧面被定向为非矩形平行四边形（7,9-图4），其中一对边与所述[0,01 ]和晶体结构的[0 0（超芯（1）]平面，另一对侧与晶体结构的[0,1]和[0 {超晶核（1（超晶核（1））平面之一平行。

4. 发明授权

US06528829B1 Integrated circuit structure having a charge injection barrier 失效
标题翻译：具有电荷注入阻挡层的集成电路结构
公开(公告)号：US06528829B1
公开(公告)日：2003-03-04
申请号：US09276041
申请日：1999-03-25
申请人： Augusto L. Gutierrez-Aitken , Aaron K. Oki , Michael Wojtowicz , Dwight C. Streit , Thomas R. Block , Frank M. Yamada
发明人： Augusto L. Gutierrez-Aitken , Aaron K. Oki , Michael Wojtowicz , Dwight C. Streit , Thomas R. Block , Frank M. Yamada
IPC分类号： H01L2970
CPC分类号： H01L21/02395 , H01L21/02463 , H01L21/02505 , H01L21/0251 , H01L21/02546 , H01L29/267 , H01L29/7371
摘要： The invention relates to an integrated circuit structure that includes a substrate wafer having an active device layer disposed on a surface of the substrate wafer and having an electrically conductive element contained therein. The integrated circuit structure further comprises a barrier disposed between the substrate wafer and the active device layer, where the barrier blocks carriers injected into the substrate wafer and reduces low frequency oscillation effect.
摘要翻译：本发明涉及一种集成电路结构，其包括具有设置在衬底晶片的表面上并且其中包含导电元件的有源器件层的衬底晶片。集成电路结构还包括设置在衬底晶片和有源器件层之间的势垒，其中势垒阻挡载流子注入衬底晶片并降低低频振荡效应。

5. 发明授权

US06376867B1 Heterojunction bipolar transistor with reduced thermal resistance 有权
标题翻译：具有降低的热阻的异质结双极晶体管
公开(公告)号：US06376867B1
公开(公告)日：2002-04-23
申请号：US09631597
申请日：2000-08-03
申请人： Augusto L. Gutierrez-Aitken , Aaron K. Oki , Patrick T. Chin , Dwight C. Streit
发明人： Augusto L. Gutierrez-Aitken , Aaron K. Oki , Patrick T. Chin , Dwight C. Streit
IPC分类号： H01L310328
CPC分类号： H01L29/0821 , H01L29/7371
摘要： The performance of a heterojunction bipolar transistor (HBT) operating at high power is limited by the power that can be dissipated by the device. This, in turn, is limited by the thermal resistance of the device to heat dissipation. In a typical HBT, and especially InP-based HBTs, heat generated during operation is concentrated near the collector-base junction. In order to more efficiently dissipate heat downward through the device to the substrate, both the collector and the sub-collector are formed of InP, which has a substantially lower thermal resistance than other typically used semiconductor materials.
摘要翻译：以高功率工作的异质结双极晶体管（HBT）的性能受到器件消耗的功率的限制。这又受到设备的散热热阻的限制。在典型的HBT中，特别是基于InP的HBT中，在操作期间产生的热量集中在集电极 - 基极结附近。为了更有效地将热量通过器件向下散发到衬底，集电极和副集电极都由InP形成，其具有比其它通常使用的半导体材料显着更低的热阻。

6. 发明授权

US5986517A Low-loss air suspended radially combined patch for N-way RF switch 失效
标题翻译：低损耗空气悬挂式径向组合贴片，用于N路RF开关
公开(公告)号：US5986517A
公开(公告)日：1999-11-16
申请号：US3197
申请日：1998-01-06
申请人： Kevin W. Kobayashi , Aaron K. Oki
发明人： Kevin W. Kobayashi , Aaron K. Oki
IPC分类号： H01P1/12 , H01P1/15 , H01P11/00
CPC分类号： H01P1/15 , H01P11/003
摘要： A microstrip switch includes N-input switch arms and an output port formed from a microstrip transmission line. Each input switch arm includes one or more p-i-n diodes. The input switch arms as well as the output port are connected at a radially combined center patch. In order to improve the insertion losses at millimeter wave frequencies, the center patch is air suspended in order to reduce the parasitic shunt capacitance in order to extend the low pass frequency response of the switch.
摘要翻译：微带开关包括N输入开关臂和由微带传输线形成的输出端口。每个输入开关臂包括一个或多个p-i-n二极管。输入开关臂以及输出端口连接在径向组合的中心贴片上。为了提高毫米波频率下的插入损耗，中心贴片为空气悬浮，以减小寄生并联电容，以扩展开关的低通频率响应。

7. 发明授权

US5892248A Double photoresist layer self-aligned heterojuction bipolar transistor 失效
标题翻译：双光阻层自对准异质双极晶体管
公开(公告)号：US5892248A
公开(公告)日：1999-04-06
申请号：US720388
申请日：1996-09-30
申请人： Aaron K. Oki , Donald K. Umemoto , Liem T. Tran , Dwight C. Streit
发明人： Aaron K. Oki , Donald K. Umemoto , Liem T. Tran , Dwight C. Streit
IPC分类号： H01L29/73 , H01L21/331 , H01L29/205 , H01L29/737 , H01L31/0328 , H01L27/082 , H01L31/0336
CPC分类号： H01L29/66318 , Y10S148/01 , Y10S148/011 , Y10S148/072 , Y10S148/10 , Y10S148/143
摘要： A heterojunction bipolar transistor and a method for fabricating an HBT with self-aligned base metal contacts using a double photoresist, which requires fewer process steps than known methods, while minimizing damage to the active emitter contact region. In particular, a photoresist is used to form the emitter mesa. The emitter mesa photoresist is left on and a double polymethylmethacrylate (PMMA) and photoresist layer is then applied. The triple photoresist combination is patterned to create a non-critical lateral alignment for the base metal contacts to the emitter mesa, which permits selective base ohmic metal deposition and lift-off. By utilizing the double photoresist as opposed to a metal or dielectric for masking, an additional photolithography step and etching step is eliminated. By eliminating the need for an additional etching step, active regions of the semiconductors are prevented from being exposed to the etching step and possibly damaged.
摘要翻译：异相结双极晶体管和使用双光致抗蚀剂制造具有自对准基底金属触点的HBT的方法，其比已知方法需要更少的工艺步骤，同时最小化对有源发射极接触区域的损害。特别地，光致抗蚀剂用于形成发射台台面。留下发射台面光致抗蚀剂，然后施加双重聚甲基丙烯酸甲酯（PMMA）和光致抗蚀剂层。将三重光致抗蚀剂组合图案化以产生用于基底金属接触到发射极台面的非关键侧向对准，这允许选择性基极欧姆金属沉积和剥离。通过利用双光致抗蚀剂与用于掩蔽的金属或电介质相反，消除了额外的光刻步骤和蚀刻步骤。通过消除对另外的蚀刻步骤的需要，可以防止半导体的有源区暴露于蚀刻步骤并且可能被损坏。

8. 发明授权

US5736417A Method of fabricating double photoresist layer self-aligned heterojunction bipolar transistor 失效
标题翻译：制造双光致抗蚀剂层自对准异质结双极晶体管的方法
公开(公告)号：US5736417A
公开(公告)日：1998-04-07
申请号：US647609
申请日：1996-05-13
申请人： Aaron K. Oki , Donald K. Umemoto , Liem T. Tran , Dwight C. Streit
发明人： Aaron K. Oki , Donald K. Umemoto , Liem T. Tran , Dwight C. Streit
IPC分类号： H01L29/73 , H01L21/331 , H01L29/205 , H01L29/737 , H01L21/265
CPC分类号： H01L29/66318 , Y10S148/01 , Y10S148/011 , Y10S148/072 , Y10S148/10 , Y10S148/143
摘要： A heterejunction bipolar transistor and a method for fabricating an HBT with self-aligned base metal contacts using a double photoresist, which requires fewer process steps than known methods, while minimizing damage to the active emitter contact region. In particular, a photoresist is used to form the emitter mesa. The emitter mesa photoresist is left on and a double polymethylmethacrylate (PMMA) and photoresist layer is then applied. The triple photoresist combination is patterned to create a non-critical lateral alignment for the base metal contacts to the emitter mesa, which permits selective base ohmic metal deposition and lift-off. By utilizing the double photoresist as opposed to a metal or dielectric for masking, an additional photolithography step and etching step is eliminated. By eliminating the need for an additional etching step, active regions of the semiconductors are prevented from being exposed to the etching step and possibly damaged.
摘要翻译：双极性晶体管和使用双光致抗蚀剂制造具有自对准基底金属触点的HBT的方法，其需要比已知方法更少的工艺步骤，同时最小化对有源发射极接触区域的损害。特别地，光致抗蚀剂用于形成发射台台面。留下发射台面光致抗蚀剂，然后施加双重聚甲基丙烯酸甲酯（PMMA）和光致抗蚀剂层。将三重光致抗蚀剂组合图案化以产生用于基底金属接触到发射极台面的非关键侧向对准，这允许选择性基极欧姆金属沉积和剥离。通过利用双光致抗蚀剂与用于掩蔽的金属或电介质相反，消除了额外的光刻步骤和蚀刻步骤。通过消除对另外的蚀刻步骤的需要，可以防止半导体的有源区暴露于蚀刻步骤并且可能被损坏。

9. 发明授权

US5631477A Quaternary collector InAlAs-InGaAlAs heterojunction bipolar transistor 失效
标题翻译：四元收集器InAlAs-InGaAlAs异质结双极晶体管
公开(公告)号：US5631477A
公开(公告)日：1997-05-20
申请号：US490440
申请日：1995-06-02
申请人： Dwight C. Streit , Aaron K. Oki , Liem T. Tran
发明人： Dwight C. Streit , Aaron K. Oki , Liem T. Tran
IPC分类号： H01L29/73 , H01L21/331 , H01L29/08 , H01L29/205 , H01L29/737 , H01L31/0328 , H01L31/0336
CPC分类号： H01L29/0821 , H01L29/7371
摘要： An InAlAs/InGaAlAs heterojunction bipolar transistor that includes a constant quaternary InGaAlAs collector layer. Graded InGaAlAs collector layers are provided on each side of the quaternary collector layer to minimize transitions through the constant collector layer. The InAlAs/InGaAlAs HBT may also include one or more of a graded InGaAlAs emitter-base transition region, a graded-doping InGaAs base layer, and a graded-composition InGaAlAs base layer.
摘要翻译： InAlAs / InGaAlAs异质结双极晶体管，其包括恒定的四元InGaAlAs集电极层。渐变的InGaAlAs集电极层设置在四元集电极层的每一侧，以使通过恒定集电极层的过渡最小化。 InAlAs / InGaAlAs HBT还可以包括渐变的InGaAlAs发射极 - 基极化过渡区，渐变掺杂的InGaAs基层和渐变组成的InGaAlAs基层中的一个或多个。

10. 发明授权

US5448087A Heterojunction bipolar transistor with graded base doping 失效
标题翻译：异质结双极晶体管，具有分级基极掺杂
公开(公告)号：US5448087A
公开(公告)日：1995-09-05
申请号：US876199
申请日：1992-04-30
申请人： Swight C. Streit , Aaron K. Oki
发明人： Swight C. Streit , Aaron K. Oki
IPC分类号： H01L29/10 , H01L29/737 , H01L29/161 , H01L29/205 , H01L29/225
CPC分类号： H01L29/7371 , H01L29/1004
摘要： A heterojunction bipolar transistor with an exponentially graded base doping is disclosed, in addition to a technique for fabricating the transistor. In accordance with the preferred embodiment, the transistor employs a base with an exponentially graded Beryllium doping which varies from 5.times.10.sup.19 cm.sup.-3 at the base-emitter junction to 5.times.10.sup.18 cm.sup.-3 at the base-collector junction. The built-in field due to the exponentially graded doping profile significantly reduces base transit time despite bandgap narrowing associated with high base doping. Compared to devices with the same base thickness and uniform base doping, the cut off frequency is increased and the maximum frequency of oscillation is also increased. Also, consistently higher common emitter current gain results even though the Gummel number is twice as high and the base resistance is reduced by 40%.
摘要翻译：除了制造晶体管的技术之外，还公开了具有指数梯度的基极掺杂的异质结双极晶体管。根据优选实施例，晶体管采用具有指数级渐变的铍掺杂的基极，其在基极 - 集电极结处的基极 - 发射极结处从5×10 19 cm -3变化到5×10 18 cm -3。由于具有指数梯度的掺杂特性，内置场可显着降低基极通过时间，尽管与高基极掺杂相关的带隙变窄。与具有相同基底厚度和均匀基极掺杂的器件相比，截止频率增加，振荡的最大频率也增加。此外，尽管Gummel数量是两倍高，基极电阻降低了40％，但始终更高的公共发射极电流增益。

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