专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US06465289B1 Method of fabricating monolithic multifunction integrated circuit devices 失效
标题翻译：单片多功能集成电路器件的制造方法
公开(公告)号：US06465289B1
公开(公告)日：2002-10-15
申请号：US08675248
申请日：1996-07-01
申请人： Dwight C. Streit , Donald K. Umemoto , Aaron K. Oki , Kevin W. Kobayashi
发明人： Dwight C. Streit , Donald K. Umemoto , Aaron K. Oki , Kevin W. Kobayashi
IPC分类号： H01L21338
CPC分类号： H01L27/0605 , H01L21/8252
摘要： A method of selective molecular beam epitaxy for fabricating monolithically integrated circuit devices on a common substrate including combinations of PIN diode devices, HBT devices, HEMT devices and MESFET devices. The method includes depositing a profile layer of one of the devices on an appropriate substrate and then depositing a first dielectric layer over the profile layer. The profile layer and the dielectric layer are then etched to define a first device profile. A second profile layer for defining a second device is then deposited over the exposed substrate. The second profile is then selectively etched to define a second device profile. This process can be extended to more than two different device types monolithically integrated on a common substrate as long as the first developed devices are robust enough to handle the temperature cycling involved with developing the subsequent devices.
摘要翻译：一种用于在包括PIN二极管器件，HBT器件，HEMT器件和MESFET器件的组合的公共衬底上制造单片集成电路器件的选择性分子束外延的方法。该方法包括将一个器件的轮廓层沉积在合适的衬底上，然后在轮廓层上沉积第一介电层。然后蚀刻轮廓层和电介质层以限定第一装置轮廓。用于限定第二装置的第二轮廓层然后沉积在暴露的基底上。然后选择性地蚀刻第二轮廓以限定第二装置轮廓。只要第一个开发的设备足够坚固以处理与后续设备相关的温度循环，该过程可以扩展到单个集成在公共基板上的多于两种不同的设备类型。

2. 发明授权

US5262335A Method to produce complementary heterojunction bipolar transistors 失效
标题翻译：产生互补异质结双极晶体管的方法
公开(公告)号：US5262335A
公开(公告)日：1993-11-16
申请号：US772809
申请日：1991-10-08
申请人： Dwight C. Streit , Aaron K. Oki , Donald K. Umemoto , James R. Velebir, Jr.
发明人： Dwight C. Streit , Aaron K. Oki , Donald K. Umemoto , James R. Velebir, Jr.
IPC分类号： H01L29/205 , H01L21/331 , H01L21/8228 , H01L21/8252 , H01L27/06 , H01L27/082 , H01L29/73 , H01L29/737 , H01L21/265 , H01L29/70
CPC分类号： H01L21/8252 , H01L27/0605 , H01L27/0826 , Y10S148/072
摘要： Disclosed is a method for fabricating complementary heterojunction bipolar transistors on a common substrate. The method comprises the steps of depositing a PNP profile by molecular beam epitaxy on an appropriate substrate and then depositing a layer of silicon nitride on the PNP profile just deposited. The substrate is then heated in a vacuum in order to densify the silicon nitride. A mask and resist layer are used to produce the desired PNP profile patterns. The NPN profile is deposited on the area of the substrate etched away as well as on the silicon nitride layer protecting the already deposited PNP layers. The NPN profile is then patterned using a resist and masking process. The polycrystalline NPN area on top of the silicon nitride layer and the remaining silicon nitride layer are etched away forming two adjacent complementary NPN and PNP profiles on a common substrate. In the fabrication of the heterojunction bipolar transistor circuits, the P-ohmic contacts on both the NPN and PNP materials is evaporated at the appropriate locations simultaneously. All of the N-ohmic contacts are also deposited simultaneously. By this, the complementary dual heterojunction bipolar transistor device can be effectively fabricated with excellent DC and microwave capabilities.

3. 发明授权

US5892248A Double photoresist layer self-aligned heterojuction bipolar transistor 失效
标题翻译：双光阻层自对准异质双极晶体管
公开(公告)号：US5892248A
公开(公告)日：1999-04-06
申请号：US720388
申请日：1996-09-30
申请人： Aaron K. Oki , Donald K. Umemoto , Liem T. Tran , Dwight C. Streit
发明人： Aaron K. Oki , Donald K. Umemoto , Liem T. Tran , Dwight C. Streit
IPC分类号： H01L29/73 , H01L21/331 , H01L29/205 , H01L29/737 , H01L31/0328 , H01L27/082 , H01L31/0336
CPC分类号： H01L29/66318 , Y10S148/01 , Y10S148/011 , Y10S148/072 , Y10S148/10 , Y10S148/143
摘要： A heterojunction bipolar transistor and a method for fabricating an HBT with self-aligned base metal contacts using a double photoresist, which requires fewer process steps than known methods, while minimizing damage to the active emitter contact region. In particular, a photoresist is used to form the emitter mesa. The emitter mesa photoresist is left on and a double polymethylmethacrylate (PMMA) and photoresist layer is then applied. The triple photoresist combination is patterned to create a non-critical lateral alignment for the base metal contacts to the emitter mesa, which permits selective base ohmic metal deposition and lift-off. By utilizing the double photoresist as opposed to a metal or dielectric for masking, an additional photolithography step and etching step is eliminated. By eliminating the need for an additional etching step, active regions of the semiconductors are prevented from being exposed to the etching step and possibly damaged.
摘要翻译：异相结双极晶体管和使用双光致抗蚀剂制造具有自对准基底金属触点的HBT的方法，其比已知方法需要更少的工艺步骤，同时最小化对有源发射极接触区域的损害。特别地，光致抗蚀剂用于形成发射台台面。留下发射台面光致抗蚀剂，然后施加双重聚甲基丙烯酸甲酯（PMMA）和光致抗蚀剂层。将三重光致抗蚀剂组合图案化以产生用于基底金属接触到发射极台面的非关键侧向对准，这允许选择性基极欧姆金属沉积和剥离。通过利用双光致抗蚀剂与用于掩蔽的金属或电介质相反，消除了额外的光刻步骤和蚀刻步骤。通过消除对另外的蚀刻步骤的需要，可以防止半导体的有源区暴露于蚀刻步骤并且可能被损坏。

4. 发明授权

US5736417A Method of fabricating double photoresist layer self-aligned heterojunction bipolar transistor 失效
标题翻译：制造双光致抗蚀剂层自对准异质结双极晶体管的方法
公开(公告)号：US5736417A
公开(公告)日：1998-04-07
申请号：US647609
申请日：1996-05-13
申请人： Aaron K. Oki , Donald K. Umemoto , Liem T. Tran , Dwight C. Streit
发明人： Aaron K. Oki , Donald K. Umemoto , Liem T. Tran , Dwight C. Streit
IPC分类号： H01L29/73 , H01L21/331 , H01L29/205 , H01L29/737 , H01L21/265
CPC分类号： H01L29/66318 , Y10S148/01 , Y10S148/011 , Y10S148/072 , Y10S148/10 , Y10S148/143
摘要： A heterejunction bipolar transistor and a method for fabricating an HBT with self-aligned base metal contacts using a double photoresist, which requires fewer process steps than known methods, while minimizing damage to the active emitter contact region. In particular, a photoresist is used to form the emitter mesa. The emitter mesa photoresist is left on and a double polymethylmethacrylate (PMMA) and photoresist layer is then applied. The triple photoresist combination is patterned to create a non-critical lateral alignment for the base metal contacts to the emitter mesa, which permits selective base ohmic metal deposition and lift-off. By utilizing the double photoresist as opposed to a metal or dielectric for masking, an additional photolithography step and etching step is eliminated. By eliminating the need for an additional etching step, active regions of the semiconductors are prevented from being exposed to the etching step and possibly damaged.
摘要翻译：双极性晶体管和使用双光致抗蚀剂制造具有自对准基底金属触点的HBT的方法，其需要比已知方法更少的工艺步骤，同时最小化对有源发射极接触区域的损害。特别地，光致抗蚀剂用于形成发射台台面。留下发射台面光致抗蚀剂，然后施加双重聚甲基丙烯酸甲酯（PMMA）和光致抗蚀剂层。将三重光致抗蚀剂组合图案化以产生用于基底金属接触到发射极台面的非关键侧向对准，这允许选择性基极欧姆金属沉积和剥离。通过利用双光致抗蚀剂与用于掩蔽的金属或电介质相反，消除了额外的光刻步骤和蚀刻步骤。通过消除对另外的蚀刻步骤的需要，可以防止半导体的有源区暴露于蚀刻步骤并且可能被损坏。

5. 发明授权

US6037646A High-frequency GaAs substrate based schottky barrier diodes 失效
标题翻译：基于高频GaAs衬底的肖特基势垒二极管
公开(公告)号：US6037646A
公开(公告)日：2000-03-14
申请号：US865890
申请日：1997-05-30
申请人： Aaron K. Oki , Donald K. Umemoto , Liem T. Tran , Dwight C. Streit
发明人： Aaron K. Oki , Donald K. Umemoto , Liem T. Tran , Dwight C. Streit
IPC分类号： H01L21/329 , H01L29/47 , H01L29/872 , H01L27/095
CPC分类号： H01L29/66212 , H01L29/872
摘要： A Schottky barrier diode and a method for fabricating a Schottky barrier diode that utilizes HBT active device layers. The Schottky barrier diode is formed with a vertically integrated profile on a GaAs substrate, with a subcollector layer and a collector layer. A suitable dielectric material is deposited on top of the collector layer. Vias are formed in the collector layer and subcollector layer for the barrier and ohmic contacts. The collector via is relatively deeply etched into the collector layer to lower the series resistance between the barrier and ohmic contacts, which results in relatively higher cut-off frequency performance.
摘要翻译：一种肖特基势垒二极管和一种利用HBT有源器件层制造肖特基势垒二极管的方法。肖特基势垒二极管在GaAs衬底上形成垂直集成的形状，具有子集电极层和集电极层。合适的电介质材料沉积在集电极层的顶部。在集电极层和子集电极层中形成用于屏障和欧姆接触的通孔。集电极通孔相对深度地蚀刻到集电极层中，以降低阻挡层和欧姆接触之间的串联电阻，这导致相对较高的截止频率性能。

6. 发明授权

US5036286A Magnetic and electric force sensing method and apparatus 失效
标题翻译：磁电力传感方法及装置
公开(公告)号：US5036286A
公开(公告)日：1991-07-30
申请号：US501296
申请日：1990-03-12
申请人： James W. Holm-Kennedy , Donald K. Umemoto
发明人： James W. Holm-Kennedy , Donald K. Umemoto
IPC分类号： G01R33/038
CPC分类号： G01R33/038
摘要： A magnetic and electric force sensing method uses a force responsive transducer made of a micromachined, solid state magnetic sensor consisting of a central silicon platform surrounded and supported by a thin silicon membrane. The silicon substrate is placed over an aluminum pad recessed into a well on a supporting glass substrate. The magnetic sensor responds to a static method of measuring force whereby the Earth's magnetic field or magnetic field or other origin acts as an attractive or repulsive force towards the magnetic material placed onto the silicon platform. The magnetic force mechanically displaces the silicon platform and diaphragm membrane which is transduced to an electrical signal where a change in capacitance is measured. Geometry of the silicon platform, diaphragm membrane and glass well depth are used to affect the linearity, sensitivity and range of measurements of the magnetic sensor.
摘要翻译：磁力和电力感测方法使用由微加工的固态磁传感器制成的力响应传感器，该传感器由被薄硅膜包围和支撑的中心硅平台组成。将硅衬底放置在凹入到支撑玻璃衬底上的阱中的铝垫上。磁传感器响应测量力的静态方法，由此地球的磁场或磁场或其他原点作为朝向放置在硅平台上的磁性材料的有吸引力或排斥力。磁力机械地移动硅平台和隔膜，其被传导到电信号，其中测量电容的变化。使用硅平台，隔膜和玻璃深度的几何尺寸来影响磁传感器的线性度，灵敏度和测量范围。

7. 发明授权

US5930636A Method of fabricating high-frequency GaAs substrate-based Schottky barrier diodes 失效
标题翻译：制造高频GaAs衬底的肖特基势垒二极管的方法
公开(公告)号：US5930636A
公开(公告)日：1999-07-27
申请号：US645361
申请日：1996-05-13
申请人： Aaron K. Oki , Donald K. Umemoto , Liem T. Tran , Dwight C. Streit
发明人： Aaron K. Oki , Donald K. Umemoto , Liem T. Tran , Dwight C. Streit
IPC分类号： H01L21/329 , H01L29/47 , H01L29/872 , H01L21/331 , H01L21/00 , H01L21/338 , H01L31/0328
CPC分类号： H01L29/66212 , H01L29/872
摘要： A Schottky barrier diode and a method for fabricating a Schottky barrier diode that utilizes HBT active device layers. The Schottky barrier diode is formed with a vertically integrated profile on a GaAs substrate, with a subcollector layer and a collector layer. A suitable dielectric material is deposited on top of the collector layer. Vias are formed in the collector layer and subcollector layer for the barrier and ohmic contacts. The collector via is relatively deeply etched into the collector layer to lower the series resistance between the barrier and ohmic contacts, which results in relatively higher cut-off frequency performance.
摘要翻译：一种肖特基势垒二极管和一种利用HBT有源器件层制造肖特基势垒二极管的方法。肖特基势垒二极管在GaAs衬底上形成垂直集成的形状，具有子集电极层和集电极层。合适的电介质材料沉积在集电极层的顶部。在集电极层和子集电极层中形成用于屏障和欧姆接触的通孔。集电极通孔相对深度地蚀刻到集电极层中，以降低阻挡层和欧姆接触之间的串联电阻，这导致相对较高的截止频率性能。

8. 发明授权

US5840612A Method of fabricating very high gain heterojunction bipolar transistors 失效
标题翻译：制造超高增益异质结双极晶体管的方法
公开(公告)号：US5840612A
公开(公告)日：1998-11-24
申请号：US911388
申请日：1997-08-14
申请人： Aaron K. Oki , Dwight C. Streit , Donald K. Umemoto , Liem T. Tran
发明人： Aaron K. Oki , Dwight C. Streit , Donald K. Umemoto , Liem T. Tran
IPC分类号： H01L29/73 , H01L21/331 , H01L29/205 , H01L29/737
CPC分类号： H01L29/66318 , H01L29/7371
摘要： A heterojunction bipolar transistor with a vertically integrated profile includes a substrate layer, a collector contact layer, a collector layer, a base layer and an emitter layer, formed from AlGaAs, etched to form an emitter mesa leaving a relatively thin passivating layer, adjacent the emitter mesa. The base metal contacts are formed on the passivating layer, resulting in a wider bandgap, thus minimizing surface recombination velocity at the emitter-base junction and increasing the overall gain (.beta.) of the device. The base metal contacts are formed by evaporating a p-ohmic metal onto the n-type passivation layer. The p-ohmic contacts are annealed, resulting in p-type metal diffusion through the passivating layer and reaction with the base layer, resulting in ohmic contacts.
摘要翻译：具有垂直集成轮廓的异质结双极晶体管包括由AlGaAs形成的衬底层，集电极接触层，集电极层，基极层和发射极层，蚀刻形成离开较薄钝化层的发射极台面，邻近发射台台面贱金属触点形成在钝化层上，导致更宽的带隙，从而最小化发射极 - 基极结处的表面复合速度，并增加器件的总增益（β）。通过将p-欧姆金属蒸发到n型钝化层上而形成基底金属接触。 p欧姆接触被退火，导致p型金属通过钝化层扩散并与基层反应，导致欧姆接触。

9. 发明授权

US5323138A Reliable thin film resistors for integrated circuit applications 失效
标题翻译：用于集成电路应用的可靠的薄膜电阻
公开(公告)号：US5323138A
公开(公告)日：1994-06-21
申请号：US940556
申请日：1992-09-04
申请人： Aaron K. Oki , Donald K. Umemoto , Frank M. Yamada , Dwight C. Streit
发明人： Aaron K. Oki , Donald K. Umemoto , Frank M. Yamada , Dwight C. Streit
IPC分类号： H01C7/00 , H01C1/012
CPC分类号： H01C7/006
摘要： A thin film resistor with an insulating layer disposed between a substrate material and a resistor material is disclosed. Also, disclosed is a technique for fabricating this thin film resistor. In accordance with the preferred embodiment, the thin film resistor employs an insulating layer of silicon nitride with a thickness of 2000 .ANG.. The insulating layer prevents the resistor layer from diffusing into the substrate material which, in turn, significantly reduces variations in the resistor value during accelerated life testing. Compared to thin film resistors with a resistor layer evaporated directly upon a substrate material, reliability is increased from a few hundred hours up to thousands of hours. Also, the maximum current handling capability is increased by greater than one order of magnitude, which results in a thin film resistor which requires less surface area of a wafer.
摘要翻译：公开了一种具有设置在基板材料和电阻材料之间的绝缘层的薄膜电阻器。此外，公开了一种制造该薄膜电阻器的技术。根据优选实施例，薄膜电阻器使用厚度为2000安培的氮化硅绝缘层。绝缘层防止电阻层扩散到衬底材料中，这又显着地减少了加速寿命测试期间电阻值的变化。与直接在衬底材料上蒸发的电阻层的薄膜电阻器相比，可靠性从几百小时提高到数千小时。此外，最大电流处理能力增加大于一个数量级，这导致需要较少的晶片表面积的薄膜电阻器。

10. 发明授权

US4960177A Silicon membrane micro-scale 失效
标题翻译：硅膜微尺度
公开(公告)号：US4960177A
公开(公告)日：1990-10-02
申请号：US201881
申请日：1988-06-03
申请人： James W. Holm-Kennedy , Donald K. Umemoto
发明人： James W. Holm-Kennedy , Donald K. Umemoto
IPC分类号： G01G7/06 , G01L1/14 , G01L1/18
CPC分类号： G01L1/148 , G01G7/06 , G01L1/18
摘要： This invention relates to force responsive transducers and more particularly concerns a micromachined, solid state micro-scale. The device consists of a central silicon platorm surrounded and supported by a thin silicon membrane. The silicon substrate is placed over an aluminum pad recessed into a well on a supporting glass substrate. The micro-scale responds to a static method of measuring force, similar to a spring scale. A gravitational acceleration vector acting on a mass placed onto the device produces a force known as weight. The weight mechanically displaces the silicon platform and membrane which is transduced to an electrical signal where a change in capacitance is measured. Geometry of the silicon platform, membrane and glass well depth may be used to affect the linearity, sensitivity and range of measurement of the micro-scale.
摘要翻译：本发明涉及力响应传感器，并且更具体地涉及微加工的固态微尺度。该装置由被薄的硅膜包围和支撑的中心硅板。将硅衬底放置在凹入到支撑玻璃衬底上的阱中的铝垫上。微尺度响应于静态的测量力的方法，类似于弹簧秤。作用在放置在设备上的质量块上的重力加速度矢量产生称为重量的力。该重量将硅平台和膜机械地移位，该平台和膜被传导到测量电容变化的电信号。硅平台的几何形状，膜和玻璃深度可用于影响微尺度的线性度，灵敏度和测量范围。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式