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1. 发明申请

US20080283918A1 Ultra Thin Channel (UTC) MOSFET Structure Formed on BOX Regions Having Different Depths and Different Thicknesses Beneath the UTC and SourceDrain Regions and Method of Manufacture Thereof 有权
标题翻译：超薄通道（UTC）MOSFET结构形成在具有不同深度和不同厚度的BOX区域之下，UTC和SourceDrain区域及其制造方法
公开(公告)号：US20080283918A1
公开(公告)日：2008-11-20
申请号：US12166285
申请日：2008-07-01
申请人： Kangguo Cheng , Dureseti Chidambarrao , Brian Joseph Greene , Jack A. Mandelman , Kern Rim
发明人： Kangguo Cheng , Dureseti Chidambarrao , Brian Joseph Greene , Jack A. Mandelman , Kern Rim
IPC分类号： H01L29/786 , H01L21/336
CPC分类号： H01L21/2652 , H01L21/3003 , H01L29/1083 , H01L29/66545 , H01L29/6659 , H01L29/66772 , H01L29/7833 , H01L29/78603 , H01L29/78621 , H01L29/78696
摘要： A MOSFET structure includes a planar semiconductor substrate, a gate dielectric and a gate. A UT SOI channel extends to a first depth below the top surface of the substrate and is self-aligned to and is laterally coextensive with the gate. Source-drain regions, extend to a second depth greater than the first depth below the top surface, and are self-aligned to the UT channel region. A BOX1 region extends across the entire structure, and vertically from the second depth to a third depth below the top surface. An upper portion of a BOX2 region under the UT channel region is self-aligned to and is laterally coextensive with the gate, and extends vertically from the first depth to a third depth below the top surface, and where the third depth is greater than the second depth.
摘要翻译： MOSFET结构包括平面半导体衬底，栅极电介质和栅极。 UT SOI沟道延伸到衬底的顶表面下方的第一深度，并且与栅极自对准并且横向共延伸。源极 - 漏极区域延伸到大于顶部表面下方的第一深度的第二深度，并且与UT沟道区域自对准。 BOX 1区域跨越整个结构延伸，并且从第二深度垂直延伸到顶表面下方的第三深度。在UT通道区域下面的BOX 2区域的上部与栅极自对准并且与栅极横向共同延伸，并且从第一深度垂直延伸到顶表面下方的第三深度，并且其中第三深度大于第二个深度。

2. 发明授权

US07812397B2 Ultra thin channel (UTC) MOSFET structure formed on BOX regions having different depths and different thicknesses beneath the UTC and source/drain regions and method of manufacture thereof 有权
标题翻译：在UTC和源极/漏极区域下方形成具有不同深度和不同厚度的BOX区域上的超薄沟道（UTC）MOSFET结构及其制造方法
公开(公告)号：US07812397B2
公开(公告)日：2010-10-12
申请号：US12166285
申请日：2008-07-01
申请人： Changguo Cheng , Dureseti Chidambarrao , Brian Joseph Greene , Jack A. Mandelman , Kern Rim
发明人： Changguo Cheng , Dureseti Chidambarrao , Brian Joseph Greene , Jack A. Mandelman , Kern Rim
IPC分类号： H01L21/336
CPC分类号： H01L21/2652 , H01L21/3003 , H01L29/1083 , H01L29/66545 , H01L29/6659 , H01L29/66772 , H01L29/7833 , H01L29/78603 , H01L29/78621 , H01L29/78696
摘要： A MOSFET structure includes a planar semiconductor substrate, a gate dielectric and a gate. A UT SOI channel extends to a first depth below the top surface of the substrate and is self-aligned to and is laterally coextensive with the gate. Source-drain regions, extend to a second depth greater than the first depth below the top surface, and are self-aligned to the UT channel region. A BOX1 region extends across the entire structure, and vertically from the second depth to a third depth below the top surface. An upper portion of a BOX2 region under the UT channel region is self-aligned to and is laterally coextensive with the gate, and extends vertically from the first depth to a third depth below the top surface, and where the third depth is greater than the second depth.
摘要翻译： MOSFET结构包括平面半导体衬底，栅极电介质和栅极。 UT SOI沟道延伸到衬底的顶表面下方的第一深度，并且与栅极自对准并且横向共延伸。源极 - 漏极区域延伸到大于顶部表面下方的第一深度的第二深度，并且与UT沟道区域自对准。 BOX1区域跨越整个结构延伸，并且从第二深度垂直延伸到顶表面下方的第三深度。在UT通道区域下面的BOX2区域的上部与栅极自对准并且与栅极横向共同延伸，并且从第一深度垂直延伸到顶表面下方的第三深度，并且其中第三深度大于第二深度

3. 发明申请

US20070069300A1 PLANAR ULTRA-THIN SEMICONDUCTOR-ON-INSULATOR CHANNEL MOSFET WITH EMBEDDED SOURCE/DRAIN 审中-公开
标题翻译：具有嵌入式源/漏极的平面超薄半导体绝缘体通道MOSFET
公开(公告)号：US20070069300A1
公开(公告)日：2007-03-29
申请号：US11162959
申请日：2005-09-29
申请人： Kangguo Cheng , Dureseti Chidambarrao , Brian Greene , Jack Mandelman , Kern Rim
发明人： Kangguo Cheng , Dureseti Chidambarrao , Brian Greene , Jack Mandelman , Kern Rim
IPC分类号： H01L29/94
CPC分类号： H01L21/2652 , H01L21/02203 , H01L21/02238 , H01L21/02255 , H01L21/02299 , H01L21/31662 , H01L29/1083 , H01L29/66545 , H01L29/6659 , H01L29/7833
摘要： A MOSFET structure includes a planar semiconductor substrate, a gate dielectric and a gate. An ultra-thin (UT) semiconductor-on-insulator channel extends to a first depth below the top surface of the substrate and is self-aligned to and is laterally coextensive with the gate. Source-drain regions, extend to a second depth greater than the first depth below the top surface, and are self-aligned to the UT channel region. A first BOX region extends across the entire structure, and vertically from the second depth to a third depth below the top surface. An upper portion of a second BOX region under the UT channel region is self-aligned to and is laterally coextensive with the gate, and extends vertically from the first depth to a third depth below the top surface, and where the third depth is greater than the second depth.
摘要翻译： MOSFET结构包括平面半导体衬底，栅极电介质和栅极。超薄（UT）绝缘体上半导体通道延伸到衬底的顶表面下方的第一深度，并且与栅极自对准并且横向共延伸。源极 - 漏极区域延伸到大于顶部表面下方的第一深度的第二深度，并且与UT沟道区域自对准。第一BOX区域跨越整个结构延伸，并且从第二深度垂直延伸到顶表面下方的第三深度。在UT通道区域下面的第二BOX区域的上部自对准并且与栅极横向共同延伸，并且从第一深度垂直延伸到顶表面下方的第三深度，并且其中第三深度大于第二个深度。

4. 发明授权

US09059316B2 Structure and method for mobility enhanced MOSFETs with unalloyed silicide 有权
标题翻译：具有非合金化硅化物的迁移率增强型MOSFET的结构和方法
公开(公告)号：US09059316B2
公开(公告)日：2015-06-16
申请号：US13397860
申请日：2012-02-16
申请人： Yaocheng Liu , Dureseti Chidambarrao , Oleg Gluschenkov , Judson R. Holt , Renee T. Mo , Kern Rim
发明人： Yaocheng Liu , Dureseti Chidambarrao , Oleg Gluschenkov , Judson R. Holt , Renee T. Mo , Kern Rim
IPC分类号： H01L21/8238 , H01L21/768 , H01L21/84 , H01L27/12 , H01L29/66 , H01L29/78 , H01L27/32 , H01L29/165
CPC分类号： H01L21/823864 , H01L21/76886 , H01L21/823807 , H01L21/823814 , H01L21/84 , H01L27/1203 , H01L27/3279 , H01L29/165 , H01L29/665 , H01L29/6656 , H01L29/66628 , H01L29/66636 , H01L29/7848
摘要： While embedded silicon germanium alloy and silicon carbon alloy provide many useful applications, especially for enhancing the mobility of MOSFETs through stress engineering, formation of alloyed silicide on these surfaces degrades device performance. The present invention provides structures and methods for providing unalloyed silicide on such silicon alloy surfaces placed on semiconductor substrates. This enables the formation of low resistance contacts for both mobility enhanced PFETs with embedded SiGe and mobility enhanced NFETs with embedded Si:C on the same semiconductor substrate. Furthermore, this invention provides methods for thick epitaxial silicon alloy, especially thick epitaxial Si:C alloy, above the level of the gate dielectric to increase the stress on the channel on the transistor devices.
摘要翻译：虽然嵌入式硅锗合金和硅碳合金提供了许多有用的应用，特别是为了通过应力工程增强MOSFET的迁移率，在这些表面上形成合金化硅化物降低了器件性能。本发明提供了在放置在半导体衬底上的这种硅合金表面上提供非合金硅化物的结构和方法。这使得能够在具有嵌入式SiGe的迁移率增强的PFET和在同一半导体衬底上具有嵌入的Si：C的迁移率增强的NFET形成低电阻触点。此外，本发明提供了在栅极电介质的电平之上的厚外延硅合金，特别是厚的外延Si：C合金的方法，以增加晶体管器件上的沟道上的应力。

5. 发明申请

US20110147885A1 FORMATION OF IMPROVED SOI SUBSTRATES USING BULK SEMICONDUCTOR WAFERS 有权
标题翻译：使用块状半导体波形形成改进的SOI衬底
公开(公告)号：US20110147885A1
公开(公告)日：2011-06-23
申请号：US13037608
申请日：2011-03-01
申请人： William K. Henson , Dureseti Chidambarrao , Kern Rim , Hsingjen Wann , Hung Y. Ng
发明人： William K. Henson , Dureseti Chidambarrao , Kern Rim , Hsingjen Wann , Hung Y. Ng
IPC分类号： H01L23/58
CPC分类号： H01L21/764 , H01L21/76283
摘要： The present invention relates to a semiconductor-on-insulator (SOI) substrate having one or more device regions. Each device region comprises at least a base semiconductor substrate layer and a semiconductor device layer with a buried insulator layer located therebetween, while the semiconductor device layer is supported by one or more vertical insulating pillars. The vertical insulating pillars each preferably has a ledge extending between the base semiconductor substrate layer and the semiconductor device layer. The SOI substrates of the present invention can be readily formed from a precursor substrate structure with a “floating” semiconductor device layer that is spaced apart from the base semiconductor substrate layer by an air gap and is supported by one or more vertical insulating pillars. The air gap is preferably formed by selective removal of a sacrificial layer located between the base semiconductor substrate layer and the semiconductor device layer.
摘要翻译：本发明涉及具有一个或多个器件区域的绝缘体上半导体（SOI）衬底。每个器件区域至少包括基底半导体衬底层和其间设置有掩埋绝缘体层的半导体器件层，而半导体器件层由一个或多个垂直绝缘柱支撑。垂直绝缘柱各自优选地具有在基底半导体衬底层和半导体器件层之间延伸的凸缘。本发明的SOI衬底可以容易地由具有“浮动”半导体器件层的前体衬底结构形成，半导体器件层通过气隙与基底半导体衬底层间隔开并由一个或多个垂直绝缘柱支撑。气隙优选通过选择性地去除位于基底半导体衬底层和半导体器件层之间的牺牲层来形成。

6. 发明授权

US07615418B2 High performance stress-enhance MOSFET and method of manufacture 有权
标题翻译：高性能应力增强型MOSFET及其制造方法
公开(公告)号：US07615418B2
公开(公告)日：2009-11-10
申请号：US11380688
申请日：2006-04-28
申请人： Dureseti Chidambarrao , Ricardo A. Donaton , William K. Henson , Kern Rim
发明人： Dureseti Chidambarrao , Ricardo A. Donaton , William K. Henson , Kern Rim
IPC分类号： H01L21/8232 , H01L21/335
CPC分类号： H01L27/1203 , H01L21/823807 , H01L21/823814 , H01L29/1054 , H01L29/6653 , H01L29/66636 , H01L29/7843 , H01L29/7848 , Y10S438/938
摘要： A semiconductor structure and method of manufacturing and more particularly a CMOS device with a stress inducing material embedded in both gates and also in the source/drain region of the PFET. The PFET region and the NFET region having a different sized gate to vary the device performance of the NFET and the PFET.
摘要翻译：一种半导体结构和制造方法，更具体地说是具有嵌入在PFET的栅极和源极/漏极区域中的应力诱导材料的CMOS器件。 PFET区域和NFET区域具有不同尺寸的栅极，以改变NFET和PFET的器件性能。

7. 发明授权

US07452784B2 Formation of improved SOI substrates using bulk semiconductor wafers 有权
标题翻译：使用块状半导体晶片形成改进的SOI衬底
公开(公告)号：US07452784B2
公开(公告)日：2008-11-18
申请号：US11420279
申请日：2006-05-25
申请人： William K. Henson , Dureseti Chidambarrao , Kern Rim , Hsingjen Wann , Hung Y. Ng
发明人： William K. Henson , Dureseti Chidambarrao , Kern Rim , Hsingjen Wann , Hung Y. Ng
IPC分类号： H01L21/76
CPC分类号： H01L21/764 , H01L21/76283
摘要： The present invention relates to a semiconductor-on-insulator (SOI) substrate having one or more device regions. Each device region comprises at least a base semiconductor substrate layer and a semiconductor device layer with a buried insulator layer located therebetween, while the semiconductor device layer is supported by one or more vertical insulating pillars. The vertical insulating pillars each preferably has a ledge extending between the base semiconductor substrate layer and the semiconductor device layer. The SOI substrates of the present invention can be readily formed from a precursor substrate structure with a “floating” semiconductor device layer that is spaced apart from the base semiconductor substrate layer by an air gap and is supported by one or more vertical insulating pillars. The air gap is preferably formed by selective removal of a sacrificial layer located between the base semiconductor substrate layer and the semiconductor device layer.
摘要翻译：本发明涉及具有一个或多个器件区域的绝缘体上半导体（SOI）衬底。每个器件区域至少包括基底半导体衬底层和其间设置有掩埋绝缘体层的半导体器件层，而半导体器件层由一个或多个垂直绝缘柱支撑。垂直绝缘柱各自优选地具有在基底半导体衬底层和半导体器件层之间延伸的凸缘。本发明的SOI衬底可以容易地由具有“浮动”半导体器件层的前体衬底结构形成，半导体器件层通过气隙与基底半导体衬底层间隔开并由一个或多个垂直绝缘柱支撑。气隙优选通过选择性地去除位于基底半导体衬底层和半导体器件层之间的牺牲层来形成。

8. 发明申请

US20080128712A1 RAISED STI STRUCTURE AND SUPERDAMASCENE TECHNIQUE FOR NMOSFET PERFORMANCE ENHANCEMENT WITH EMBEDDED SILICON CARBON 有权
标题翻译：用于具有嵌入式硅碳的NMOSFET性能增强的提高的结构和超级散射技术
公开(公告)号：US20080128712A1
公开(公告)日：2008-06-05
申请号：US12028191
申请日：2008-02-08
申请人： Ashima B. Chakravarti , Dureseti Chidambarrao , Judson R. Holt , Yaocheng Liu , Kern Rim
发明人： Ashima B. Chakravarti , Dureseti Chidambarrao , Judson R. Holt , Yaocheng Liu , Kern Rim
IPC分类号： H01L27/092 , H01L29/778
CPC分类号： H01L21/823864 , H01L21/76224 , H01L21/823807 , H01L21/823814 , H01L21/823878 , H01L29/165 , H01L29/66628 , H01L29/7843 , H01L29/7848
摘要： An embedded silicon carbon (Si:C) having a substitutional carbon content in excess of one percent in order to effectively increase electron mobility by application of tension to a channel region of an NFET is achieved by overfilling a gap or trench formed by transistor gate structures with Si:C and polishing an etching the Si:C to or below a surface of a raised gate structure in a super-Damascene process, leaving Si:C only in selected regions above the transistor source and drain, even though processes capable of depositing Si:C with sufficiently high substitutional carbon content are inherently non-selective.
摘要翻译：通过过度填充由晶体管栅极结构形成的间隙或沟槽，实现了通过向NFET的沟道区域施加张力来有效地增加电子迁移率的具有超过1％的取代碳含量的嵌入式硅碳（Si：C）用Si：C，并在超级马赛克法中抛光将Si：C蚀刻到升高的栅极结构的表面或之下，即使在晶体管源极和漏极之上的选定区域中仅保留Si：C，即使能够沉积具有足够高的替代碳含量的Si：C固有地是非选择性的。

9. 发明申请

US20070275532A1 OPTIMIZED DEEP SOURCE/DRAIN JUNCTIONS WITH THIN POLY GATE IN A FIELD EFFECT TRANSISTOR 审中-公开
标题翻译：优化的深度源/漏极结与场效应晶体管中的多晶栅
公开(公告)号：US20070275532A1
公开(公告)日：2007-11-29
申请号：US11420053
申请日：2006-05-24
申请人： Dureseti Chidambarrao , Yaocheng Liu , Kern Rim
发明人： Dureseti Chidambarrao , Yaocheng Liu , Kern Rim
IPC分类号： H01L21/336
CPC分类号： H01L21/26513 , H01L21/2658 , H01L21/823814 , H01L21/823864 , H01L29/6653 , H01L29/66545 , H01L29/6656
摘要： A semiconductor structure in which the poly depletion and parasitic capacitance problems with poly-Si gate are reduced is provided as well as a method of making the same. The structure includes a thin poly-Si gate and optimized deep source/drain doping. The method changes the sequence of the different implantations steps and makes it possible to fabricate the structure without having dose loss or doping penetration problems. In accordance with the present invention, a sacrificial hard mask capping layer is used to block the high energy implantation and a 3-1 spacer (off-set spacer, first spacer and second spacer) scheme is used to optimize the source/drain doping profile. With this approach, the dose implanted into the thin poly-Si gate can be increased while the deep source/drain implantation can be optimized without worrying about the penetration problem.
摘要翻译：提供了其中减少多晶硅栅极的多晶硅耗尽和寄生电容问题的半导体结构及其制造方法。该结构包括薄多晶硅栅极和优化的深源极/漏极掺杂。该方法改变了不同植入步骤的顺序，并且使得可以制造结构而没有剂量损失或掺杂渗透问题。根据本发明，牺牲硬掩模覆盖层用于阻挡高能量注入，并且使用3-1间隔物（偏置间隔物，第一间隔物和第二间隔物）方案来优化源极/漏极掺杂分布。通过这种方法，可以增加注入薄多晶硅栅极的剂量，同时可以优化深源/漏植入，而不用担心渗透问题。

10. 发明申请

US20070122956A1 TRANSISTOR WITH DIELECTRIC STRESSOR ELEMENT FULLY UNDERLYING THE ACTIVE SEMICONDUCTOR REGION 失效
标题翻译：具有完全基于主动半导体区域的电介质压电元件的晶体管
公开(公告)号：US20070122956A1
公开(公告)日：2007-05-31
申请号：US11164632
申请日：2005-11-30
申请人： Dureseti Chidambarrao , Brian Greene , Kern Rim
发明人： Dureseti Chidambarrao , Brian Greene , Kern Rim
IPC分类号： H01L21/8234 , H01L31/00 , H01L21/336
CPC分类号： H01L29/7849 , H01L21/26513 , H01L21/31675 , H01L21/823807 , H01L21/823878 , H01L29/6659 , H01L29/66772 , H01L29/7833 , H01L29/78654
摘要： A compressive stress is applied to a channel region of a PFET by structure including a discrete dielectric stressor element that fully underlies the bottom surface of an active semiconductor region in which the source, drain and channel region of the PFET is disposed. In particular, the dielectric stressor element includes a region of collapsed oxide which fully contacts the bottom surface of the active semiconductor region such that it has an area coextensive with an area of the bottom surface. Bird's beak oxide regions at edges of the dielectric stressor element apply an upward force at edges of the dielectric stressor element to impart a compressive stress to the channel region of the PFET.
摘要翻译：压缩应力通过结构施加到PFET的沟道区域，其包括完全位于其中设置有PFET的源极，漏极和沟道区域的有源半导体区域的底表面的离散介电应激元件。特别地，介电应力元件包括与活性半导体区域的底表面完全接触的塌陷氧化物区域，使得其具有与底表面的区域共同延伸的区域。电介质应力元件边缘处的鸟喙氧化物区域在介质应力元件的边缘施加向上的力，以向PFET的沟道区域施加压应力。

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