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1. 发明授权

US07507631B2 Epitaxial filled deep trench structures 失效
标题翻译：外延填充深沟槽结构
公开(公告)号：US07507631B2
公开(公告)日：2009-03-24
申请号：US11428983
申请日：2006-07-06
申请人： Brian Joseph Greene , Judson Robert Holt
发明人： Brian Joseph Greene , Judson Robert Holt
IPC分类号： H01L21/336
CPC分类号： H01L29/7813 , H01L21/02532 , H01L21/02576 , H01L21/0262 , H01L21/22 , H01L29/0634 , H01L29/66734
摘要： A method of forming and a structure of an electronic device. The method including: forming a trench in a single-crystal semiconductor substrate; forming a dopant diffusion barrier layer on sidewalls and a bottom of the trench; and epitaxially growing a single-crystal semiconductor layer in the trench, the single-crystal semiconductor layer filling the trench, the dopant diffusion barrier layer a barrier to diffusion of semiconductor dopants. Also a power transistor formed by the same method.
摘要翻译：一种电子设备的形成方法和结构。该方法包括：在单晶半导体衬底中形成沟槽; 在沟槽的侧壁和底部上形成掺杂剂扩散阻挡层; 并且在沟槽中外延生长单晶半导体层，填充沟槽的单晶半导体层，掺杂剂扩散阻挡层是半导体掺杂剂的扩散的障碍。也是用相同的方法形成的功率晶体管。

2. 发明申请

US20080283918A1 Ultra Thin Channel (UTC) MOSFET Structure Formed on BOX Regions Having Different Depths and Different Thicknesses Beneath the UTC and SourceDrain Regions and Method of Manufacture Thereof 有权
标题翻译：超薄通道（UTC）MOSFET结构形成在具有不同深度和不同厚度的BOX区域之下，UTC和SourceDrain区域及其制造方法
公开(公告)号：US20080283918A1
公开(公告)日：2008-11-20
申请号：US12166285
申请日：2008-07-01
申请人： Kangguo Cheng , Dureseti Chidambarrao , Brian Joseph Greene , Jack A. Mandelman , Kern Rim
发明人： Kangguo Cheng , Dureseti Chidambarrao , Brian Joseph Greene , Jack A. Mandelman , Kern Rim
IPC分类号： H01L29/786 , H01L21/336
CPC分类号： H01L21/2652 , H01L21/3003 , H01L29/1083 , H01L29/66545 , H01L29/6659 , H01L29/66772 , H01L29/7833 , H01L29/78603 , H01L29/78621 , H01L29/78696
摘要： A MOSFET structure includes a planar semiconductor substrate, a gate dielectric and a gate. A UT SOI channel extends to a first depth below the top surface of the substrate and is self-aligned to and is laterally coextensive with the gate. Source-drain regions, extend to a second depth greater than the first depth below the top surface, and are self-aligned to the UT channel region. A BOX1 region extends across the entire structure, and vertically from the second depth to a third depth below the top surface. An upper portion of a BOX2 region under the UT channel region is self-aligned to and is laterally coextensive with the gate, and extends vertically from the first depth to a third depth below the top surface, and where the third depth is greater than the second depth.
摘要翻译： MOSFET结构包括平面半导体衬底，栅极电介质和栅极。 UT SOI沟道延伸到衬底的顶表面下方的第一深度，并且与栅极自对准并且横向共延伸。源极 - 漏极区域延伸到大于顶部表面下方的第一深度的第二深度，并且与UT沟道区域自对准。 BOX 1区域跨越整个结构延伸，并且从第二深度垂直延伸到顶表面下方的第三深度。在UT通道区域下面的BOX 2区域的上部与栅极自对准并且与栅极横向共同延伸，并且从第一深度垂直延伸到顶表面下方的第三深度，并且其中第三深度大于第二个深度。

3. 发明授权

US07405131B2 Method and structure to prevent silicide strapping of source/drain to body in semiconductor devices with source/drain stressor 有权
标题翻译：用于防止源/漏应力源的半导体器件中源极/漏极穿过物体的方法和结构
公开(公告)号：US07405131B2
公开(公告)日：2008-07-29
申请号：US11182681
申请日：2005-07-16
申请人： Yung Fu Chong , Brian Joseph Greene
发明人： Yung Fu Chong , Brian Joseph Greene
IPC分类号： H01L21/20 , H01L21/336
CPC分类号： H01L29/665 , H01L29/165 , H01L29/6653 , H01L29/6656 , H01L29/66636 , H01L29/7834 , H01L29/7848
摘要： The example embodiments disclose devices and methods to prevent silicide strapping of the Source/Drain to Body in semiconductor devices with S/D stressor. We provide isolation regions in the substrate and a gate structure over the substrate. We form recesses in the substrate adjacent to the gate structure with disposable spacers and adjacent to the isolation regions. We provide stressor regions filling the recesses. The stress region can have a pit adjacent the isolation regions. We form stressor spacers at least partially in the pit on the sidewalls of the stressor regions. We form silicide regions over the stressor regions. The spacer on the stressor regions sidewalls inhibit the formation of silicide at the stressor region edge during the silicide process, thus preventing silicide strapping of the Source/Drain to Body.
摘要翻译：示例性实施例公开了用于在具有S / D应力源的半导体器件中防止源极/漏极到体的硅化物贴带的器件和方法。我们提供衬底中的隔离区域和衬底上的栅极结构。我们在邻近栅极结构的衬底的基板上形成有一次性间隔件并与隔离区相邻的凹槽。我们提供填充凹槽的压力区。应力区域可以具有邻近隔离区域的凹坑。我们在应力区域的侧壁上的凹坑中至少部分地形成应力源间隔物。我们在应力区域形成硅化物区域。应力区域侧壁上的间隔物在硅化物处理期间抑制了应力区域边缘处的硅化物的形成，从而防止了源/漏对体的硅化物带。

4. 发明授权

US07542330B2 SRAM with asymmetrical pass gates 失效
标题翻译：具有不对称传递门的SRAM
公开(公告)号：US07542330B2
公开(公告)日：2009-06-02
申请号：US11763555
申请日：2007-06-15
申请人： Brian Joseph Greene , Chun-Yung Sung , Clement Wann , Robert Chi-Foon Wong , Ying Zhang
发明人： Brian Joseph Greene , Chun-Yung Sung , Clement Wann , Robert Chi-Foon Wong , Ying Zhang
IPC分类号： G11C11/00
CPC分类号： G11C11/412
摘要： An SRAM having asymmetrical FET pass gates and a method of fabricating an SRAM having asymmetrical FET pass gates. The pass gates are asymmetrical with respect to current conduction from the drain to the source of the pass gate being different from current conduction from the source to the drain of the pass gate.
摘要翻译：具有不对称FET通孔的SRAM和制造具有不对称FET通孔的SRAM的方法。相对于从栅极的漏极到源极的电流传导，通路门不对称，不同于从通过栅极的源极到漏极的电流传导。

5. 发明申请

US20080310212A1 SRAM WITH ASYMMETRICAL PASS GATES 失效
标题翻译：带不对称门的SRAM
公开(公告)号：US20080310212A1
公开(公告)日：2008-12-18
申请号：US11763555
申请日：2007-06-15
申请人： Brian Joseph Greene , Chun-Yung Sung , Clement Wann , Robert Chi-Foon Wong , Ying Zhang
发明人： Brian Joseph Greene , Chun-Yung Sung , Clement Wann , Robert Chi-Foon Wong , Ying Zhang
IPC分类号： G11C11/40
CPC分类号： G11C11/412
摘要： An SRAM having asymmetrical FET pass gates and a method of fabricating an SRAM having asymmetrical FET pass gates. The pass gates are asymmetrical with respect to current conduction from the drain to the source of the pass gate being different from current conduction from the source to the drain of the pass gate.
摘要翻译：具有不对称FET通孔的SRAM和制造具有不对称FET通孔的SRAM的方法。相对于从栅极的漏极到源极的电流传导，通路门不对称，不同于从通过栅极的源极到漏极的电流传导。

6. 发明申请

US20080211054A1 METHODS FOR FORMING GERMANIUM-ON-INSULATOR SEMICONDUCTOR STRUCTURES USING A POROUS LAYER AND SEMICONDUCTOR STRUCTURES FORMED BY THESE METHODS 有权
标题翻译：使用这种方法形成多孔层和半导体结构形成绝缘体绝缘体半导体结构的方法
公开(公告)号：US20080211054A1
公开(公告)日：2008-09-04
申请号：US12120455
申请日：2008-05-14
申请人： Kangguo Cheng , Brian Joseph Greene , Jack Allan Mandelman
发明人： Kangguo Cheng , Brian Joseph Greene , Jack Allan Mandelman
IPC分类号： H01L29/16
CPC分类号： H01L21/76251 , H01L21/76245 , Y10S438/933
摘要： A semiconductor structure that includes a monocrystalline germanium-containing layer, preferably substantially pure germanium, a substrate, and a buried insulator layer separating the germanium-containing layer from the substrate. A porous layer, which may be porous silicon, is formed on a substrate and a germanium-containing layer is formed on the porous silicon layer. The porous layer may be converted to a layer of oxide, which provides the buried insulator layer. Alternatively, the germanium-containing layer may be transferred from the porous layer to an insulating layer on another substrate. After the transfer, the insulating layer is buried between the latter substrate and the germanium-containing layer.
摘要翻译：一种半导体结构，其包括单晶含锗层，优选基本上纯的锗，衬底和将锗含量层与衬底分离的掩埋绝缘体层。在基板上形成可以是多孔硅的多孔层，在多孔硅层上形成含锗层。多孔层可以转化成一层氧化物，这提供了埋层绝缘体层。或者，含锗层可以从多孔层转移到另一衬底上的绝缘层。在转移之后，绝缘层被埋在后面的衬底和含锗层之间。

7. 发明授权

US07939413B2 Embedded stressor structure and process 有权
标题翻译：嵌入式应力器结构与过程
公开(公告)号：US07939413B2
公开(公告)日：2011-05-10
申请号：US11297522
申请日：2005-12-08
申请人： Yung Fu Chong , Zhijiong Luo , Joo Chan Kim , Brian Joseph Greene , Kern Rim
发明人： Yung Fu Chong , Zhijiong Luo , Joo Chan Kim , Brian Joseph Greene , Kern Rim
IPC分类号： H01L21/336
CPC分类号： H01L21/823814 , H01L21/823807 , H01L29/165 , H01L29/66545 , H01L29/66628 , H01L29/66636 , H01L29/7848
摘要： An example embodiments are structures and methods for forming an FET with embedded stressor S/D regions (e.g., SiGe), a doped layer below the embedded S/D region adjacent to the isolation regions, and a stressor liner over reduced spacers of the FET gate. An example method comprising the following. We provide a gate structure over a first region in a substrate. The gate structure is comprised of gate dielectric, a gate, and sidewall spacers. We provide isolation regions in the first region spaced from the gate structure; and a channel region in the substrate under the gate structure. We form S/D recesses in the first region in the substrate adjacent to the sidewall spacers. We form S/D stressor regions filling the S/D recesses. The S/D stressor regions can be thicker adjacent to the gate structure than adjacent to the isolation regions; We implant dopant ions into the S/D stressor regions and into the substrate below the S/D stressor regions adjacent to the isolation regions to form upper stressor doped regions.
摘要翻译：示例性实施例是用于形成具有嵌入的应力源S / D区域（例如，SiGe）的FET的结构和方法，位于与隔离区域相邻的嵌入式S / D区域下方的掺杂层，以及FET上减少的间隔物上的应力衬垫门。包括以下的示例性方法。我们在衬底的第一区域上提供栅极结构。栅极结构由栅极电介质，栅极和侧壁间隔物组成。我们提供与栅极结构间隔开的第一区域中的隔离区域; 以及栅极结构下的衬底中的沟道区。我们在邻近侧壁间隔物的衬底的第一区域中形成S / D凹槽。形成填充S / D凹槽的S / D应力区域。与隔离区相邻的S / D应力区可以比栅极结构更厚; 我们将掺杂剂离子注入到S / D应力区域中并进入与隔离区域相邻的S / D应力区域下方的衬底中以形成上部应力源掺杂区域。

8. 发明授权

US07812397B2 Ultra thin channel (UTC) MOSFET structure formed on BOX regions having different depths and different thicknesses beneath the UTC and source/drain regions and method of manufacture thereof 有权
标题翻译：在UTC和源极/漏极区域下方形成具有不同深度和不同厚度的BOX区域上的超薄沟道（UTC）MOSFET结构及其制造方法
公开(公告)号：US07812397B2
公开(公告)日：2010-10-12
申请号：US12166285
申请日：2008-07-01
申请人： Changguo Cheng , Dureseti Chidambarrao , Brian Joseph Greene , Jack A. Mandelman , Kern Rim
发明人： Changguo Cheng , Dureseti Chidambarrao , Brian Joseph Greene , Jack A. Mandelman , Kern Rim
IPC分类号： H01L21/336
CPC分类号： H01L21/2652 , H01L21/3003 , H01L29/1083 , H01L29/66545 , H01L29/6659 , H01L29/66772 , H01L29/7833 , H01L29/78603 , H01L29/78621 , H01L29/78696
摘要： A MOSFET structure includes a planar semiconductor substrate, a gate dielectric and a gate. A UT SOI channel extends to a first depth below the top surface of the substrate and is self-aligned to and is laterally coextensive with the gate. Source-drain regions, extend to a second depth greater than the first depth below the top surface, and are self-aligned to the UT channel region. A BOX1 region extends across the entire structure, and vertically from the second depth to a third depth below the top surface. An upper portion of a BOX2 region under the UT channel region is self-aligned to and is laterally coextensive with the gate, and extends vertically from the first depth to a third depth below the top surface, and where the third depth is greater than the second depth.
摘要翻译： MOSFET结构包括平面半导体衬底，栅极电介质和栅极。 UT SOI沟道延伸到衬底的顶表面下方的第一深度，并且与栅极自对准并且横向共延伸。源极 - 漏极区域延伸到大于顶部表面下方的第一深度的第二深度，并且与UT沟道区域自对准。 BOX1区域跨越整个结构延伸，并且从第二深度垂直延伸到顶表面下方的第三深度。在UT通道区域下面的BOX2区域的上部与栅极自对准并且与栅极横向共同延伸，并且从第一深度垂直延伸到顶表面下方的第三深度，并且其中第三深度大于第二深度

9. 发明授权

US07767541B2 Methods for forming germanium-on-insulator semiconductor structures using a porous layer and semiconductor structures formed by these methods 失效
标题翻译：使用多孔层形成绝缘体上半导体结构的方法和通过这些方法形成的半导体结构的方法
公开(公告)号：US07767541B2
公开(公告)日：2010-08-03
申请号：US11259297
申请日：2005-10-26
申请人： Kangguo Cheng , Brian Joseph Greene , Jack Allan Mandelman
发明人： Kangguo Cheng , Brian Joseph Greene , Jack Allan Mandelman
IPC分类号： H01L21/30 , H01L21/46
CPC分类号： H01L21/76251 , H01L21/76245 , Y10S438/933
摘要： A semiconductor structure that includes a monocrystalline germanium-containing layer, preferably substantially pure germanium, a substrate, and a buried insulator layer separating the germanium-containing layer from the substrate. A porous layer, which may be porous silicon, is formed on a substrate and a germanium-containing layer is formed on the porous silicon layer. The porous layer may be converted to a layer of oxide, which provides the buried insulator layer. Alternatively, the germanium-containing layer may be transferred from the porous layer to an insulating layer on another substrate. After the transfer, the insulating layer is buried between the latter substrate and the germanium-containing layer.
摘要翻译：一种半导体结构，其包括单晶含锗层，优选基本上纯的锗，衬底和将锗含量层与衬底分离的掩埋绝缘体层。在基板上形成可以是多孔硅的多孔层，在多孔硅层上形成含锗层。多孔层可以转化成一层氧化物，这提供了埋层绝缘体层。或者，含锗层可以从多孔层转移到另一衬底上的绝缘层。在转移之后，绝缘层被埋在后面的衬底和含锗层之间。

10. 发明授权

US07442618B2 Method to engineer etch profiles in Si substrate for advanced semiconductor devices 有权
标题翻译：在先进半导体器件的Si衬底中设计蚀刻轮廓的方法
公开(公告)号：US07442618B2
公开(公告)日：2008-10-28
申请号：US11182682
申请日：2005-07-16
申请人： Yung Fu Chong , Brian Joseph Greene , Siddhartha Panda , Nivo Rovedo
发明人： Yung Fu Chong , Brian Joseph Greene , Siddhartha Panda , Nivo Rovedo
IPC分类号： H01L21/44
CPC分类号： H01L29/7833 , H01L21/76232 , H01L29/165 , H01L29/6659 , H01L29/66628 , H01L29/7846 , H01L29/7848
摘要： Structures and methods for forming keyhole shaped regions for isolation and/or stressing the substrate are shown. In a first embodiment, we form an inverted keyhole shaped trench in the substrate in the first opening preferably using a two step etch. Next, we fill the inverted keyhole trench with a material that insulates and/or creates stress on the sidewalls of the inverted keyhole trench. In a second embodiment, we form a keyhole stressor region adjacent to the gate and isolation structures. The keyhole stressor region creates stress near the channel region of the FET to improve FET performance. The stressor region can be filled with an insulator or a semiconductor material.
摘要翻译：示出了用于形成用于隔离和/或应力衬底的键孔区域的结构和方法。在第一实施例中，我们在第一开口中的衬底中形成倒置的键孔形沟槽，优选地使用两步蚀刻。接下来，我们使用在倒置的键孔沟槽的侧壁上绝缘和/或产生应力的材料填充倒置的孔眼沟槽。在第二实施例中，我们形成与栅极和隔离结构相邻的键孔应力区域。键孔应力区域在FET的通道区域附近产生应力，以提高FET性能。应力区域可以用绝缘体或半导体材料填充。

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