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1. 发明授权

US06330682B1 Semiconductor memory device achieving faster operation based on earlier timings of latch operations 失效
标题翻译：半导体存储器件基于较早的锁存操作定时实现更快的操作
公开(公告)号：US06330682B1
公开(公告)日：2001-12-11
申请号：US09104374
申请日：1998-06-25
申请人： Kazuyuki Kanazashi , Naoharu Shinozaki , Toshiya Uchida
发明人： Kazuyuki Kanazashi , Naoharu Shinozaki , Toshiya Uchida
IPC分类号： G06F104
CPC分类号： G11C8/18
摘要： A semiconductor memory device having an internal circuit includes a command decoder which decodes input-command signals to supply decoded-command signals, an address-latch-signal-generation circuit, operating faster than the command decoder, which decodes the input-command signals to supply an address-latch signal, and a control circuit which controls the internal circuit based on the decoded-command signals. The semiconductor memory device further includes an address-input circuit which latches an address signal in response to the address-latch signal.
摘要翻译：具有内部电路的半导体存储器件包括命令解码器，其对输入命令信号进行解码以提供解码命令信号，地址锁存信号产生电路比命令解码器运行得更快，将输入命令信号解码为提供地址锁存信号，以及基于解码指令信号控制内部电路的控制电路。半导体存储器件还包括地址输入电路，其响应于地址锁存信号而锁存地址信号。

2. 发明授权

US08064264B2 Ornand flash memory and method for controlling the same 有权
标题翻译： Ornand闪存及其控制方法
公开(公告)号：US08064264B2
公开(公告)日：2011-11-22
申请号：US11974295
申请日：2007-10-11
申请人： Naoharu Shinozaki , Masao Taguchi , Akira Ogawa , Takuo Ito
发明人： Naoharu Shinozaki , Masao Taguchi , Akira Ogawa , Takuo Ito
IPC分类号： G11C16/06
CPC分类号： G11C16/26
摘要： A semiconductor device that includes: a memory cell array that includes non-volatile memory cells; an area that is contained in the memory cell array and stores area data; a first storage unit that holds data transferred from the memory cell array, and outputs the data; and a control circuit that selects between a primary reading mode for causing the first storage unit to hold the area data transferred from the memory cell array and to output the area data, and a secondary reading mode for causing the first storage unit to hold a plurality of pieces of divisional data formed by dividing the area data and transferred from the memory cell array and to output the divisional data.
摘要翻译：一种半导体器件，包括：包括非易失性存储单元的存储单元阵列; 包含在存储单元阵列中并存储区域数据的区域; 第一存储单元，保存从存储单元阵列传送的数据，并输出数据; 以及控制电路，其选择用于使所述第一存储单元保持从所述存储单元阵列传送的区域数据并输出所述区域数据的主读取模式;以及辅助读取模式，用于使所述第一存储单元保持多个通过划分区域数据并从存储单元阵列传送而形成的分割数据并输出分割数据。

3. 发明授权

US07471585B2 Semiconductor memory 失效
标题翻译：半导体存储器
公开(公告)号：US07471585B2
公开(公告)日：2008-12-30
申请号：US11508917
申请日：2006-08-24
申请人： Naoharu Shinozaki , Tatsuya Kanda , Takahiko Sato , Akihiro Funyu
发明人： Naoharu Shinozaki , Tatsuya Kanda , Takahiko Sato , Akihiro Funyu
IPC分类号： G11C7/00
CPC分类号： G11C29/028 , G11C11/401 , G11C11/406 , G11C11/40603 , G11C29/02 , G11C29/50012 , G11C29/50016 , G11C2029/0403 , G11C2211/4061
摘要： A refresh signal is output in response to a refresh request generated at predetermined cycles, and a refresh operation is performed. The refresh operation ends when a conflict occurs between an access request and the refresh request. Consequently, an access operation corresponding to the access request can be started earlier with a reduction in access time. The access time can be reduced further by changing the end time of the refresh operation in accordance with the timing of supply of the access request. Since a test circuit for notifying the state of the refresh operation to exterior is formed, the operation margin of the refresh operation can be evaluated in a short time. As a result, it is possible to reduce the development period of the semiconductor memory.
摘要翻译：响应于以预定周期产生的刷新请求输出刷新信号，并执行刷新操作。刷新操作在访问请求与刷新请求之间发生冲突时结束。因此，与访问请求相对应的访问操作可以随着访问时间的减少而更早地启动。可以根据访问请求的提供时间改变刷新操作的结束时间，进一步减少访问时间。由于形成用于将刷新操作的状态通知给外部的测试电路，因此可以在短时间内评估刷新操作的操作余量。结果，可以减少半导体存储器的显影周期。

4. 发明授权

US07113441B2 Semiconductor memory 有权
标题翻译：半导体存储器
公开(公告)号：US07113441B2
公开(公告)日：2006-09-26
申请号：US11057841
申请日：2005-02-15
申请人： Naoharu Shinozaki , Tatsuya Kanda , Takahiko Sato , Akihiro Funyu
发明人： Naoharu Shinozaki , Tatsuya Kanda , Takahiko Sato , Akihiro Funyu
IPC分类号： G11C7/00
CPC分类号： G11C29/028 , G11C11/401 , G11C11/406 , G11C11/40603 , G11C29/02 , G11C29/50012 , G11C29/50016 , G11C2029/0403 , G11C2211/4061
摘要： A refresh signal is output in response to a refresh request generated at predetermined cycles, and a refresh operation is performed. The refresh operation ends when a conflict occurs between an access request and the refresh request. Consequently, an access operation corresponding to the access request can be started earlier with a reduction in access time. The access time can be reduced further by changing the end time of the refresh operation in accordance with the timing of supply of the access request. Since a test circuit for notifying the state of the refresh operation to exterior is formed, the operation margin of the refresh operation can be evaluated in a short time. As a result, it is possible to reduce the development period of the semiconductor memory.
摘要翻译：响应于以预定周期产生的刷新请求输出刷新信号，并执行刷新操作。刷新操作在访问请求与刷新请求之间发生冲突时结束。因此，与访问请求相对应的访问操作可以随着访问时间的减少而更早地启动。可以根据访问请求的提供时间改变刷新操作的结束时间，进一步减少访问时间。由于形成用于将刷新操作的状态通知给外部的测试电路，因此可以在短时间内评估刷新操作的操作余量。结果，可以减少半导体存储器的显影周期。

5. 发明授权

US06438667B1 Semiconductor memory and memory system 有权
标题翻译：半导体存储器和存储器系统
公开(公告)号：US06438667B1
公开(公告)日：2002-08-20
申请号：US09236338
申请日：1999-01-25
申请人： Naoharu Shinozaki
发明人： Naoharu Shinozaki
IPC分类号： G06F1214
CPC分类号： G11C29/1201 , G11C29/48 , G11C2029/2602
摘要： When a test instruction signal is outputted from a command decoder, a test mode decoder receives the test instruction signal and outputs a test signal. When a DQM switch circuit receives the test signal, the DQM switch circuit outputs a mask/disable signal (MASK0 or MASK1) inputted to any one of two mask/disable terminals (DQML, DQMU) as a mask/disable signal inputted from the two terminals DQML and DQMU to a write amplifier/sense buffer. Therefore, it is possible to execute a mask/disable operation for all of input and output data with one of the two mask/disable terminals.
摘要翻译：当从命令解码器输出测试指令信号时，测试模式解码器接收测试指令信号并输出测试信号。当DQM开关电路接收到测试信号时，DQM开关电路输出输入到两个屏蔽/禁止端子（DQML，DQMU）中的任何一个的屏蔽/禁止信号（MASK0或MASK1）作为从两个输入端口输入的屏蔽/禁止信号端子DQML和DQMU到写入放大器/检测缓冲器。因此，可以通过两个屏蔽/禁止端子之一对所有的输入和输出数据执行掩码/禁止操作。

6. 发明授权

US06339353B1 Input circuit of a memory having a lower current dissipation 有权
标题翻译：具有较低电流消耗的存储器的输入电路
公开(公告)号：US06339353B1
公开(公告)日：2002-01-15
申请号：US09542454
申请日：2000-04-04
申请人： Hiroyoshi Tomita , Naoharu Shinozaki
发明人： Hiroyoshi Tomita , Naoharu Shinozaki
IPC分类号： H03K3356
CPC分类号： G11C7/109 , G11C8/06 , H03K3/012 , H03K3/356121 , H03K3/356139 , H03K5/133 , H03K5/1534
摘要： The present invention provides an input circuit having small current consumption in a clock synchronization type semiconductor integrated circuit. The input circuit is activated by an activation signal to receive an input signal and an activation signal generating circuit generates the activation signal. The activation signal generating circuit activates intermittently the activation signal for a time shorter than a period of a clock signal and including a setup time and a hold time of the input signal in order to activate the input circuit. The input circuit is activated only for the limited time of one period of the clock signal and therefore current consumption can be reduced.
摘要翻译：本发明提供一种在时钟同步型半导体集成电路中具有小电流消耗的输入电路。输入电路由激活信号激活以接收输入信号，激活信号产生电路产生激活信号。激活信号发生电路间歇地激活比时钟信号周期短的时间的激活信号，并且包括输入信号的建立时间和保持时间，以激活输入电路。输入电路仅在时钟信号的一个周期的有限时间内被激活，因此可以减少电流消耗。

7. 发明授权

US06317372B1 Semiconductor memory device equipped with serial/parallel conversion circuitry for testing memory cells 失效
标题翻译：半导体存储器件配有用于测试存储单元的串行/并行转换电路
公开(公告)号：US06317372B1
公开(公告)日：2001-11-13
申请号：US09528983
申请日：2000-03-20
申请人： Tomonori Hayashi , Naoharu Shinozaki , Hiroyoshi Tomita
发明人： Tomonori Hayashi , Naoharu Shinozaki , Hiroyoshi Tomita
IPC分类号： G11C2900
CPC分类号： G11C29/40 , G11C29/34 , G11C29/48
摘要： An input conversion unit converts serial data supplied from the exterior into parallel data. Each of the converted parallel data is respectively written into a plurality of memory cell areas. An output conversion unit converts parallel data constructed by data read from each memory cell area into serial data. An operational unit is activated during a testing mode so as to logically operate on the parallel data read from each memory cell area. By writing predetermined data into each memory cell area in advance, it is confirmed by a logic operation that correct data is stored in each memory cell area. The data can be checked simultaneously for the plurality of memory cell areas so that the operation test in the memory cell areas can be carried out at high speed. Besides, serial data accepted, twice per cycle of a data strobe signal, is converted into parallel data. Each of the converted parallel data is respectively written into a first memory cell area and a second memory cell area. Parallel data read from the first and second memory cell area is logically operated in a testing mode and the operation result is output at once in synchronization with the clock signal. Accordingly, the data can be checked simultaneously for the first and the second memory cell area so that the operation test in the memory cell areas can be carried out at high speed.
摘要翻译：输入转换单元将从外部提供的串行数据转换为并行数据。每个转换的并行数据分别写入多个存储单元区域。输出转换单元将从每个存储单元区域读取的数据构成的并行数据转换为串行数据。在测试模式期间激活操作单元，以便对从每个存储单元区域读取的并行数据进行逻辑运算。通过预先将预定数据写入每个存储单元区域，通过逻辑运算来确认正确的数据被存储在每个存储单元区域中。可以同时检查多个存储单元区域的数据，使得可以高速地执行存储单元区域中的操作测试。此外，接受数据选通信号每周期两次的串行数据被转换为并行数据。每个转换的并行数据分别被写入第一存储器单元区域和第二存储器单元区域中。从第一和第二存储单元区域读取的并行数据在测试模式下逻辑运行，并且与时钟信号同步地一次输出运算结果。因此，可以同时检查第一和第二存储单元区域的数据，使得可以高速地执行存储单元区域中的操作测试。

8. 发明授权

US06256240B1 Semiconductor memory circuit 有权
标题翻译：半导体存储电路
公开(公告)号：US06256240B1
公开(公告)日：2001-07-03
申请号：US09385006
申请日：1999-08-27
申请人： Naoharu Shinozaki
发明人： Naoharu Shinozaki
IPC分类号： G11C700
CPC分类号： G11C29/46
摘要： A semiconductor memory circuit includes a circuit which generates a test mode entry signal which enables a test mode directed to evaluating the semiconductor memory circuit. The circuit generates the test mode entry signal on the basis of a plurality of combinations of a predetermined command signal sequentially applied from an outside of the semiconductor memory circuit.
摘要翻译：半导体存储器电路包括产生测试模式输入信号的电路，该测试模式输入信号使得能够进行评估半导体存储器电路的测试模式。该电路根据从半导体存储电路的外部依次施加的预定指令信号的多个组合，生成测试模式输入信号。

9. 发明申请

US20110051529A1 MEMORY DEVICE 有权
标题翻译：内存设备
公开(公告)号：US20110051529A1
公开(公告)日：2011-03-03
申请号：US12548034
申请日：2009-08-26
申请人： Naoharu Shinozaki , Satoshi Moue
发明人： Naoharu Shinozaki , Satoshi Moue
IPC分类号： G11C7/10 , G11C7/00 , G11C8/16
CPC分类号： G11C7/22 , G11C7/10
摘要： Systems and methods for reading data from or writing data to a memory device. The methods involve receiving a first pulse signal having a first pulse frequency at the memory device. The methods also involve generating, at the memory device, a second pulse signal using the first pulse signal. The second pulse signal is a compliment of the first pulse signal. The second pulse signal has a second pulse frequency that is equal to the first frequency. The first pulse signal is used to control first read/write operations so that first data is output from or input to the memory device at a first data rate. The first and second pulse signals are used to control second read/write operations so that second data is output from or input to the memory device at a second data rate. The second data rate is twice the first data rate.
摘要翻译：用于从存储器件读取数据或将数据写入存储器件的系统和方法。所述方法包括在存储器件处接收具有第一脉冲频率的第一脉冲信号。该方法还涉及在存储器件中使用第一脉冲信号产生第二脉冲信号。第二脉冲信号是第一脉冲信号的补充。第二脉冲信号具有等于第一频率的第二脉冲频率。第一脉冲信号用于控制第一读/写操作，使得第一数据以第一数据速率从存储器件输出或输入到存储器件。第一和第二脉冲信号用于控制第二读/写操作，使得第二数据以第二数据速率从存储器件输出或输入到存储器件。第二个数据速率是第一个数据速率的两倍。

10. 发明授权

US07894238B2 Semiconductor memory device with stacked memory cell structure 有权
标题翻译：具有堆叠存储单元结构的半导体存储器件
公开(公告)号：US07894238B2
公开(公告)日：2011-02-22
申请号：US12253619
申请日：2008-10-17
申请人： Naoharu Shinozaki
发明人： Naoharu Shinozaki
IPC分类号： G11C5/06
CPC分类号： H01L27/0688 , H01L27/24
摘要： A semiconductor device including: a first memory cell including a non-volatile first variable resistance element that stores data by varying a resistance value and a selection transistor that selects the first variable resistance element; a first memory layer provided with more than one such first memory cell arranged in a plane; a second memory cell including a non-volatile second variable resistance element that stores data by varying a resistance value and a selection diode that selects the second variable resistance element; and a second memory layer provided with more than one such second memory cell arranged in a plane; wherein more than one such second memory layer is stacked over the first memory layer.
摘要翻译：一种半导体器件，包括：第一存储单元，包括通过改变电阻值存储数据的非易失性第一可变电阻元件和选择第一可变电阻元件的选择晶体管; 设置有布置在平面中的多于一个这样的第一存储单元的第一存储器层; 包括通过改变电阻值存储数据的非易失性第二可变电阻元件和选择第二可变电阻元件的选择二极管的第二存储单元; 以及第二存储器层，其设置有布置在平面中的多于一个的所述第二存储器单元; 其中多于一个这样的第二存储器层被堆叠在第一存储器层上。

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