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1. 发明授权

US06330682B1 Semiconductor memory device achieving faster operation based on earlier timings of latch operations 失效
标题翻译：半导体存储器件基于较早的锁存操作定时实现更快的操作
公开(公告)号：US06330682B1
公开(公告)日：2001-12-11
申请号：US09104374
申请日：1998-06-25
申请人： Kazuyuki Kanazashi , Naoharu Shinozaki , Toshiya Uchida
发明人： Kazuyuki Kanazashi , Naoharu Shinozaki , Toshiya Uchida
IPC分类号： G06F104
CPC分类号： G11C8/18
摘要： A semiconductor memory device having an internal circuit includes a command decoder which decodes input-command signals to supply decoded-command signals, an address-latch-signal-generation circuit, operating faster than the command decoder, which decodes the input-command signals to supply an address-latch signal, and a control circuit which controls the internal circuit based on the decoded-command signals. The semiconductor memory device further includes an address-input circuit which latches an address signal in response to the address-latch signal.
摘要翻译：具有内部电路的半导体存储器件包括命令解码器，其对输入命令信号进行解码以提供解码命令信号，地址锁存信号产生电路比命令解码器运行得更快，将输入命令信号解码为提供地址锁存信号，以及基于解码指令信号控制内部电路的控制电路。半导体存储器件还包括地址输入电路，其响应于地址锁存信号而锁存地址信号。

2. 发明授权

US06337833B1 Memory device 有权
标题翻译：内存设备
公开(公告)号：US06337833B1
公开(公告)日：2002-01-08
申请号：US09346919
申请日：1999-07-02
申请人： Kazuyuki Kanazashi , Toshiya Uchida , Masaki Okuda
发明人： Kazuyuki Kanazashi , Toshiya Uchida , Masaki Okuda
IPC分类号： G11C800
CPC分类号： G11C7/225 , G11C7/1051 , G11C7/1072
摘要： One aspect of the present invention is that, when the memory is in the non-power-down state, the supply of clock signals to the data output circuit is limited to the read status after the reception of a read command, and no clock signal supply is performed when either the active status or the write status is in effect. In the best aspect, furthermore, in the read status after the reception of a read command, the supply of clock signals to the data output circuit starts after a number of clock signals corresponding to a set CAS latency following the read command, and stops after a number of clock signals corresponding to a set burst length, after the output of the read out data from the data output circuit starts. Accordingly, even in the non-power-down state, clock signals are only supplied during the time required for the read out data to be actually output from the data output circuit to the outside, whereby it is possible to reduce the number of clock signal supply actions that require large current drive.
摘要翻译：本发明的一个方面是，当存储器处于非掉电状态时，向数据输出电路提供时钟信号被限制在接收到读命令之后的读状态，并且没有时钟信号当活动状态或写入状态都有效时执行供电。此外，在最佳方面，在接收到读取命令之后的读取状态下，在与读取命令之后的设定的CAS延迟相对应的多个时钟信号之后，向数据输出电路提供时钟信号开始，并且在后面停止在从数据输出电路输出读出数据开始之后，与设定的突发长度对应的多个时钟信号。因此，即使在非掉电状态下，时钟信号仅在从数据输出电路向外部输出的读出数据所需的时间内提供，从而可以减少时钟信号的数量提供需要大电流驱动的动作。

3. 发明授权

US06567923B2 Semiconductor memory device achieving faster operation based on earlier timings of latch operations 有权
公开(公告)号：US06567923B2
公开(公告)日：2003-05-20
申请号：US09875127
申请日：2001-07-30
申请人： Kazuyuki Kanazashi , Toshiya Uchida
发明人： Kazuyuki Kanazashi , Toshiya Uchida
IPC分类号： G06F104
CPC分类号： G11C8/18
摘要： A semiconductor memory device having an internal circuit includes a command decoder which decodes input-command signals to supply decoded-command signals, an address-latch-signal-generation circuit, operating faster than the command decoder, which decodes the input-command signals to supply an address-latch signal, and a control circuit which controls the internal circuit based on the decoded-command signals. The semiconductor memory device further includes an address-input circuit which latches an address signal in response to the address-latch signal.

4. 发明授权

US6147915A Semiconductor integrated circuit 有权
标题翻译：半导体集成电路
公开(公告)号：US6147915A
公开(公告)日：2000-11-14
申请号：US296547
申请日：1999-04-22
申请人： Makoto Yanagisawa , Kazuyuki Kanazashi , Yuji Kurita
发明人： Makoto Yanagisawa , Kazuyuki Kanazashi , Yuji Kurita
IPC分类号： G11C7/10 , G11C7/22 , G11C8/10 , G11C8/18 , G11C7/00 , G11C8/00
CPC分类号： G11C8/10 , G11C7/1045 , G11C7/1072 , G11C7/22 , G11C8/18 , G11C2207/108
摘要： A semiconductor integrated circuit includes a plurality of circuits operating in parallel in accordance with a timing signal and having an enabled state and a disabled state, a control circuit setting each of the plurality of circuits to the enable state or the disabled state in accordance with an operation mode, and a timing adjustment circuit which adjusts the timing signal in accordance with a number of circuits which are in the enabled state.
摘要翻译：半导体集成电路包括根据定时信号并行操作并具有使能状态和禁用状态的多个电路，控制电路将多个电路中的每一个设置为使能状态或禁用状态，根据操作模式，以及定时调整电路，其根据处于使能状态的电路的数量来调整定时信号。

5. 发明授权

US07760837B2 Synchronization determination method and apparatus 有权
标题翻译：同步确定方法和装置
公开(公告)号：US07760837B2
公开(公告)日：2010-07-20
申请号：US11412947
申请日：2006-04-28
申请人： Kazuyuki Kanazashi
发明人： Kazuyuki Kanazashi
IPC分类号： H04L7/00
CPC分类号： H04L7/10
摘要： A synchronization determination method includes: a synchronization determining step of determining whether or not synchronization has been successfully performed by detecting a synchronous pattern from the demodulated data input as a data stream; a synchronization probability determining step of determining whether or not there is a probability that synchronization is successfully performed using the progress of detecting a synchronous pattern in the synchronization determining step; and a synchronization determination discard step of discarding a determination in the synchronization determining step when it is determined in the synchronization probability determining step that there is no probability that synchronization is successfully performed, and passing control to the process performed when it is determined in the synchronization determining step that synchronization has not been successfully performed.
摘要翻译：同步确定方法包括：同步确定步骤，通过从作为数据流输入的解调数据检测同步模式来确定是否已经成功执行了同步; 同步概率确定步骤，用于使用所述同步确定步骤中的同步模式的检测步骤来确定是否存在成功执行同步的概率; 以及同步确定丢弃步骤，当在所述同步概率确定步骤中确定没有成功执行同步的可能性时，丢弃所述同步确定步骤中的确定，并且当所述同步确定步骤确定时执行的处理确定步骤尚未成功执行同步。

6. 发明授权

US07742469B2 Data input circuit and semiconductor device utilizing data input circuit 有权
标题翻译：数据输入电路和半导体器件利用数据输入电路
公开(公告)号：US07742469B2
公开(公告)日：2010-06-22
申请号：US11501848
申请日：2006-08-10
申请人： Kazuyuki Kanazashi
发明人： Kazuyuki Kanazashi
IPC分类号： H04L12/50 , H04Q11/00 , G11C7/10 , G11C7/22
CPC分类号： G06F5/00
摘要： A data input circuit converts input serial data to n-bit parallel data, and outputs the n-bit parallel data by following an address signal. The data input circuit includes a data shifting unit including a plurality of columns, and sequentially shifting the input serial data through the plurality of columns; and a selection unit selecting a column among the plurality of columns as an input column by following the address signal, wherein the input serial data is inputted to the data shifting unit through the input column. Thus, the data input device can speed up its processing speed with a simplified circuit structure whose circuit size is reduced.
摘要翻译：数据输入电路将输入串行数据转换为n位并行数据，并通过跟随地址信号输出n位并行数据。数据输入电路包括数据移位单元，其包括多列，并且顺序地移位通过多列的输入串行数据; 以及选择单元，通过跟随地址信号来选择多列中的列作为输入列，其中输入的串行数据通过输入列输入到数据移位单元。因此，数据输入装置可以通过电路尺寸减小的简化电路结构来加快其处理速度。

7. 发明授权

US07724859B2 Synchronizing apparatus and synchronizing method 有权
标题翻译：同步装置和同步方法
公开(公告)号：US07724859B2
公开(公告)日：2010-05-25
申请号：US11442993
申请日：2006-05-31
申请人： Kazuyuki Kanazashi
发明人： Kazuyuki Kanazashi
IPC分类号： H04L7/00
CPC分类号： H04L7/042 , H04L7/10 , H04L27/3827 , H04L27/3863
摘要： A synchronizing apparatus comprises a normal lock synchronization detecting unit for detecting synchronization by detecting from demodulated data a synchronization pattern in a normal lock state, and a pseudo lock synchronization detecting unit for detecting synchronization by detecting from the demodulated data a synchronization pattern in a pseudo lock state.
摘要翻译：同步装置包括通常锁定同步检测单元，用于通过从解调数据检测正常锁定状态下的同步模式来检测同步;以及伪锁定同步检测单元，用于通过从解调数据检测伪锁中的同步模式来检测同步州。

8. 发明授权

US07173994B2 Timing recovery circuit with multiple stages 有权
标题翻译：多级定时恢复电路
公开(公告)号：US07173994B2
公开(公告)日：2007-02-06
申请号：US11357031
申请日：2006-02-21
申请人： Kazuyuki Kanazashi
发明人： Kazuyuki Kanazashi
IPC分类号： H04L3/24
CPC分类号： H04L7/0029 , H04L7/0012 , H04L7/0331
摘要： A timing recovery circuit includes a first oscillating circuit configured to produce a first timing signal, a second oscillating circuit configured to produce a second timing signal, a first decimation circuit coupled to a supply node of a first clock signal and to the first oscillating circuit to produce a second clock signal made by decimating pulses of the first clock signal in response to the first timing signal, and a second decimation circuit coupled to the first decimation circuit and to the second oscillating circuit to produce a third clock signal made by decimating pulses of the second clock signal in response to the second timing signal, wherein one of the first timing signal and the second timing signal has a fixed cycle, and another one has a cycle responsive to feedback control.
摘要翻译：定时恢复电路包括被配置为产生第一定时信号的第一振荡电路，被配置为产生第二定时信号的第二振荡电路，耦合到第一时钟信号的电源节点的第一抽取电路和第一振荡电路，产生通过响应于第一定时信号抽取第一时钟信号的脉冲而产生的第二时钟信号，以及耦合到第一抽取电路和第二振荡电路的第二抽取电路，以产生第三时钟信号，所述第二时钟信号响应于所述第二定时信号，其中所述第一定时信号和所述第二定时信号中的一个具有固定周期，并且另一个具有响应于反馈控制的周期。

9. 发明授权

US06343041B1 Semiconductor integrated circuit 有权
公开(公告)号：US06343041B1
公开(公告)日：2002-01-29
申请号：US09635868
申请日：2000-08-10
申请人： Kazuyuki Kanazashi
发明人： Kazuyuki Kanazashi
IPC分类号： G11C700
CPC分类号： G11C11/4093 , G11C7/1006 , G11C7/1072
摘要： The semiconductor integrated circuit comprises a parallel-serial converter for converting parallel data read from memory cells into serial data and a switch control circuit for receiving a control signal and controlling the parallel-serial converter. The parallel-serial converter has a plurality of switches connected in a predetermined order. The switch control circuit controls the order of connecting the switches in accordance with the control signal so that parallel data are converted into serial data in a predetermined bit order. This minimizes delay elements formed on the transmission paths of parallel data. Specifically, for example, it eliminates the need for a conversion circuit for changing the bit order of parallel data. This results in faster data read operations from memory cells. Each of the switches in the parallel-serial converter operates in synchronization with a clock signal supplied from the exterior. This can heighten the speed of read operations, for example, in a clock-synchronous type of semiconductor integrated circuit having memory cells.

10. 发明授权

US5629645A Transmission-line-voltage control circuit and electronic device including the control circuit 失效
标题翻译：传输线路电压控制电路和包括控制电路的电子设备
公开(公告)号：US5629645A
公开(公告)日：1997-05-13
申请号：US403945
申请日：1995-03-14
申请人： Yoshinori Okajima , Kazuyuki Kanazashi
发明人： Yoshinori Okajima , Kazuyuki Kanazashi
IPC分类号： G06F3/00 , G06F12/00 , G06F13/16 , G11C11/401 , H03K5/02 , H04L25/02 , H04L25/03 , H03K19/094
CPC分类号： H04L25/0264 , H04L25/03834
摘要： A transmission-line-voltage control circuit for controlling a level of a transmission line is disclosed. A signal of a first level indicating a logic high and a signal of a second level indicating a logic low are supplied to the transmission line. The transmission-line voltage control circuit includes a circuit connected to the transmission line. This circuit reduces, after the signal of the first level is supplied to the transmission line, the level of the transmission line to a third level which indicates the logic high and is less than the first level. And also the circuit increases, after the signal of the second level is supplied to the transmission line, the level of the transmission line to a fourth level which indicates the logic low and is higher than the second level.
摘要翻译：公开了一种用于控制传输线的电平的传输线电压控制电路。指示逻辑高的第一电平的信号和指示逻辑低的第二电平的信号被提供给传输线。传输线电压控制电路包括连接到传输线的电路。在将第一电平的信号提供给传输线之后，该电路将传输线的电平降低到指示逻辑高并且小于第一电平的第三电平。并且在第二电平的信号被提供给传输线之后，电路也增加了传输线的电平到指示逻辑低并且高于第二电平的第四电平。

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