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1. 发明授权

US5043297A Wiring method of on-chip modification for an LSI 失效
标题翻译： LSI的片上修改接线方法
公开(公告)号：US5043297A
公开(公告)日：1991-08-27
申请号：US571179
申请日：1990-08-22
申请人： Katsuyoshi Suzuki , Masato Hamamoto , Takahiko Takahashi
发明人： Katsuyoshi Suzuki , Masato Hamamoto , Takahiko Takahashi
IPC分类号： H01L21/3205 , H01L21/768 , H01L21/82 , H01L23/52 , H01L23/525
CPC分类号： H01L21/76894 , H01L21/76888 , H01L23/5258 , H01L2924/0002 , Y10S438/94
摘要： A wiring method for on-chip modification of an LSI is provided to cut a portion of a wire inside of the LSI with an ion beam and connect the wire with a laser induced CVD process so that the logic is changed when developing the LSI. The method comprises the steps of cutting or connecting an LSI wire even if another wire is located above or adjacent to the LSI wire and repairing an excessively cut or connected portion. The method thus makes it possible to widen the range of a possible cutting or connection spot, thereby making any kind of repairs possible, some of which would have never been repaired by the conventional method.
摘要翻译：提供了用于片上修改LSI的布线方法，用离子束切割LSI内的线的一部分，并且用激光感应CVD工艺连接线，使得在开发LSI时逻辑被改变。该方法包括如下步骤：即使另一个线位于LSI线上方或邻近LSI线并修复过度切割或连接部分，也可以切断或连接LSI线。因此，该方法可以扩大可能的切割或连接点的范围，从而进行任何种类的修理成为可能，其中一些将永远不会被常规方法修复。

2. 发明授权

US06670201B2 Manufacturing method of semiconductor device 失效
公开(公告)号：US06670201B2
公开(公告)日：2003-12-30
申请号：US09939670
申请日：2001-08-28
申请人： Masaki Kouno , Masato Hamamoto , Atsushi Wakahara , Hideyuki Takahashi , Keiichi Higeta , Mitsugu Kusunoki , Kazutaka Mori
发明人： Masaki Kouno , Masato Hamamoto , Atsushi Wakahara , Hideyuki Takahashi , Keiichi Higeta , Mitsugu Kusunoki , Kazutaka Mori
IPC分类号： G01R3126
CPC分类号： G01R31/3004
摘要： A manufacturing method of a semiconductor device capable of obtaining highly reliable semiconductor devices with the realization of high integration and high speed intended is provided. During processes after a desired circuit including a CMOS static type circuit is formed on a semiconductor substrate until product shipment, a first operation of feeding a predetermined input signal to the circuit and retrieving a first output signal corresponding to it and a second operation of giving an operating condition of increasing an ON resistance value of MOSFETs constituting the CMOS static type circuit and retrieving a second output signal corresponding to the condition are conducted, and a testing step of determining a failure by the first output signal varying from the second output signal.

3. 发明授权

US06359472B2 Semiconductor integrated circuit and its fabrication method 有权
标题翻译：半导体集成电路及其制造方法
公开(公告)号：US06359472B2
公开(公告)日：2002-03-19
申请号：US09791831
申请日：2001-02-26
申请人： Michiaki Nakayama , Masato Hamamoto , Kazutaka Mori , Satoru Isomura
发明人： Michiaki Nakayama , Masato Hamamoto , Kazutaka Mori , Satoru Isomura
IPC分类号： H01L2704
CPC分类号： H01L27/1104 , H01L27/0921 , H01L27/0928
摘要： An integrated circuit having a CMOS circuit constituted by electrically connecting an n-type well 2, in which p-channel transistor Tp of the CMOS circuit is set, with a supply line Vdd through switching transistor Tps, and electrically connecting a p-type well 3, in which n-channel transistor Tn of the CMOS circuit is set, with supply line Vss through switching transistor Tns. Thermal runaway due to leakage current can be controlled by turning off switching transistors Tps and Tns and supplying potentials suitable for a test to the n-type well 2 and the p-type well 3 from an external unit when the integrated circuit is being tested. Fluctuations of the latch-up phenomenon and operation speed can be prevented by turning on switching transistors Tps and Tns and setting the n-type well 2 and the p-type well 3 to the voltages Vdd and Vss, respectively.
摘要翻译：具有CMOS电路的集成电路，其通过将n型阱2（其中CMOS电路的p沟道晶体管Tp被置位）与通过开关晶体管Tps的电源线Vdd电连接而构成，并且电连接p型阱如图3所示，其中CMOS电路的n沟道晶体管Tn被设置，电源线Vss通过开关晶体管Tns。当集成电路被测试时，可以通过关断开关晶体管Tps和Tns并从外部单元向n型阱2和p型阱3提供适合于测试的电位来控制由于泄漏电流引起的热失控。通过接通开关晶体管Tps和Tns并分别将n型阱2和p型阱3分别设置为电压Vdd和Vss可以防止闩锁现象和操作速度的波动。

4. 发明授权

US06194915B1 Semiconductor integrated circuit device and process for manufacturing the same 失效
标题翻译：半导体集成电路器件及其制造方法
公开(公告)号：US06194915B1
公开(公告)日：2001-02-27
申请号：US09077829
申请日：1998-06-04
申请人： Michiaki Nakayama , Masato Hamamoto , Kazutaka Mori , Satoru Isomura
发明人： Michiaki Nakayama , Masato Hamamoto , Kazutaka Mori , Satoru Isomura
IPC分类号： H01L2704
CPC分类号： H01L27/1104 , H01L27/0921 , H01L27/0928
摘要： To provide a semiconductor integrated circuit having a CMOS circuit constituted by electrically connecting an n-type well 2, in which one transistor Tp for constituting the CMOS circuit is set, with a first power-supply-voltage line Vdd through a switching transistor Tps, and electrically connecting a p-type well 3 in which the other transistor Tn for constituting the CMOS circuit is set with a second power-supply-voltage line Vss through a switching transistor Tns. Moreover, the semiconductor integrated circuit is constituted so that thermal runaway due to leakage current can be controlled by turning off the switching transistors Tps and Tns and supplying a potential suitable for a test to the n-type well 2 and the p-type well 3 from an external unit when the semiconductor integrated circuit is being tested. Furthermore, the semiconductor integrated circuit is constituted so that fluctuations of the latch-up phenomenon and operation speed can be prevented by turning on the switching transistors Tps and Tns and setting the n-type well 2 and the p-type well 3 to the power supply voltages Vdd and Vss, respectively.
摘要翻译：为了提供具有CMOS电路的半导体集成电路，该CMOS电路通过电连接构成CMOS电路的一个晶体管Tp与通过开关晶体管Tps的第一电源电压线Vdd电连接的n型阱2，并且通过开关晶体管Tns将构成CMOS电路的另一个晶体管Tn与p型阱3电连接到第二电源电压线Vss。此外，半导体集成电路被构造成使得可以通过关断开关晶体管Tps和Tns并且向n型阱2和p型阱3提供适合于测试的电位来控制由漏电流引起的热失控当半导体集成电路被测试时，从外部单元。此外，半导体集成电路构成为通过接通开关晶体管Tps和Tns并将n型阱2和p型阱3设置为功率来防止闩锁现象和操作速度的波动电源电压Vdd和Vss。

5. 发明授权

US06937068B2 Semiconductor integrated circuit 失效
标题翻译：半导体集成电路
公开(公告)号：US06937068B2
公开(公告)日：2005-08-30
申请号：US10642138
申请日：2003-08-18
申请人： Michiaki Nakayama , Masato Hamamoto , Kazutaka Mori , Satoru Isomura
发明人： Michiaki Nakayama , Masato Hamamoto , Kazutaka Mori , Satoru Isomura
IPC分类号： H01L27/092 , H01L27/11 , H01L27/04
CPC分类号： H01L27/1104 , H01L27/0921 , H01L27/0928
摘要： An integrated circuit having a CMOS circuit constituted by electrically connecting an n-type well 2, in which p-channel transistor Tp of the CMOS circuit is set, with a supply line Vdd through switching transistor Tps, and electrically connecting a p-type well 3, in which n-channel transistor Tn of the CMOS circuit is set, with supply line Vss through switching transistor Tns. Thermal runaway due to leakage current can be controlled by turning off switching transistors Tps and Tns and supplying potentials suitable for a test to the n-type well 2 and the p-type well 3 from an external unit when the integrated circuit is being tested. Fluctuations of the latch-up phenomenon and operation speed can be prevented by turning on switching transistors Tps and Tns and setting the n-type well 2 and the p-type well 3 to the voltages Vdd and Vss, respectively.
摘要翻译：具有CMOS电路的集成电路，其通过将n型阱2（其中CMOS电路的p沟道晶体管Tp被置位）与通过开关晶体管Tps的电源线Vdd电连接而构成，并且电连接p型阱如图3所示，其中CMOS电路的n沟道晶体管Tn被设置，电源线Vss通过开关晶体管Tns。当集成电路被测试时，可以通过关断开关晶体管Tps和Tns并从外部单元向n型阱2和p型阱3提供适合于测试的电位来控制由于泄漏电流引起的热失控。通过接通开关晶体管Tps和Tns并分别将n型阱2和p型阱3分别设置为电压Vdd和Vss可以防止闩锁现象和操作速度的波动。

6. 发明授权

US5140184A Clock feeding circuit and clock wiring system 失效
标题翻译：时钟馈电电路和时钟接线系统
公开(公告)号：US5140184A
公开(公告)日：1992-08-18
申请号：US615930
申请日：1990-11-20
申请人： Masato Hamamoto , Toshio Yamada
发明人： Masato Hamamoto , Toshio Yamada
IPC分类号： G06F1/10 , H01L21/82 , H01L21/822 , H01L27/04 , H03K5/15 , H03K19/0175 , H04L7/00
CPC分类号： H03K5/15013 , G06F1/10
摘要： Dummy power source wirings connected to a power source wiring are arranged in empty regions among the signal wirings that cross the clock wirings, the dummy power source wirings being arranged over or under the clock wirings in a manner to cross the clock wirings. The dummy power source wirings are formed to equalize the capacitances of the wirings whose lengths should be equalized among, for example, the clock distributing circuits or among the clock drivers.
摘要翻译：连接到电源布线的虚拟电源布线布置在穿过时钟布线的信号布线中的空白区域中，虚拟电源布线布置在时钟布线的上方或下方，以跨越时钟布线的方式。形成虚拟电源布线，以使例如时钟分配电路或时钟驱动器之间的长度相等的布线的电容相等。

7. 发明授权

US5055710A Integrated logic circuit having plural input cells and flip-flop and output cells arranged in a cell block 失效
标题翻译：具有多个输入单元和布置在单元块中的触发器和输出单元的集成逻辑电路
公开(公告)号：US5055710A
公开(公告)日：1991-10-08
申请号：US520875
申请日：1990-05-09
申请人： Kazuo Tanaka , Masato Hamamoto , Toshio Yamada , Tohru Kobayashi , Hiromasa Katoh
发明人： Kazuo Tanaka , Masato Hamamoto , Toshio Yamada , Tohru Kobayashi , Hiromasa Katoh
IPC分类号： G01R31/3185 , H01L27/02
CPC分类号： H01L27/0207 , G01R31/318538 , G01R31/318572
摘要： Flip-flops are disposed corresponding to input circuits or output circuits of an integrated logic circuit so as to be cascaded to configure a shift register for a test and to enable a parallel transfer of data between each flip-flop and a corresponding input or output circuit. As a result, without connecting the probe to all terminals of the LSI, test signals can be supplied from some terminals via all input circuits to an internal circuit so as to conduct a diagnosis.
摘要翻译：触发器对应于集成逻辑电路的输入电路或输出电路进行布置，以便级联以配置用于测试的移位寄存器，并且能够在每个触发器和相应的输入或输出电路之间并行传输数据。结果，在不将探头连接到LSI的所有端子的情况下，可以通过所有输入电路从一些端子向内部电路提供测试信号，以进行诊断。

8. 发明授权

US4999520A High speed TTL buffer circuit which is resistive to the influence of alpha-rays 失效
标题翻译：高速TTL缓冲电路，可抵抗α射线的影响
公开(公告)号：US4999520A
公开(公告)日：1991-03-12
申请号：US330461
申请日：1989-03-30
申请人： Mitsuo Usami , Noboru Shiozawa , Toshio Yamada , Hiromasa Katoh , Kazuyoshi Satoh , Tohru Kobayashi , Tatsuya Kimura , Masato Hamamoto , Atsushi Shimizu , Kaoru Koyu
发明人： Mitsuo Usami , Noboru Shiozawa , Toshio Yamada , Hiromasa Katoh , Kazuyoshi Satoh , Tohru Kobayashi , Tatsuya Kimura , Masato Hamamoto , Atsushi Shimizu , Kaoru Koyu
IPC分类号： H03K3/2885 , H03K17/0412 , H03K17/66 , H03K19/013 , H03K19/086
CPC分类号： H03K3/2885 , H03K17/04126 , H03K17/666 , H03K19/0136 , H03K19/086
摘要： A semiconductor integrated circuit wherein an input circuit is formed by a phase split circuit consisting of a bipolar transistor which outputs an inverted output from the collector and non-inverted output from the emitter, the emitter follower output circuit is driven by an inverted output of the phase split circuit, meanwhile, an emitter load of the emitter follower output circuit is formed by a transistor, and the emitter load transistor is temporarily driven conductively by a charging current of the capacitance to be charged by the rising edge of the non-inverted output of the phase split circuit.
摘要翻译：一种半导体集成电路，其中输入电路由相位分离电路形成，该相位分离电路由输出来自集电极的反相输出和从发射极输出的非反相输出的双极晶体管构成，射极跟随器输出电路由反相输出驱动同相分流电路，射极跟随器输出电路的发射极负载由晶体管形成，发射极负载晶体管通过非反相输出的上升沿的待充电电容的充电电流暂时驱动导通的相分离电路。

9. 发明授权

US06636075B2 Semiconductor integrated circuit and its fabrication method 失效
公开(公告)号：US06636075B2
公开(公告)日：2003-10-21
申请号：US10060390
申请日：2002-02-01
申请人： Michiaki Nakayama , Masato Hamamoto , Kazutaka Mori , Satoru Isomura
发明人： Michiaki Nakayama , Masato Hamamoto , Kazutaka Mori , Satoru Isomura
IPC分类号： H01P308
CPC分类号： H01L27/1104 , H01L27/0921 , H01L27/0928
摘要： An integrated circuit having a CMOS circuit constituted by electrically connecting an n-type well 2, in which p-channel transistor Tp of the CMOS circuit is set, with a supply line Vdd through switching transistor Tps, and electrically connecting a p-type well 3, in which n-channel transistor Tn of the CMOS circuit is set, with supply line Vss through switching transistor Tns. Thermal runaway due to leakage current can be controlled by turning off switching transistors Tps and Tns and supplying potentials suitable for a test to the n-type well 2 and the p-type well 3 from an external unit when the integrated circuit is being tested. Fluctuations of the latch-up phenomenon and operation speed can be prevented by turning on switching transistors Tps and Tns and setting the n-type well 2 and the p-type well 3 to the voltages Vdd and Vss, respectively.

10. 发明授权

US4940905A ECL flip-flop with improved x-ray resistant properties 失效
标题翻译： ECL触发器具有改进的x射线抗性
公开(公告)号：US4940905A
公开(公告)日：1990-07-10
申请号：US426047
申请日：1989-10-24
申请人： Tohru Kobayashi , Masato Hamamoto , Toshio Yamada
发明人： Tohru Kobayashi , Masato Hamamoto , Toshio Yamada
IPC分类号： H03K3/037 , H03K3/2885
CPC分类号： H03K3/2885 , H03K3/0375
摘要： An ECL flip-flop circuit has a data holding differential transistor pair and a feedback circuit provided between the collectors and bases of this differential transistor pair. The feedback circuit includes a resistor connected between the bases of the data holding differential transistor pair, a pair of switching means for selectively terminating one end or the other of the resistor, and a pair of feedback transistors each adapted to receive at its base the collector potential of one transistor or the other of the differential transistor pair and to form an emitter follower circuit with the resistor selectively included therein. Thus, it is possible to prevent a malfunction of the ECl flip-flop circuit due to .alpha.-particles or the like.
摘要翻译： ECL触发器电路具有数据保持差分晶体管对和设置在该差分晶体管对的集电极和基极之间的反馈电路。反馈电路包括连接在数据保持差分晶体管对的基极之间的电阻器，用于选择性地端接电阻器的一端或另一端的一对开关装置，以及一对反馈晶体管，每个反馈晶体管适于在其基极处接收集电极一个晶体管或另一个差分晶体管对的电位并且形成具有选择性地包括在其中的电阻的射极跟随器电路。因此，可以防止由于α-粒子等导致的ECl触发器电路的故障。

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