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1. 发明授权

US06670201B2 Manufacturing method of semiconductor device 失效
公开(公告)号：US06670201B2
公开(公告)日：2003-12-30
申请号：US09939670
申请日：2001-08-28
申请人： Masaki Kouno , Masato Hamamoto , Atsushi Wakahara , Hideyuki Takahashi , Keiichi Higeta , Mitsugu Kusunoki , Kazutaka Mori
发明人： Masaki Kouno , Masato Hamamoto , Atsushi Wakahara , Hideyuki Takahashi , Keiichi Higeta , Mitsugu Kusunoki , Kazutaka Mori
IPC分类号： G01R3126
CPC分类号： G01R31/3004
摘要： A manufacturing method of a semiconductor device capable of obtaining highly reliable semiconductor devices with the realization of high integration and high speed intended is provided. During processes after a desired circuit including a CMOS static type circuit is formed on a semiconductor substrate until product shipment, a first operation of feeding a predetermined input signal to the circuit and retrieving a first output signal corresponding to it and a second operation of giving an operating condition of increasing an ON resistance value of MOSFETs constituting the CMOS static type circuit and retrieving a second output signal corresponding to the condition are conducted, and a testing step of determining a failure by the first output signal varying from the second output signal.

2. 发明申请

US20060245266A1 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US20060245266A1
公开(公告)日：2006-11-02
申请号：US11409963
申请日：2006-04-25
申请人： Ryusuke Sahara , Mitsugu Kusunoki , Kazutaka Mori , Hiroshige Kogayu
发明人： Ryusuke Sahara , Mitsugu Kusunoki , Kazutaka Mori , Hiroshige Kogayu
IPC分类号： G11C7/10
CPC分类号： H03M1/1061 , H03M1/687 , H03M1/785 , H03M1/808
摘要： A DAC having a memory mat including a plurality of first memory cells, and a plurality of output lines connected to the plurality of first memory cells. Each of the plurality of memory cells has a first memory portion including bipolar transistors and storing information in non-volatility based on whether a junction of the bipolar transistors is destroyed or not, and a second memory portion connected to the first memory portion and for outputting information to corresponding one of the plurality of output lines. The DAC has a first mode in which information is transferred from the first memory portions to the second memory portions when the information is written into the second memory portions, and a second mode in which the second memory portions are specified externally and information is written into the second memory portions. Thus, the performance of a D/A converter can be improved.
摘要翻译：具有包括多个第一存储单元的存储器垫的DAC和连接到多个第一存储单元的多个输出线。多个存储单元中的每一个具有包括双极晶体管的第一存储器部分，并且基于双极晶体管的结是否被破坏来存储非易失性的信息，以及连接到第一存储器部分并用于输出的第二存储器部分信息到多个输出行中的相应一个。 DAC具有第一模式，其中当信息被写入第二存储器部分时，信息从第一存储器部分传送到第二存储器部分，以及第二模式，其中第二存储器部分被外部指定并且信息被写入第二存储器部分。因此，可以提高D / A转换器的性能。

3. 发明申请

US20060244103A1 Semiconductor apparatus 失效
公开(公告)号：US20060244103A1
公开(公告)日：2006-11-02
申请号：US11411096
申请日：2006-04-26
申请人： Koji Ishikawa , Kazutaka Mori , Hiroshige Kogayu , Tamotsu Miyake , Mitsugu Kusunoki
发明人： Koji Ishikawa , Kazutaka Mori , Hiroshige Kogayu , Tamotsu Miyake , Mitsugu Kusunoki
IPC分类号： H01L27/082
CPC分类号： H01L23/5252 , H01L27/0823 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor apparatus includes a first transistor having a first emitter electrode, a first base electrode, and a first collector electrode in a region over a first region. Base lead-out polysilicon connecting the first base electrode and a first base region passes over a second region provided out of the first region and a resistor element is added. A writing voltage is reduced in an antifuse using two bipolar transistors.

4. 发明申请

US20080055140A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20080055140A1
公开(公告)日：2008-03-06
申请号：US11877561
申请日：2007-10-23
申请人： Ryusuke SAHARA , Mitsugu Kusunoki , Kazutaka Mori , Hiroshige Kogayu
发明人： Ryusuke SAHARA , Mitsugu Kusunoki , Kazutaka Mori , Hiroshige Kogayu
IPC分类号： H03M1/66
CPC分类号： H03M1/1061 , H03M1/687 , H03M1/785 , H03M1/808
摘要： A DAC having a memory mat including a plurality of first memory cells, and a plurality of output lines connected to the plurality of first memory cells. Each of the plurality of memory cells has a first memory portion including bipolar transistors and storing information in non-volatility based on whether a junction of the bipolar transistors is destroyed or not, and a second memory portion connected to the first memory portion and for outputting information to corresponding one of the plurality of output lines. The DAC has a first mode in which information is transferred from the first memory portions to the second memory portions when the information is written into the second memory portions, and a second mode in which the second memory portions are specified externally and information is written into the second memory portions. Thus, the performance of a D/A converter can be improved.
摘要翻译：具有包括多个第一存储单元的存储器垫的DAC和连接到多个第一存储单元的多个输出线。多个存储单元中的每一个具有包括双极晶体管的第一存储器部分，并且基于双极晶体管的结是否被破坏来存储非易失性的信息，以及连接到第一存储器部分并用于输出的第二存储器部分信息到多个输出行中的相应一个。 DAC具有第一模式，其中当信息被写入第二存储器部分时，信息从第一存储器部分传送到第二存储器部分，以及第二模式，其中第二存储器部分被外部指定并且信息被写入第二存储器部分。因此，可以提高D / A转换器的性能。

5. 发明授权

US07310266B2 Semiconductor device having memory cells implemented with bipolar-transistor-antifuses operating in a first and second mode 有权
标题翻译：具有以第一和第二模式工作的双极晶体管 - 反熔丝实现的存储单元的半导体器件
公开(公告)号：US07310266B2
公开(公告)日：2007-12-18
申请号：US11409963
申请日：2006-04-25
申请人： Ryusuke Sahara , Mitsugu Kusunoki , Kazutaka Mori , Hiroshige Kogayu
发明人： Ryusuke Sahara , Mitsugu Kusunoki , Kazutaka Mori , Hiroshige Kogayu
IPC分类号： G11C11/40 , H03M1/66
CPC分类号： H03M1/1061 , H03M1/687 , H03M1/785 , H03M1/808
摘要： A DAC having a memory mat including a plurality of first memory cells, and a plurality of output lines connected to the plurality of first memory cells. Each of the plurality of memory cells has a first memory portion including bipolar transistors and storing information in non-volatility based on whether a junction of the bipolar transistors is destroyed or not, and a second memory portion connected to the first memory portion and for outputting information to corresponding one of the plurality of output lines. The DAC has a first mode in which information is transferred from the first memory portions to the second memory portions when the information is written into the second memory portions, and a second mode in which the second memory portions are specified externally and information is written into the second memory portions.
摘要翻译：具有包括多个第一存储单元的存储器垫的DAC和连接到多个第一存储单元的多个输出线。多个存储单元中的每一个具有包括双极晶体管的第一存储器部分，并且基于双极晶体管的结点是否被破坏来存储非易失性的信息，以及连接到第一存储器部分并用于输出的第二存储器部分信息到多个输出行中的相应一个。 DAC具有第一模式，其中当信息被写入第二存储器部分时，信息从第一存储器部分传送到第二存储器部分，以及第二模式，其中第二存储器部分被外部指定并且信息被写入第二存储器部分。

6. 发明授权

US07629669B2 Semiconductor apparatus 失效
标题翻译：半导体装置
公开(公告)号：US07629669B2
公开(公告)日：2009-12-08
申请号：US11411096
申请日：2006-04-26
申请人： Koji Ishikawa , Kazutaka Mori , Hiroshige Kogayu , Tamotsu Miyake , Mitsugu Kusunoki
发明人： Koji Ishikawa , Kazutaka Mori , Hiroshige Kogayu , Tamotsu Miyake , Mitsugu Kusunoki
IPC分类号： H01L27/102
CPC分类号： H01L23/5252 , H01L27/0823 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor apparatus includes a first transistor having a first emitter electrode, a first base electrode, and a first collector electrode in a region over a first region. Base lead-out polysilicon connecting the first base electrode and a first base region passes over a second region provided out of the first region and a resistor element is added. A writing voltage is reduced in an antifuse using two bipolar transistors.
摘要翻译：半导体装置包括在第一区域的区域中具有第一发射极，第一基极和第一集电极的第一晶体管。连接第一基极和第一基极区域的基极引出多晶硅通过在第一区域外提供的第二区域，并且添加电阻元件。使用两个双极晶体管在反熔丝中减小写入电压。

7. 发明授权

US07522083B2 Semiconductor device having D/A conversion portion 有权
标题翻译：具有D / A转换部分的半导体器件
公开(公告)号：US07522083B2
公开(公告)日：2009-04-21
申请号：US11877561
申请日：2007-10-23
申请人： Ryusuke Sahara , Mitsugu Kusunoki , Kazutaka Mori , Hiroshige Kogayu
发明人： Ryusuke Sahara , Mitsugu Kusunoki , Kazutaka Mori , Hiroshige Kogayu
IPC分类号： H03M1/78
CPC分类号： H03M1/1061 , H03M1/687 , H03M1/785 , H03M1/808
摘要： A DAC having a memory mat including a plurality of first memory cells, and a plurality of output lines connected to the plurality of first memory cells. Each of the plurality of memory cells has a first memory portion including bipolar transistors and storing information in non-volatility based on whether a junction of the bipolar transistors is destroyed or not, and a second memory portion connected to the first memory portion and for outputting information to corresponding one of the plurality of output lines. The DAC has a first mode in which information is transferred from the first memory portions to the second memory portions when the information is written into the second memory portions, and a second mode in which the second memory portions are specified externally and information is written into the second memory portions. Thus, the performance of a D/A converter can be improved.
摘要翻译：具有包括多个第一存储单元的存储器垫的DAC和连接到多个第一存储单元的多个输出线。多个存储单元中的每一个具有包括双极晶体管的第一存储器部分，并且基于双极晶体管的结是否被破坏来存储非易失性的信息，以及连接到第一存储器部分并用于输出的第二存储器部分信息到多个输出行中的相应一个。 DAC具有第一模式，其中当信息被写入第二存储器部分时，信息从第一存储器部分传送到第二存储器部分，以及第二模式，其中第二存储器部分被外部指定并且信息被写入第二存储器部分。因此，可以提高D / A转换器的性能。

8. 发明授权

US07078928B2 Semiconductor integrated circuit device 失效
标题翻译：半导体集成电路器件
公开(公告)号：US07078928B2
公开(公告)日：2006-07-18
申请号：US10736673
申请日：2003-12-17
申请人： Ryusuke Sahara , Kozaburo Kurita , Yuuji Suzuki , Mitsugu Kusunoki , Hideki Sakakibara
发明人： Ryusuke Sahara , Kozaburo Kurita , Yuuji Suzuki , Mitsugu Kusunoki , Hideki Sakakibara
IPC分类号： H03K19/00 , G01R31/28 , H03H11/26
CPC分类号： G01R31/318577
摘要： The present invention provides a semiconductor integrated circuit device equipped with at least one pulse generator which generates a pulse of a pulse with shorter than a rising time up to the full amplitude of a transfer signal.A first signal and a second signal supplied from outside through a first signal path and a second signal path are respectively transferred to the pulse generator. When a rising time up to the full amplitude at any one of buffers in the first signal path and the second signal path is longer than a pulse width of a pulse to be formed by the pulse generator, the difference in phase between the first signal and the second signal is caused to correspond to a pulse width of a first pulse.
摘要翻译：本发明提供一种配备有至少一个脉冲发生器的半导体集成电路器件，该脉冲发生器产生的脉冲脉冲短于传输信号的全幅度的上升时间。通过第一信号路径和第二信号路径从外部提供的第一信号和第二信号分别传送到脉冲发生器。当在第一信号路径和第二信号路径中的任何一个缓冲器上的上升时间达到全幅度时，脉冲发生器将形成的脉冲的脉冲宽度大于第一信号与第二信号路径之间的相位差使第二信号对应于第一脉冲的脉冲宽度。

9. 发明授权

US07903013B2 Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US07903013B2
公开(公告)日：2011-03-08
申请号：US12507660
申请日：2009-07-22
申请人： Kenichiro Yamaguchi , Atsushi Okumura , Mitsugu Kusunoki , Tomoo Murata
发明人： Kenichiro Yamaguchi , Atsushi Okumura , Mitsugu Kusunoki , Tomoo Murata
IPC分类号： H03M1/66
CPC分类号： H03M1/0643 , H01L27/0203 , H03M1/687 , H03M1/745 , H03M1/785 , Y10T307/696
摘要： Operating speed as well as output accuracy of a D-A converter is enhanced. With a semiconductor device including unit current sources, and unit current source switches, plural current source elements constituting each of the unit current sources are disposed so as to be evenly dispersed, thereby reducing errors of the current source element, dependent on distance while the unit current source switches are concentratedly disposed in a small region, thereby mitigating delay in operation, attributable to parasitic capacitance. In addition, with the semiconductor device including R2R resistance ladders, the R2R resistance ladder is provided on the positive and the negative of each of the unit current source switches, and the respective R2R resistance ladders are shorted with each other at respective nodes on a unit current source switch-by-unit current source switch basis, are rendered identical in length, thereby cancelling out a nonlinearity error attributable to wiring parasitic resistance.
摘要翻译：提高了D-A转换器的工作速度和输出精度。利用包括单位电流源和单位电流源开关的半导体器件，构成每个单位电流源的多个电流源元件被布置成均匀分散，从而根据距离减小电流源元件的误差，而单元电流源开关集中地设置在较小的区域中，从而减轻了由寄生电容引起的工作延迟。另外，对于包含R2R电阻梯的半导体装置，在每个单位电流源开关的正极和负极上设置R2R电阻梯，并且相应的R2R电阻梯在单元的相应节点处相互短路电流源逐个电流源开关基础的长度相同，从而消除归因于布线寄生电阻的非线性误差。

10. 发明授权

US06806743B2 Semiconductor integrated circuit device 失效
标题翻译：半导体集成电路器件
公开(公告)号：US06806743B2
公开(公告)日：2004-10-19
申请号：US10360868
申请日：2003-02-10
申请人： Kayoko Saito , Mitsugu Kusunoki
发明人： Kayoko Saito , Mitsugu Kusunoki
IPC分类号： H03F345
CPC分类号： H03F3/45219 , H03F3/72 , H03F2203/45396 , H03F2203/45506
摘要： The present invention provides a semiconductor integrated circuit device equipped with an input circuit capable of stably performing a high-speed operation up to a low voltage. A rail to rail circuit constitutes a differential input circuit, and a circuit similar to such a differential input circuit is used to constitute a bias circuit. A pair of output terminals of a differential circuit constituting such a bias circuit is commonly connected to form a bias voltage corresponding to a middle point. The bias voltage is supplied to the gates of current source MOSFET and the gates of cascode-connected MOSFETs in the differential input circuit, and the gates of the corresponding current source MOSFETs and cascode-connected MOSFETs in the bias circuit corresponding to itself.
摘要翻译：本发明提供一种配备有能够稳定地进行低电压的高速运转的输入电路的半导体集成电路装置。轨到轨电路构成差分输入电路，并且使用类似于这种差分输入电路的电路来构成偏置电路。构成这种偏置电路的差分电路的一对输出端子通常连接以形成对应于中点的偏置电压。偏置电压被提供给电流源MOSFET的栅极和差分输入电路中的共源共栅MOSFET的栅极，偏置电路中对应的电流源MOSFET和共源共栅MOSFET的栅极对应于其自身。

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