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1. 发明授权

US5055710A Integrated logic circuit having plural input cells and flip-flop and output cells arranged in a cell block 失效
标题翻译：具有多个输入单元和布置在单元块中的触发器和输出单元的集成逻辑电路
公开(公告)号：US5055710A
公开(公告)日：1991-10-08
申请号：US520875
申请日：1990-05-09
申请人： Kazuo Tanaka , Masato Hamamoto , Toshio Yamada , Tohru Kobayashi , Hiromasa Katoh
发明人： Kazuo Tanaka , Masato Hamamoto , Toshio Yamada , Tohru Kobayashi , Hiromasa Katoh
IPC分类号： G01R31/3185 , H01L27/02
CPC分类号： H01L27/0207 , G01R31/318538 , G01R31/318572
摘要： Flip-flops are disposed corresponding to input circuits or output circuits of an integrated logic circuit so as to be cascaded to configure a shift register for a test and to enable a parallel transfer of data between each flip-flop and a corresponding input or output circuit. As a result, without connecting the probe to all terminals of the LSI, test signals can be supplied from some terminals via all input circuits to an internal circuit so as to conduct a diagnosis.
摘要翻译：触发器对应于集成逻辑电路的输入电路或输出电路进行布置，以便级联以配置用于测试的移位寄存器，并且能够在每个触发器和相应的输入或输出电路之间并行传输数据。结果，在不将探头连接到LSI的所有端子的情况下，可以通过所有输入电路从一些端子向内部电路提供测试信号，以进行诊断。

2. 发明授权

US4999520A High speed TTL buffer circuit which is resistive to the influence of alpha-rays 失效
标题翻译：高速TTL缓冲电路，可抵抗α射线的影响
公开(公告)号：US4999520A
公开(公告)日：1991-03-12
申请号：US330461
申请日：1989-03-30
申请人： Mitsuo Usami , Noboru Shiozawa , Toshio Yamada , Hiromasa Katoh , Kazuyoshi Satoh , Tohru Kobayashi , Tatsuya Kimura , Masato Hamamoto , Atsushi Shimizu , Kaoru Koyu
发明人： Mitsuo Usami , Noboru Shiozawa , Toshio Yamada , Hiromasa Katoh , Kazuyoshi Satoh , Tohru Kobayashi , Tatsuya Kimura , Masato Hamamoto , Atsushi Shimizu , Kaoru Koyu
IPC分类号： H03K3/2885 , H03K17/0412 , H03K17/66 , H03K19/013 , H03K19/086
CPC分类号： H03K3/2885 , H03K17/04126 , H03K17/666 , H03K19/0136 , H03K19/086
摘要： A semiconductor integrated circuit wherein an input circuit is formed by a phase split circuit consisting of a bipolar transistor which outputs an inverted output from the collector and non-inverted output from the emitter, the emitter follower output circuit is driven by an inverted output of the phase split circuit, meanwhile, an emitter load of the emitter follower output circuit is formed by a transistor, and the emitter load transistor is temporarily driven conductively by a charging current of the capacitance to be charged by the rising edge of the non-inverted output of the phase split circuit.
摘要翻译：一种半导体集成电路，其中输入电路由相位分离电路形成，该相位分离电路由输出来自集电极的反相输出和从发射极输出的非反相输出的双极晶体管构成，射极跟随器输出电路由反相输出驱动同相分流电路，射极跟随器输出电路的发射极负载由晶体管形成，发射极负载晶体管通过非反相输出的上升沿的待充电电容的充电电流暂时驱动导通的相分离电路。

3. 发明授权

US4720464A Electrolytes for Karl Fischer coulometric titration 失效
标题翻译：用于卡尔费休库仑滴定的电解质
公开(公告)号：US4720464A
公开(公告)日：1988-01-19
申请号：US674589
申请日：1984-11-26
申请人： Sinichi Kuwata , Hiromasa Katoh , Mitsumasa Ono
发明人： Sinichi Kuwata , Hiromasa Katoh , Mitsumasa Ono
IPC分类号： G01N31/16 , G01N33/18
CPC分类号： G01N31/168
摘要： An electrolyte for Karl Fischer coulometric titration, which contains(a) iodine or an iodine compound,(b) sulfur dioxide,(c) a halogenated hydrocarbon or an aromatic hydrocarbon,and(d)(i) an amine of the following general formula (I), an amine of the following general formula (II) and a monohydric alcohol, or(ii) an amine of the following general formula (I) and/or an amine of the following general formula (II) and a polyhydric alcohol or an ether compound thereof of the following general formula (III):General formula (I): ##STR1## wherein R.sup.1 and R.sup.2 each represent a hydrogen atom, an alkyl group, a pyridyl group or a pyrrolidinyl group;General formula (II): ##STR2## wherein R.sup.3 -R.sup.10 each represent a hydrogen atom or an alkyl group, and m is an integer of 1-5;General formula (III):R.sup.11 O--(CH.sub.2).sub.n --OR.sup.12 (III)wherein R.sup.11 and R.sup.12 each represent a hydrogen atom or an alkyl group, and n is 2 or 3. The electrolytes of the invention are free from pungent pyridine odors and can accurately measure the water in various samples, especially those containing ketones, carboxylic acids etc.
摘要翻译：一种用于卡尔费休库仑滴定的电解质，其包含（a）碘或碘化合物，（b）二氧化硫，（c）卤代烃或芳族烃，和（d）（i）下列通式（I），下述通式（II）的胺和一元醇，或（ii）下述通式（I）的胺和/或下述通式（II）的胺和多元醇或其醚化合物：通式（I）：其中R 1和R 2各自表示氢原子，烷基，吡啶基或吡咯烷基;（I）其中R 1和R 2各自表示氢原子，通式（II）：其中R 3 -R 10各自表示氢原子或烷基，m为1-5的整数; 通式（III）：R 11 O-（CH 2）n -OR 12（III）其中R 11和R 12各自表示氢原子或烷基，n为2或3.本发明的电解质不含刺激性吡啶气味，可以精确测量各种样品中的水分，特别是含有酮，羧酸等的水分。

4. 发明授权

US4802957A Method for measuring the water content of a solid sample using Karl Fischer's coulometric titration 失效
标题翻译：使用卡尔·费休的库仑滴定法测量固体样品的含水量的方法
公开(公告)号：US4802957A
公开(公告)日：1989-02-07
申请号：US850527
申请日：1986-04-10
申请人： Sinichi Kuwata , Hiromasa Katoh , Mitsumasa Ono
发明人： Sinichi Kuwata , Hiromasa Katoh , Mitsumasa Ono
IPC分类号： G01N27/44 , G01N31/00 , G01N31/16 , G01N31/22 , G01N33/18
CPC分类号： G01N31/168
摘要： An electrolytic solution for Karl Fischer's coulometric titation and a method for measuring the water content of a sample using the same are disclosed. The electrolytic solution contains iodine or an iodide, sulfur dioxide, an amine and a solvent, wherein the amine is a pyridine derivative, imidazole or an imidazole derivative and the solvent is a mixture of (a) a polyhydric alcohol or an ether compound thereof, (b) methanol and (c) a halogenated hydrocarbon or an aromatic hydrocarbon. The measurement method achieves a high precision with reduced measurement time and is suitable for making water content measurements using a water content vaporization method.
摘要翻译：公开了一种卡尔·费休库仑电解液的电解液和使用该溶液测量样品的含水量的方法。电解液含有碘或碘，二氧化硫，胺和溶剂，其中胺是吡啶衍生物，咪唑或咪唑衍生物，溶剂是（a）多元醇或其醚化合物的混合物，（b）甲醇和（c）卤代烃或芳族烃。测量方法在测量时间缩短的同时实现了高精度，适用于使用含水汽化法进行含水量测量。

5. 发明授权

US5298802A Semiconductor integrated circuit device with a plurality of logic circuits having active pull-down functions 失效
标题翻译：具有多个具有主动下拉功能的逻辑电路的半导体集成电路器件
公开(公告)号：US5298802A
公开(公告)日：1994-03-29
申请号：US56798
申请日：1993-05-03
申请人： Mitsuo Usami , Noboru Shiozawa , Toshio Yamada , Hiromasa Katoh , Kazuyoshi Satoh , Tohru Kobayashi , Tatsuya Kimura , Masato Hamamoto , Atsushi Shimizu , Kaoru Koyu
发明人： Mitsuo Usami , Noboru Shiozawa , Toshio Yamada , Hiromasa Katoh , Kazuyoshi Satoh , Tohru Kobayashi , Tatsuya Kimura , Masato Hamamoto , Atsushi Shimizu , Kaoru Koyu
IPC分类号： H03K3/2885 , H03K17/0412 , H03K17/66 , H03K19/013 , H03K19/086
CPC分类号： H03K19/086 , H03K17/04126 , H03K17/666 , H03K19/0136 , H03K3/2885
摘要： In accordance with one aspect of the invention, a semiconductor integrated circuit is provided wherein an input circuit is formed by a phase split circuit having a bipolar transistor which outputs an inverted output from the collector and a non-inverted output from the emitter. The emitter follower output circuit is driven by an inverted output of the phase split circuit. Meanwhile, an emitter load of the emitter follower output circuit is formed by a transistor, and the emitter load transistor is temporarily driven conductively by a charging current of the capacitance to be charged by the rising edge of the non-inverted output of the phase split circuit. As a second aspect of the invention, a logic circuit is formed of a logic portion and an output portion. The output portion includes an emitter follower output transistor receiving an output signal generated by the logic portion and an active pull-down transistor receiving at its base a signal supplied thereto through a capacitance element. The signal received by the active pull-down transistor has a phase reverse to that of the input signal supplied to the base of said output transistor. Between the base and emitter of the active pull-down transistor, there is disposed a bias circuit formed of a transistor receiving at its base a predetermined bias voltage and an emitter resistor. Further, between a junction point of the emitter follower output transistor and the active pull-down transistor and the emitter of the transistor as a constituent of the bias circuit, there is disposed a capacitance element for feeding back the output signal.
摘要翻译：根据本发明的一个方面，提供一种半导体集成电路，其中输入电路由具有从集电极输出反相输出的双极晶体管和来自发射极的非反相输出的相位分离电路形成。射极跟随器输出电路由相位分离电路的反相输出驱动。同时，射极跟随器输出电路的发射极负载由晶体管形成，并且发射极负载晶体管由相分离的非反相输出的上升沿的待充电电容的充电电流导通地临时驱动电路。作为本发明的第二方面，逻辑电路由逻辑部分和输出部分组成。输出部分包括接收由逻辑部分产生的输出信号的射极跟随器输出晶体管和有源下拉晶体管，在其底部接收通过电容元件提供给它的信号。由有源下拉晶体管接收的信号与提供给所述输出晶体管的基极的输入信号的相位相反。在有源下拉晶体管的基极和发射极之间设置偏置电路，该偏置电路由其基极接收预定偏置电压的晶体管和发射极电阻构成。此外，在射极跟随器输出晶体管的连接点和有源下拉晶体管和作为偏置电路的组成部分的晶体管的发射极之间，设置有用于反馈输出信号的电容元件。

6. 发明授权

US5283480A Semiconductor integrated circuit device with a plurality of logic circuits having active pull-down functions 失效
公开(公告)号：US5283480A
公开(公告)日：1994-02-01
申请号：US557109
申请日：1990-07-25
申请人： Mitsuo Usami , Noboru Shiozawa , Toshio Yamada , Hiromasa Katoh , Kazuyoshi Satoh , Tohru Kobayashi , Tatsuya Kimura , Masato Hamamoto , Atsushi Shimizu , Kaoru Koyu
发明人： Mitsuo Usami , Noboru Shiozawa , Toshio Yamada , Hiromasa Katoh , Kazuyoshi Satoh , Tohru Kobayashi , Tatsuya Kimura , Masato Hamamoto , Atsushi Shimizu , Kaoru Koyu
IPC分类号： H03K3/2885 , H03K17/0412 , H03K17/66 , H03K19/013 , H03K19/086
CPC分类号： H03K19/086 , H03K17/04126 , H03K17/666 , H03K19/0136 , H03K3/2885
摘要： In accordance with one aspect of the invention, a semiconductor integrated circuit is provided wherein an input circuit is formed by a phase split circuit having a bipolar transistor which outputs an inverted output from the collector and a non-inverted output from the emitter. The emitter follower output circuit is driven by an inverted output of the phase split circuit. Meanwhile, an emitter load of the emitter follower output circuit is formed by a transistor, and the emitter load transistor is temporarily driven conductively by a charging current of the capacitance to be charged by the rising edge of the non-inverted output of the phase split circuit. As a second aspect of the invention, a logic circuit is formed of a logic portion and an output portion. The output portion includes an emitter follower output transistor receiving an output signal generated by the logic portion and an active pull-down transistor receiving at its base a signal supplied thereto through a capacitance element. The signal received by the active pull-down transistor has a phase reverse to that of the input signal supplied to the base of said output transistor. Between the base and emitter of the active pull-down transistor, there is disposed a bias circuit formed of a transistor receiving at its base a predetermined bias voltage and an emitter resistor. Further, between a junction point of the emitter follower output transistor and the active pull-down transistor and the emitter of the transistor as a constituent of the bias circuit, there is disposed a capacitance element for feeding back the output signal.

7. 发明授权

US5059819A Integrated logic circuit 失效
标题翻译：集成逻辑电路
公开(公告)号：US5059819A
公开(公告)日：1991-10-22
申请号：US133915
申请日：1987-12-16
申请人： Kazuo Tanaka , Masato Hamamoto , Toshio Yamada , Tohru Kobayashi , Hiromasa Katoh
发明人： Kazuo Tanaka , Masato Hamamoto , Toshio Yamada , Tohru Kobayashi , Hiromasa Katoh
IPC分类号： G01R31/3185 , H01L27/02
CPC分类号： H01L27/0207 , G01R31/318538 , G01R31/318572
摘要： Flip-flops are disposed corresponding to input circuits or output circuits of an integrated logic circuit so as to be cascaded to configure a shift register for a test and to enable a parallel transfer of data between each flip-flop and a corresponding input or output circuit. As a result, without connecting the probe to all terminals of the LSI, test signals can be supplied from some terminals via all input circuits to an internal circuit so as to conduct a diagnosis.
摘要翻译：触发器对应于集成逻辑电路的输入电路或输出电路进行布置，以便级联以配置用于测试的移位寄存器，并且能够在每个触发器和相应的输入或输出电路之间并行传输数据。结果，在不将探头连接到LSI的所有端子的情况下，可以通过所有输入电路从一些端子向内部电路提供测试信号，以进行诊断。

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