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1. 发明授权

US07787312B2 Semiconductor device and controlling method for the same 有权
标题翻译：半导体装置及其控制方法
公开(公告)号：US07787312B2
公开(公告)日：2010-08-31
申请号：US12130583
申请日：2008-05-30
申请人： Junya Kawamata , Tsutomu Nakai , Hirokazu Nagashima , Kenichi Takehana , Kenji Arai , Kazuki Yamauchi , Kazuhide Kurosaki
发明人： Junya Kawamata , Tsutomu Nakai , Hirokazu Nagashima , Kenichi Takehana , Kenji Arai , Kazuki Yamauchi , Kazuhide Kurosaki
IPC分类号： G11C7/10
CPC分类号： G11C29/74 , G11C16/0416 , H01L27/0207 , H01L27/105 , H01L27/115 , H01L27/11519 , H01L27/11526 , H01L27/11531
摘要： A semiconductor device has a plurality of bit lines BL provided in a memory cell area 101, a plurality of word lines WL provided crossing the plurality of bit lines BL, a plurality of diffusion source lines VSL provided along the plurality of word lines WL, a plurality of non-volatile active cells AC storing data, the plurality of non-volatile active cells AC being provided at cross sections of the plurality of bit lines BL and the plurality of word lines WL and being connected to the plurality of bit lines BL, the plurality of word lines WL, and the plurality of diffusion source lines VSL, and a controller simultaneously writes or reads data to and from at least two active cells AC among the plurality of active cells AC, in which the number of the plurality of active cells AC is less than that of the cross sections.
摘要翻译：半导体器件具有设置在存储单元区域101中的多个位线BL，与多个位线BL交叉设置的多个字线WL，沿多个字线WL设置的多个扩散源极线VSL，多个非易失性活动单元AC存储数据，多个非易失性活动单元AC设置在多个位线BL和多个字线WL的横截面处并连接到多个位线BL，多个字线WL和多个扩散源线VSL，以及控制器同时向多个有源单元AC中的至少两个有源单元AC写入或读取数据，其中多个活动单元AC的数量细胞AC小于截面积。

2. 发明申请

US20090010076A1 SEMICONDUCTOR DEVICE AND CONTROLLING METHOD FOR THE SAME 有权
标题翻译：半导体器件及其控制方法
公开(公告)号：US20090010076A1
公开(公告)日：2009-01-08
申请号：US12130583
申请日：2008-05-30
申请人： Junya Kawamata , Tsutomu Nakai , Hirokazu Nagashima , Kenichi Takehana , Kenji Arai , Kazuki Yamauchi , Kazuhide Kurosaki
发明人： Junya Kawamata , Tsutomu Nakai , Hirokazu Nagashima , Kenichi Takehana , Kenji Arai , Kazuki Yamauchi , Kazuhide Kurosaki
IPC分类号： G11C7/00
CPC分类号： G11C29/74 , G11C16/0416 , H01L27/0207 , H01L27/105 , H01L27/115 , H01L27/11519 , H01L27/11526 , H01L27/11531
摘要： A semiconductor device has a plurality of bit lines BL provided in a memory cell area 101, a plurality of word lines WL provided crossing the plurality of bit lines BL, a plurality of diffusion source lines VSL provided along the plurality of word lines WL, a plurality of non-volatile active cells AC storing data, the plurality of non-volatile active cells AC being provided at cross sections of the plurality of bit lines BL and the plurality of word lines WL and being connected to the plurality of bit lines BL, the plurality of word lines WL, and the plurality of diffusion source lines VSL, and a controller simultaneously writes or reads data to and from at least two active cells AC among the plurality of active cells AC, in which the number of the plurality of active cells AC is less than that of the cross sections.
摘要翻译：半导体器件具有设置在存储单元区域101中的多个位线BL，与多个位线BL交叉设置的多个字线WL，沿多个字线WL设置的多个扩散源极线VSL，多个非易失性活动单元AC存储数据，多个非易失性活动单元AC设置在多个位线BL和多个字线WL的横截面处并连接到多个位线BL，多个字线WL和多个扩散源线VSL，以及控制器同时向多个有源单元AC中的至少两个有源单元AC写入或读取数据，其中多个活动单元AC的数量细胞AC小于截面积。

3. 发明授权

US08423705B2 Semiconductor device and method for controlling thereof 有权
标题翻译：半导体装置及其控制方法
公开(公告)号：US08423705B2
公开(公告)日：2013-04-16
申请号：US12139274
申请日：2008-06-13
申请人： Hirokazu Nagashima , Kazuki Yamauchi , Junya Kawamata , Tsutomu Nakai , Kenji Arai , Kenichi Takehana
发明人： Hirokazu Nagashima , Kazuki Yamauchi , Junya Kawamata , Tsutomu Nakai , Kenji Arai , Kenichi Takehana
IPC分类号： G06F12/02
CPC分类号： G06F12/0246 , G06F12/0638 , G11C16/20
摘要： A semiconductor device includes a first nonvolatile storage area including a plurality of sectors, a second nonvolatile storage area, a third nonvolatile storage area located in the first nonvolatile storage area, a fourth nonvolatile storage area located in the second nonvolatile storage area, and a control portion selecting one of a first mode and a second mode. In first mode, sectors where the third nonvolatile storage area is not located in the first nonvolatile storage area are used as a main storage area, and the second nonvolatile storage area is used to store a program or data that is read before the first nonvolatile storage area is accessed, the third nonvolatile storage area being used to store control information that controls writing, reading, and erasing of data involved in the first nonvolatile storage area or the second nonvolatile storage area. In the second mode, the first nonvolatile storage area is used as the main storage area, and the fourth nonvolatile storage area is used to store the control information.
摘要翻译：半导体器件包括：第一非易失性存储区域，包括多个扇区;第二非易失性存储区域;位于第一非易失性存储区域中的第三非易失性存储区域;位于第二非易失性存储区域中的第四非易失性存储区域;以及控制选择第一模式和第二模式之一的部分。在第一模式中，将第三非易失性存储区域不位于第一非易失性存储区域中的扇区用作主存储区域，并且第二非易失性存储区域用于存储在第一非易失性存储器之前读取的程序或数据访问第三非易失性存储区域，用于存储控制第一非易失性存储区域或第二非易失性存储区域中涉及的数据的写入，读取和擦除的控制信息。在第二模式中，将第一非易失性存储区域用作主存储区域，并且第四非易失性存储区域用于存储控制信息。

4. 发明申请

US20080298136A1 ENHANCED ERASING OPERATION FOR NON-VOLATILE MEMORY 有权
标题翻译：增强非易失性存储器的擦除操作
公开(公告)号：US20080298136A1
公开(公告)日：2008-12-04
申请号：US12129530
申请日：2008-05-29
申请人： Kazuki Yamauchi , Junya Kawamata , Tsutomu Nakai , Kenji Arai , Hirokazu Nagashima , Kenichi Takehana
发明人： Kazuki Yamauchi , Junya Kawamata , Tsutomu Nakai , Kenji Arai , Hirokazu Nagashima , Kenichi Takehana
IPC分类号： G11C16/14
CPC分类号： G11C16/14
摘要： Structures, methods, and systems for enhanced erasing operation for non-volatile memory are disclosed. In one embodiment, a semiconductor device which comprises a memory cell array having a plurality of non-volatile memory cells, a negative voltage generating circuit for applying a negative voltage to a word line of the memory cell array during an erasing operation of the memory cell array, and a positive voltage generating circuit for applying a positive voltage to a well of the memory cell array when the negative voltage reaches a predetermined voltage.
摘要翻译：公开了用于非易失性存储器的增强擦除操作的结构，方法和系统。在一个实施例中，一种包括具有多个非易失性存储单元的存储单元阵列的半导体器件，用于在存储器单元的擦除操作期间向存储单元阵列的字线施加负电压的负电压产生电路阵列和正电压产生电路，用于当负电压达到预定电压时，向存储单元阵列的阱施加正电压。

5. 发明申请

US20080320208A1 SEMICONDUCTOR DEVICE AND METHOD FOR CONTROLLING THEREOF 有权
标题翻译：半导体器件及其控制方法
公开(公告)号：US20080320208A1
公开(公告)日：2008-12-25
申请号：US12139274
申请日：2008-06-13
申请人： Hirokazu Nagashima , Kazuki Yamauchi , Junya Kawamata , Tsutomu Nakai , Kenji Arai , Kenichi Takehana
发明人： Hirokazu Nagashima , Kazuki Yamauchi , Junya Kawamata , Tsutomu Nakai , Kenji Arai , Kenichi Takehana
IPC分类号： G06F12/02 , G06F12/00
CPC分类号： G06F12/0246 , G06F12/0638 , G11C16/20
摘要： A semiconductor device includes a first nonvolatile storage area including a plurality of sectors, a second nonvolatile storage area, a third nonvolatile storage area located in the first nonvolatile storage area, a fourth nonvolatile storage area located in the second nonvolatile storage area, and a control portion selecting one of a first mode and a second mode. In first mode, sectors where the third nonvolatile storage area is not located in the first nonvolatile storage area are used as a main storage area, and the second nonvolatile storage area is used to store a program or data that is read before the first nonvolatile storage area is accessed, the third nonvolatile storage area being used to store control information that controls writing, reading, and erasing of data involved in the first nonvolatile storage area or the second nonvolatile storage area. In the second mode, the first nonvolatile storage area is used as the main storage area, and the fourth nonvolatile storage area is used to store the control information.
摘要翻译：半导体器件包括：第一非易失性存储区域，包括多个扇区;第二非易失性存储区域;位于第一非易失性存储区域中的第三非易失性存储区域;位于第二非易失性存储区域中的第四非易失性存储区域;以及控制选择第一模式和第二模式之一的部分。在第一模式中，将第三非易失性存储区域不位于第一非易失性存储区域中的扇区用作主存储区域，并且第二非易失性存储区域用于存储在第一非易失性存储器之前读取的程序或数据访问第三非易失性存储区域，用于存储控制第一非易失性存储区域或第二非易失性存储区域中涉及的数据的写入，读取和擦除的控制信息。在第二模式中，将第一非易失性存储区域用作主存储区域，并且第四非易失性存储区域用于存储控制信息。

6. 发明授权

US07679968B2 Enhanced erasing operation for non-volatile memory 有权
标题翻译：非易失性存储器的增强擦除操作
公开(公告)号：US07679968B2
公开(公告)日：2010-03-16
申请号：US12129530
申请日：2008-05-29
申请人： Kazuki Yamauchi , Junya Kawamata , Tsutomu Nakai , Kenji Arai , Hirokazu Nagashima , Kenichi Takehana
发明人： Kazuki Yamauchi , Junya Kawamata , Tsutomu Nakai , Kenji Arai , Hirokazu Nagashima , Kenichi Takehana
IPC分类号： G11C11/34
CPC分类号： G11C16/14
摘要： Structures, methods, and systems for enhanced erasing operation for non-volatile memory are disclosed. In one embodiment, a semiconductor device which comprises a memory cell array having a plurality of non-volatile memory cells, a negative voltage generating circuit for applying a negative voltage to a word line of the memory cell array during an erasing operation of the memory cell array, and a positive voltage generating circuit for applying a positive voltage to a well of the memory cell array when the negative voltage reaches a predetermined voltage.
摘要翻译：公开了用于非易失性存储器的增强擦除操作的结构，方法和系统。在一个实施例中，一种包括具有多个非易失性存储单元的存储单元阵列的半导体器件，用于在存储器单元的擦除操作期间向存储单元阵列的字线施加负电压的负电压产生电路阵列和正电压产生电路，用于当负电压达到预定电压时，向存储单元阵列的阱施加正电压。

7. 发明授权

US07831644B2 Electronic apparatus and content data providing method 有权
标题翻译：电子仪器和内容数据提供方法
公开(公告)号：US07831644B2
公开(公告)日：2010-11-09
申请号：US12421437
申请日：2009-04-09
申请人： Mitsuaki Moritani , Yasuhiro Morioka , Hiroki Iwahara , Naomiki Kobayashi , Hirokazu Nagashima
发明人： Mitsuaki Moritani , Yasuhiro Morioka , Hiroki Iwahara , Naomiki Kobayashi , Hirokazu Nagashima
IPC分类号： G06F17/30 , G06F15/16
CPC分类号： G06F3/0664 , G06F3/0605 , G06F3/067 , H04L12/2812 , H04L2012/2841 , H04L2012/2849
摘要： According to one embodiment, an electronic apparatus includes a wireless communication device, an information acquisition module, a file management information generation module, and an access control module. The information acquisition module acquires, by wireless communication with an external device, metadata corresponding to content data which the external device can provide. The file management information generation module generates, based on the acquired metadata, file management information based on which a host apparatus recognizes the content data as a file stored in a storage medium in the electronic apparatus. The access control module is configured to, upon receiving a read request for a file corresponding to the content data, which is transmitted from the host apparatus, execute external device access processing of acquiring the content data from the external device using the wireless communication device, and output the acquired content data to the host apparatus.
摘要翻译：根据一个实施例，电子设备包括无线通信设备，信息获取模块，文件管理信息生成模块和访问控制模块。信息获取模块通过与外部设备的无线通信获取与外部设备可以提供的内容数据相对应的元数据。文件管理信息生成模块基于获取的元数据生成基于主机设备将内容数据识别为存储在电子设备中的存储介质中的文件的文件管理信息。访问控制模块被配置为在从主机设备接收到对应于内容数据的文件的读取请求时，执行使用无线通信设备从外部设备获取内容数据的外部设备访问处理，并将所获取的内容数据输出到主机设备。

8. 发明申请

US20090292830A1 ELECTRONIC APPARATUS AND CONTENT DATA PROVIDING METHOD 失效
标题翻译：电子设备和内容数据提供方法
公开(公告)号：US20090292830A1
公开(公告)日：2009-11-26
申请号：US12429471
申请日：2009-04-24
申请人： Hirokazu Nagashima , Mitsuaki Moritani , Yasuhiro Morioka , Hiroki Iwahara , Naomiki Kobayashi
发明人： Hirokazu Nagashima , Mitsuaki Moritani , Yasuhiro Morioka , Hiroki Iwahara , Naomiki Kobayashi
IPC分类号： G06F12/02
CPC分类号： G06F17/30
摘要： According to one embodiment, an electronic apparatus is detachably connected to a host apparatus. The electronic apparatus includes a file management information generation module. The file management information generation module generates file management information based on which a host apparatus recognizes each of content data items as a file stored in a storage medium, the file management information being indicative of a plurality of starting storage locations on the storage medium corresponding to starting data blocks of the content data items, and a plurality of shared storage locations on the storage medium, which are shared by the content data items and correspond to second and following data blocks of each of the content data items.
摘要翻译：根据一个实施例，电子设备可拆卸地连接到主机设备。电子设备包括文件管理信息生成模块。文件管理信息生成模块生成文件管理信息，基于该文件管理信息，主机装置将每个内容数据项识别为存储在存储介质中的文件，所述文件管理信息表示存储介质上的多个起始存储位置，对应于开始内容数据项的数据块，以及存储介质上的多个共享存储位置，其由内容数据项共享，并且对应于每个内容数据项的第二和后续数据块。

9. 发明授权

US06788588B2 Asynchronous semiconductor memory device 有权
标题翻译：异步半导体存储器件
公开(公告)号：US06788588B2
公开(公告)日：2004-09-07
申请号：US10345353
申请日：2003-01-16
申请人： Kenji Nagai , Hirokazu Nagashima
发明人： Kenji Nagai , Hirokazu Nagashima
IPC分类号： G11C700
CPC分类号： G11C7/22 , G11C7/1021 , G11C2207/2281
摘要： An asynchronous semiconductor memory device includes an output circuit, which outputs data read from a memory unit, and a high impedance control circuit. The high impedance circuit is connected to the output circuit, stores a burst completion address, and compares a present address with the burst completion address. The high impedance control circuit causes a data output terminal of the output circuit to enter a high impedance state when the present address substantially coincides with the burst completion address. Due to the high impedance control circuit, an exclusive terminal for high impedance control is not necessary.
摘要翻译：异步半导体存储器件包括输出从存储器单元读出的数据的输出电路和高阻抗控制电路。高阻抗电路连接到输出电路，存储突发完成地址，并将当前地址与突发完成地址进行比较。当本地址与突发完成地址基本一致时，高阻抗控制电路使输出电路的数据输出端进入高阻抗状态。由于高阻抗控制电路，不需要用于高阻抗控制的专用端子。

10. 发明授权

US5768209A Semiconductor memory with NAND type memory cells having NOR gate operation delay means 失效
标题翻译：具有与非门操作延迟装置的NAND型存储单元的半导体存储器
公开(公告)号：US5768209A
公开(公告)日：1998-06-16
申请号：US736403
申请日：1996-10-24
申请人： Hirokazu Nagashima
发明人： Hirokazu Nagashima
IPC分类号： G11C11/413 , G11C8/08 , G11C16/06 , G11C8/00
CPC分类号： G11C8/08
摘要： A semiconductor memory with NAND type memory cells includes word drive circuits and selecting circuits. The word drive circuits receive first row selection signals for selecting memory cell blocks connected in series and second row selection signals for selecting given memory cells in the memory cell blocks. The selecting circuits receive the first row selection signals and control gates of memory cell block selection transistors connected in series with the memory cell blocks. Each of the word drive circuits includes a switching speed delaying circuit which causes a switching speed of selecting the memory cell blocks through the first row selection signals to be slower than a switching speed of selecting the given memory cells through the second row selection signals. The switching speed delaying circuit may be realized by inserting a resistor in a drain of each of the memory cell block selection transistors in the NOR gates. The changes of grounding inter-connection potential due to the discharge of inter-connection and gate capacitances are prevented from causing erroneous operation.
摘要翻译：具有NAND型存储单元的半导体存储器包括字驱动电路和选择电路。字驱动电路接收用于选择串联连接的存储单元块的第一行选择信号和用于选择存储单元块中的给定存储单元的第二行选择信号。选择电路接收与存储单元块串联连接的存储单元块选择晶体管的第一行选择信号和控制栅极。每个字驱动电路包括切换速度延迟电路，其使得通过第一行选择信号选择存储单元块的切换速度比通过第二行选择信号选择给定存储单元的切换速度慢。切换速度延迟电路可以通过在NOR门中的每个存储单元块选择晶体管的漏极中插入电阻器来实现。由于互连和栅极电容的放电引起的接地互连电位的变化被防止引起错误的操作。

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