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1. 发明授权

US07679968B2 Enhanced erasing operation for non-volatile memory 有权
标题翻译：非易失性存储器的增强擦除操作
公开(公告)号：US07679968B2
公开(公告)日：2010-03-16
申请号：US12129530
申请日：2008-05-29
申请人： Kazuki Yamauchi , Junya Kawamata , Tsutomu Nakai , Kenji Arai , Hirokazu Nagashima , Kenichi Takehana
发明人： Kazuki Yamauchi , Junya Kawamata , Tsutomu Nakai , Kenji Arai , Hirokazu Nagashima , Kenichi Takehana
IPC分类号： G11C11/34
CPC分类号： G11C16/14
摘要： Structures, methods, and systems for enhanced erasing operation for non-volatile memory are disclosed. In one embodiment, a semiconductor device which comprises a memory cell array having a plurality of non-volatile memory cells, a negative voltage generating circuit for applying a negative voltage to a word line of the memory cell array during an erasing operation of the memory cell array, and a positive voltage generating circuit for applying a positive voltage to a well of the memory cell array when the negative voltage reaches a predetermined voltage.
摘要翻译：公开了用于非易失性存储器的增强擦除操作的结构，方法和系统。在一个实施例中，一种包括具有多个非易失性存储单元的存储单元阵列的半导体器件，用于在存储器单元的擦除操作期间向存储单元阵列的字线施加负电压的负电压产生电路阵列和正电压产生电路，用于当负电压达到预定电压时，向存储单元阵列的阱施加正电压。

2. 发明授权

US08423705B2 Semiconductor device and method for controlling thereof 有权
标题翻译：半导体装置及其控制方法
公开(公告)号：US08423705B2
公开(公告)日：2013-04-16
申请号：US12139274
申请日：2008-06-13
申请人： Hirokazu Nagashima , Kazuki Yamauchi , Junya Kawamata , Tsutomu Nakai , Kenji Arai , Kenichi Takehana
发明人： Hirokazu Nagashima , Kazuki Yamauchi , Junya Kawamata , Tsutomu Nakai , Kenji Arai , Kenichi Takehana
IPC分类号： G06F12/02
CPC分类号： G06F12/0246 , G06F12/0638 , G11C16/20
摘要： A semiconductor device includes a first nonvolatile storage area including a plurality of sectors, a second nonvolatile storage area, a third nonvolatile storage area located in the first nonvolatile storage area, a fourth nonvolatile storage area located in the second nonvolatile storage area, and a control portion selecting one of a first mode and a second mode. In first mode, sectors where the third nonvolatile storage area is not located in the first nonvolatile storage area are used as a main storage area, and the second nonvolatile storage area is used to store a program or data that is read before the first nonvolatile storage area is accessed, the third nonvolatile storage area being used to store control information that controls writing, reading, and erasing of data involved in the first nonvolatile storage area or the second nonvolatile storage area. In the second mode, the first nonvolatile storage area is used as the main storage area, and the fourth nonvolatile storage area is used to store the control information.
摘要翻译：半导体器件包括：第一非易失性存储区域，包括多个扇区;第二非易失性存储区域;位于第一非易失性存储区域中的第三非易失性存储区域;位于第二非易失性存储区域中的第四非易失性存储区域;以及控制选择第一模式和第二模式之一的部分。在第一模式中，将第三非易失性存储区域不位于第一非易失性存储区域中的扇区用作主存储区域，并且第二非易失性存储区域用于存储在第一非易失性存储器之前读取的程序或数据访问第三非易失性存储区域，用于存储控制第一非易失性存储区域或第二非易失性存储区域中涉及的数据的写入，读取和擦除的控制信息。在第二模式中，将第一非易失性存储区域用作主存储区域，并且第四非易失性存储区域用于存储控制信息。

3. 发明申请

US20080298136A1 ENHANCED ERASING OPERATION FOR NON-VOLATILE MEMORY 有权
标题翻译：增强非易失性存储器的擦除操作
公开(公告)号：US20080298136A1
公开(公告)日：2008-12-04
申请号：US12129530
申请日：2008-05-29
申请人： Kazuki Yamauchi , Junya Kawamata , Tsutomu Nakai , Kenji Arai , Hirokazu Nagashima , Kenichi Takehana
发明人： Kazuki Yamauchi , Junya Kawamata , Tsutomu Nakai , Kenji Arai , Hirokazu Nagashima , Kenichi Takehana
IPC分类号： G11C16/14
CPC分类号： G11C16/14
摘要： Structures, methods, and systems for enhanced erasing operation for non-volatile memory are disclosed. In one embodiment, a semiconductor device which comprises a memory cell array having a plurality of non-volatile memory cells, a negative voltage generating circuit for applying a negative voltage to a word line of the memory cell array during an erasing operation of the memory cell array, and a positive voltage generating circuit for applying a positive voltage to a well of the memory cell array when the negative voltage reaches a predetermined voltage.
摘要翻译：公开了用于非易失性存储器的增强擦除操作的结构，方法和系统。在一个实施例中，一种包括具有多个非易失性存储单元的存储单元阵列的半导体器件，用于在存储器单元的擦除操作期间向存储单元阵列的字线施加负电压的负电压产生电路阵列和正电压产生电路，用于当负电压达到预定电压时，向存储单元阵列的阱施加正电压。

4. 发明申请

US20090010076A1 SEMICONDUCTOR DEVICE AND CONTROLLING METHOD FOR THE SAME 有权
标题翻译：半导体器件及其控制方法
公开(公告)号：US20090010076A1
公开(公告)日：2009-01-08
申请号：US12130583
申请日：2008-05-30
申请人： Junya Kawamata , Tsutomu Nakai , Hirokazu Nagashima , Kenichi Takehana , Kenji Arai , Kazuki Yamauchi , Kazuhide Kurosaki
发明人： Junya Kawamata , Tsutomu Nakai , Hirokazu Nagashima , Kenichi Takehana , Kenji Arai , Kazuki Yamauchi , Kazuhide Kurosaki
IPC分类号： G11C7/00
CPC分类号： G11C29/74 , G11C16/0416 , H01L27/0207 , H01L27/105 , H01L27/115 , H01L27/11519 , H01L27/11526 , H01L27/11531
摘要： A semiconductor device has a plurality of bit lines BL provided in a memory cell area 101, a plurality of word lines WL provided crossing the plurality of bit lines BL, a plurality of diffusion source lines VSL provided along the plurality of word lines WL, a plurality of non-volatile active cells AC storing data, the plurality of non-volatile active cells AC being provided at cross sections of the plurality of bit lines BL and the plurality of word lines WL and being connected to the plurality of bit lines BL, the plurality of word lines WL, and the plurality of diffusion source lines VSL, and a controller simultaneously writes or reads data to and from at least two active cells AC among the plurality of active cells AC, in which the number of the plurality of active cells AC is less than that of the cross sections.
摘要翻译：半导体器件具有设置在存储单元区域101中的多个位线BL，与多个位线BL交叉设置的多个字线WL，沿多个字线WL设置的多个扩散源极线VSL，多个非易失性活动单元AC存储数据，多个非易失性活动单元AC设置在多个位线BL和多个字线WL的横截面处并连接到多个位线BL，多个字线WL和多个扩散源线VSL，以及控制器同时向多个有源单元AC中的至少两个有源单元AC写入或读取数据，其中多个活动单元AC的数量细胞AC小于截面积。

5. 发明申请

US20080320208A1 SEMICONDUCTOR DEVICE AND METHOD FOR CONTROLLING THEREOF 有权
标题翻译：半导体器件及其控制方法
公开(公告)号：US20080320208A1
公开(公告)日：2008-12-25
申请号：US12139274
申请日：2008-06-13
申请人： Hirokazu Nagashima , Kazuki Yamauchi , Junya Kawamata , Tsutomu Nakai , Kenji Arai , Kenichi Takehana
发明人： Hirokazu Nagashima , Kazuki Yamauchi , Junya Kawamata , Tsutomu Nakai , Kenji Arai , Kenichi Takehana
IPC分类号： G06F12/02 , G06F12/00
CPC分类号： G06F12/0246 , G06F12/0638 , G11C16/20
摘要： A semiconductor device includes a first nonvolatile storage area including a plurality of sectors, a second nonvolatile storage area, a third nonvolatile storage area located in the first nonvolatile storage area, a fourth nonvolatile storage area located in the second nonvolatile storage area, and a control portion selecting one of a first mode and a second mode. In first mode, sectors where the third nonvolatile storage area is not located in the first nonvolatile storage area are used as a main storage area, and the second nonvolatile storage area is used to store a program or data that is read before the first nonvolatile storage area is accessed, the third nonvolatile storage area being used to store control information that controls writing, reading, and erasing of data involved in the first nonvolatile storage area or the second nonvolatile storage area. In the second mode, the first nonvolatile storage area is used as the main storage area, and the fourth nonvolatile storage area is used to store the control information.
摘要翻译：半导体器件包括：第一非易失性存储区域，包括多个扇区;第二非易失性存储区域;位于第一非易失性存储区域中的第三非易失性存储区域;位于第二非易失性存储区域中的第四非易失性存储区域;以及控制选择第一模式和第二模式之一的部分。在第一模式中，将第三非易失性存储区域不位于第一非易失性存储区域中的扇区用作主存储区域，并且第二非易失性存储区域用于存储在第一非易失性存储器之前读取的程序或数据访问第三非易失性存储区域，用于存储控制第一非易失性存储区域或第二非易失性存储区域中涉及的数据的写入，读取和擦除的控制信息。在第二模式中，将第一非易失性存储区域用作主存储区域，并且第四非易失性存储区域用于存储控制信息。

6. 发明授权

US07787312B2 Semiconductor device and controlling method for the same 有权
标题翻译：半导体装置及其控制方法
公开(公告)号：US07787312B2
公开(公告)日：2010-08-31
申请号：US12130583
申请日：2008-05-30
申请人： Junya Kawamata , Tsutomu Nakai , Hirokazu Nagashima , Kenichi Takehana , Kenji Arai , Kazuki Yamauchi , Kazuhide Kurosaki
发明人： Junya Kawamata , Tsutomu Nakai , Hirokazu Nagashima , Kenichi Takehana , Kenji Arai , Kazuki Yamauchi , Kazuhide Kurosaki
IPC分类号： G11C7/10
CPC分类号： G11C29/74 , G11C16/0416 , H01L27/0207 , H01L27/105 , H01L27/115 , H01L27/11519 , H01L27/11526 , H01L27/11531
摘要： A semiconductor device has a plurality of bit lines BL provided in a memory cell area 101, a plurality of word lines WL provided crossing the plurality of bit lines BL, a plurality of diffusion source lines VSL provided along the plurality of word lines WL, a plurality of non-volatile active cells AC storing data, the plurality of non-volatile active cells AC being provided at cross sections of the plurality of bit lines BL and the plurality of word lines WL and being connected to the plurality of bit lines BL, the plurality of word lines WL, and the plurality of diffusion source lines VSL, and a controller simultaneously writes or reads data to and from at least two active cells AC among the plurality of active cells AC, in which the number of the plurality of active cells AC is less than that of the cross sections.
摘要翻译：半导体器件具有设置在存储单元区域101中的多个位线BL，与多个位线BL交叉设置的多个字线WL，沿多个字线WL设置的多个扩散源极线VSL，多个非易失性活动单元AC存储数据，多个非易失性活动单元AC设置在多个位线BL和多个字线WL的横截面处并连接到多个位线BL，多个字线WL和多个扩散源线VSL，以及控制器同时向多个有源单元AC中的至少两个有源单元AC写入或读取数据，其中多个活动单元AC的数量细胞AC小于截面积。

7. 发明申请

US20060023539A1 Semiconductor device and method of generating sense signal 有权
标题翻译：半导体器件和产生感测信号的方法
公开(公告)号：US20060023539A1
公开(公告)日：2006-02-02
申请号：US11194007
申请日：2005-07-29
申请人： Tsutomu Nakai , Takao Akaogi , Kazuhide Kurosaki
发明人： Tsutomu Nakai , Takao Akaogi , Kazuhide Kurosaki
IPC分类号： G11C7/02
CPC分类号： G11C7/062 , G11C7/067 , G11C11/5642 , G11C16/28 , G11C2211/5645
摘要： A semiconductor device includes a first cascode circuit having a first current mirror amplifying a reference current flowing through a data line of a reference cell, and a second current mirror generating a first potential from an amplified reference current; and a second cascode circuit having a third current mirror amplifying a core current flowing through a data line of a core cell, and a transistor receiving a gate voltage corresponding to the amplified reference current and generating a second potential based on a difference between an amplified core cell current and the amplified reference current. Since the second potential is generated by the difference between the core cell current and the reference cell current, the second potential swings in the full range of the ground power supply voltage to the ground potential, and the range of the amplitude of the power supply voltage can be efficiently utilized. Sensing is enabled for a fine current margin.
摘要翻译：半导体器件包括第一共源共栅电路，其具有放大流过参考单元的数据线的参考电流的第一电流镜和从放大的参考电流产生第一电位的第二电流镜; 以及第二共源共栅电路，其具有放大流过芯电池的数据线的芯电流的第三电流镜，以及接收与放大的参考电流相对应的栅极电压的晶体管，并且基于放大芯之间的差产生第二电位电池电流和放大参考电流。由于第二电位是由芯电池电流和参考电池电流之间的差产生的，所以第二电位在接地电源电压的全范围内摆动到接地电位，电源电压幅度的范围可以有效利用。感应功能可用于精细的电流裕度。

8. 发明授权

US07450419B2 Semiconductor device and control method therefor 有权
标题翻译：半导体装置及其控制方法
公开(公告)号：US07450419B2
公开(公告)日：2008-11-11
申请号：US11636111
申请日：2006-12-07
申请人： Mototada Sakashita , Masaru Yano , Akira Ogawa , Tsutomu Nakai
发明人： Mototada Sakashita , Masaru Yano , Akira Ogawa , Tsutomu Nakai
IPC分类号： G11C16/06 , G11C16/10 , G11C16/32 , G11C16/24
CPC分类号： G11C16/10 , G11C2207/2263
摘要： The present invention provides a semiconductor device and a method for controlling a semiconductor device having a memory cell array having a plurality of nonvolatile memory cells, the method including detecting the number of bits to be written as division data that is divided from data to be programmed into the memory cell array, comparing the number of bits with a predetermined number of bits, inverting or not inverting the division data to produce inversion data in accordance with a result of comparing the number of bits with the predetermined number of bits, and programming the inversion data into the memory cell array. The method further includes detecting the number of bits to be written as next division data and comparing the number of bits of next division data with the predetermined number of bits, while concurrently programming the inversion data into the memory cell array.
摘要翻译：本发明提供一种用于控制具有多个非易失性存储单元的存储单元阵列的半导体器件的半导体器件和方法，该方法包括检测要写入的位数，作为从要编程的数据划分的划分数据进入存储单元阵列，将比特数与预定比特数进行比较，根据比特数与预定比特数比较的结果，反转或不反相除数数据以产生反转数据，并对反转数据进入存储单元阵列。该方法还包括检测要写入的比特数作为下一个分割数据，并将下一个分割数据的比特数与预定比特数进行比较，同时将反演数据编程到存储单元阵列中。

9. 发明授权

US07057229B2 Nonvolatile memory device for storing multi-bit data 失效
标题翻译：用于存储多位数据的非易失性存储器件
公开(公告)号：US07057229B2
公开(公告)日：2006-06-06
申请号：US10341424
申请日：2003-01-14
申请人： Tsutomu Nakai
发明人： Tsutomu Nakai
IPC分类号： H01L29/788
CPC分类号： H01L29/66833 , H01L21/28282 , H01L29/42352 , H01L29/792 , H01L29/7923
摘要： A semiconductor nonvolatile memory device for storing multi-bit data has a memory cell having a source region S and a drain region D formed at the surface of a semiconductor substrate, a gate insulator film and a control gate CG formed on a channel region CH between the source region S and the drain region D and a nonconductive trap gate in the gate insulator film. An indentation 4 is provided at the surface of the semiconductor substrate covering a region from a position in the vicinity of the drain region in the channel region to the drain region. By providing the indentation 4 on the drain region side of the channel region, the trap gate is positioned in the direction of a channel current flowing from the source region S to the drain region D. Then, the a charge having run through the channel region CH is injected efficiently into the trap gate on the indentation.
摘要翻译：用于存储多位数据的半导体非易失性存储器件具有存储单元，其具有形成在半导体衬底的表面处的源极区域S和漏极区域D，栅极绝缘膜和控制栅极CG，栅极绝缘膜和控制栅极CG形成在沟道区域CH之间，源极区S和漏极区D以及栅极绝缘膜中的非导电陷阱栅极。在半导体衬底的表面上设置有一个凹槽4，该表面覆盖从沟道区域中的漏极区域附近的位置到漏极区域的区域。通过在沟道区域的漏极区侧设置压痕4，阱栅位于从源极区域S流到漏极区域D的沟道电流的方向上。然后，通过沟道区域 CH被有效地注入到压痕上的陷阱门中。

10. 发明授权

US06865133B2 Memory circuit with redundant configuration 有权
标题翻译：具有冗余配置的内存电路
公开(公告)号：US06865133B2
公开(公告)日：2005-03-08
申请号：US10652035
申请日：2003-09-02
申请人： Yoshihiro Tsukidate , Kazuhiro Kurihara , Yasushi Kasa , Tsutomu Nakai , Andy Cheung
发明人： Yoshihiro Tsukidate , Kazuhiro Kurihara , Yasushi Kasa , Tsutomu Nakai , Andy Cheung
IPC分类号： G11C16/06 , G11C16/02 , G11C29/00 , G11C29/04 , G11C29/24 , G11C8/00
CPC分类号： G11C29/82 , G11C29/24 , G11C29/846
摘要： A memory circuit has a plurality of blocks which further comprises a plurality of regular sectors and a spare sector, wherein each sector further comprises a plurality of memory cells, and when a regular sector in a first block is defective, this defective regular sector is replaced with a spare sector in a second block. And responding to an address to be supplied, the regular sector corresponding to the supplied address in the first block and the spare selector in the second block are selected simultaneously during a first period, and after the first period, selection of one of the regular sector and the spare sector is maintained according to the result of redundancy judgment on whether the supply address matches with the redundant address. Regardless the result of redundancy judgment on whether the supplied address matches the redundant address indicating the defective sector, a regular sector in the first block and the spare sector in the second block, to be a pair thereof, are set to selected status simultaneously during the first period when access operation stars, so a drop in access speed due to a redundancy judgment operation can be suppressed.
摘要翻译：存储器电路具有多个块，其还包括多个常规扇区和备用扇区，其中每个扇区还包括多个存储器单元，并且当第一块中的规则扇区有缺陷时，该缺陷正规扇区被替换在第二块中有一个备用扇区。并且响应要提供的地址，在第一时段期间同时选择对应于第一块中提供的地址的常规扇区和第二块中的备用选择器，并且在第一周期之后，选择常规扇区之一并根据关于供应地址是否与冗余地址匹配的冗余判断结果来维护备用扇区。无论冗余判断结果是否提供的地址是否与指示缺陷扇区的冗余地址匹配，第一块中的规则扇区和第二块中的备用扇区成为其一对，在访问操作星的第一周期，因此可以抑制由冗余判断操作引起的访问速度的下降。

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