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1. 发明授权

US06822901B2 Non-volatile memory circuit comprising automatic erase function 失效
标题翻译：包括自动擦除功能的非易失性存储电路
公开(公告)号：US06822901B2
公开(公告)日：2004-11-23
申请号：US10346123
申请日：2003-01-17
申请人： Junya Kawamata
发明人： Junya Kawamata
IPC分类号： G11C1604
CPC分类号： G11C16/16 , G11C16/22
摘要： A nonvolatile memory circuit, comprises: memory regions, which contain N (N is a plurality) of the sectors, N not being an exponentiated number of two and the sectors having the same capacity; a sector selection circuit for decoding a sector address and selecting the sector which corresponds to the sector address; and a memory control circuit which, in response to an erase command, executes an erase operation to the selected sector and, upon verifying that the erasure is complete, sequentially changes said sector address to select the next sector. When a sector that does not exist in the memory regions is selected, said memory control circuit selects the next sector without performing an erase operation to the nonexistent sector.
摘要翻译：一种非易失性存储器电路，包括：存储区域，其包含N（N是多个）扇区，N不是二进制数，并且具有相同容量的扇区; 扇区选择电路，用于对扇区地址进行解码并选择对应于扇区地址的扇区; 以及存储器控制电路，其响应于擦除命令对所选择的扇区执行擦除操作，并且在验证完成擦除之后，顺序地改变所述扇区地址以选择下一个扇区。当选择存储区域中不存在的扇区时，所述存储器控制电路选择下一个扇区，而不对不存在的扇区执行擦除操作。

2. 发明授权

US08423705B2 Semiconductor device and method for controlling thereof 有权
标题翻译：半导体装置及其控制方法
公开(公告)号：US08423705B2
公开(公告)日：2013-04-16
申请号：US12139274
申请日：2008-06-13
申请人： Hirokazu Nagashima , Kazuki Yamauchi , Junya Kawamata , Tsutomu Nakai , Kenji Arai , Kenichi Takehana
发明人： Hirokazu Nagashima , Kazuki Yamauchi , Junya Kawamata , Tsutomu Nakai , Kenji Arai , Kenichi Takehana
IPC分类号： G06F12/02
CPC分类号： G06F12/0246 , G06F12/0638 , G11C16/20
摘要： A semiconductor device includes a first nonvolatile storage area including a plurality of sectors, a second nonvolatile storage area, a third nonvolatile storage area located in the first nonvolatile storage area, a fourth nonvolatile storage area located in the second nonvolatile storage area, and a control portion selecting one of a first mode and a second mode. In first mode, sectors where the third nonvolatile storage area is not located in the first nonvolatile storage area are used as a main storage area, and the second nonvolatile storage area is used to store a program or data that is read before the first nonvolatile storage area is accessed, the third nonvolatile storage area being used to store control information that controls writing, reading, and erasing of data involved in the first nonvolatile storage area or the second nonvolatile storage area. In the second mode, the first nonvolatile storage area is used as the main storage area, and the fourth nonvolatile storage area is used to store the control information.
摘要翻译：半导体器件包括：第一非易失性存储区域，包括多个扇区;第二非易失性存储区域;位于第一非易失性存储区域中的第三非易失性存储区域;位于第二非易失性存储区域中的第四非易失性存储区域;以及控制选择第一模式和第二模式之一的部分。在第一模式中，将第三非易失性存储区域不位于第一非易失性存储区域中的扇区用作主存储区域，并且第二非易失性存储区域用于存储在第一非易失性存储器之前读取的程序或数据访问第三非易失性存储区域，用于存储控制第一非易失性存储区域或第二非易失性存储区域中涉及的数据的写入，读取和擦除的控制信息。在第二模式中，将第一非易失性存储区域用作主存储区域，并且第四非易失性存储区域用于存储控制信息。

3. 发明申请

US20080298136A1 ENHANCED ERASING OPERATION FOR NON-VOLATILE MEMORY 有权
标题翻译：增强非易失性存储器的擦除操作
公开(公告)号：US20080298136A1
公开(公告)日：2008-12-04
申请号：US12129530
申请日：2008-05-29
申请人： Kazuki Yamauchi , Junya Kawamata , Tsutomu Nakai , Kenji Arai , Hirokazu Nagashima , Kenichi Takehana
发明人： Kazuki Yamauchi , Junya Kawamata , Tsutomu Nakai , Kenji Arai , Hirokazu Nagashima , Kenichi Takehana
IPC分类号： G11C16/14
CPC分类号： G11C16/14
摘要： Structures, methods, and systems for enhanced erasing operation for non-volatile memory are disclosed. In one embodiment, a semiconductor device which comprises a memory cell array having a plurality of non-volatile memory cells, a negative voltage generating circuit for applying a negative voltage to a word line of the memory cell array during an erasing operation of the memory cell array, and a positive voltage generating circuit for applying a positive voltage to a well of the memory cell array when the negative voltage reaches a predetermined voltage.
摘要翻译：公开了用于非易失性存储器的增强擦除操作的结构，方法和系统。在一个实施例中，一种包括具有多个非易失性存储单元的存储单元阵列的半导体器件，用于在存储器单元的擦除操作期间向存储单元阵列的字线施加负电压的负电压产生电路阵列和正电压产生电路，用于当负电压达到预定电压时，向存储单元阵列的阱施加正电压。

4. 发明授权

US06574162B2 Semiconductor memory device utilizing access to memory area located outside main memory area 有权
公开(公告)号：US06574162B2
公开(公告)日：2003-06-03
申请号：US10160117
申请日：2002-06-04
申请人： Junya Kawamata
发明人： Junya Kawamata
IPC分类号： G11C700
CPC分类号： G11C8/00 , G11C8/12
摘要： A semiconductor memory device is provided. The semiconductor memory device includes a primary memory area including a plurality of memory blocks arranged in rows and columns, the plurality of memory blocks including a predetermined memory block; a secondary memory area including a hidden memory block situated in the same column as the predetermined memory block; a decision circuit selecting one of a first mode for reading first data from the primary memory area and a second mode for reading second data from the secondary memory area, the decision circuit outputting a signal when the second mode and an address of the predetermined memory block are specified; a column decoder selecting a column corresponding to a column address inputted thereto; and a word-line decoder selecting a word line of the hidden memory block by boosting a word line of an adjacent memory block included in the primary memory area in response to the signal, the word-line decoder being included in the adjacent memory block, wherein the second data is read from the hidden memory block when the column decoder and the word-line decoder select the column corresponding to the hidden memory block and the word line of the hidden memory block respectively. According to the present invention, the semiconductor memory device enables efficient selection of an address of the secondary memory area with a simple circuit structure.

5. 发明授权

US06535420B1 Electronically rewritable non-volatile semiconductor memory device 有权
公开(公告)号：US06535420B1
公开(公告)日：2003-03-18
申请号：US09717296
申请日：2000-11-22
申请人： Junya Kawamata
发明人： Junya Kawamata
IPC分类号： G11C1604
CPC分类号： G11C16/22 , G11C16/08
摘要： The present invention provides a non-volatile semiconductor memory device that can protect each block without increasing a memory element area, and make an access to the memory cells in hidden blocks in a hidden mode in which the hidden blocks are accessed. This electrically rewritable non-volatile semiconductor memory device includes K non-volatile memory elements that store protection information, a non-volatile memory element that stores a protection status, and a storage area that is logically divided into 2K or less blocks. In accordance with information stored in the K non-volatile memory elements and the non-volatile memory element that stored the protection status, a write operation is inhibited in the successive bocks in storage area.

6. 发明授权

US07787312B2 Semiconductor device and controlling method for the same 有权
标题翻译：半导体装置及其控制方法
公开(公告)号：US07787312B2
公开(公告)日：2010-08-31
申请号：US12130583
申请日：2008-05-30
申请人： Junya Kawamata , Tsutomu Nakai , Hirokazu Nagashima , Kenichi Takehana , Kenji Arai , Kazuki Yamauchi , Kazuhide Kurosaki
发明人： Junya Kawamata , Tsutomu Nakai , Hirokazu Nagashima , Kenichi Takehana , Kenji Arai , Kazuki Yamauchi , Kazuhide Kurosaki
IPC分类号： G11C7/10
CPC分类号： G11C29/74 , G11C16/0416 , H01L27/0207 , H01L27/105 , H01L27/115 , H01L27/11519 , H01L27/11526 , H01L27/11531
摘要： A semiconductor device has a plurality of bit lines BL provided in a memory cell area 101, a plurality of word lines WL provided crossing the plurality of bit lines BL, a plurality of diffusion source lines VSL provided along the plurality of word lines WL, a plurality of non-volatile active cells AC storing data, the plurality of non-volatile active cells AC being provided at cross sections of the plurality of bit lines BL and the plurality of word lines WL and being connected to the plurality of bit lines BL, the plurality of word lines WL, and the plurality of diffusion source lines VSL, and a controller simultaneously writes or reads data to and from at least two active cells AC among the plurality of active cells AC, in which the number of the plurality of active cells AC is less than that of the cross sections.
摘要翻译：半导体器件具有设置在存储单元区域101中的多个位线BL，与多个位线BL交叉设置的多个字线WL，沿多个字线WL设置的多个扩散源极线VSL，多个非易失性活动单元AC存储数据，多个非易失性活动单元AC设置在多个位线BL和多个字线WL的横截面处并连接到多个位线BL，多个字线WL和多个扩散源线VSL，以及控制器同时向多个有源单元AC中的至少两个有源单元AC写入或读取数据，其中多个活动单元AC的数量细胞AC小于截面积。

7. 发明授权

US06728136B2 Electronically rewritable non-volatile semiconductor memory device 有权
标题翻译：电子可重写非易失性半导体存储器件
公开(公告)号：US06728136B2
公开(公告)日：2004-04-27
申请号：US10357372
申请日：2003-02-04
申请人： Junya Kawamata
发明人： Junya Kawamata
IPC分类号： G11C1604
CPC分类号： G11C16/22 , G11C16/08
摘要： The present invention provides a non-volatile semiconductor memory device that can protect each block without increasing a memory element area, and make an access to the memory cells in hidden blocks in a hidden mode in which the hidden blocks are accessed. This electrically rewritable non-volatile semiconductor memory device includes K non-volatile memory elements that store protection information, a non-volatile memory element that stores a protection status, and a storage area that is logically divided into 2K or less blocks. In accordance with information stored in the K non-volatile memory elements and the non-volatile memory element that stored the protection status, a write operation is inhibited in the successive bocks in storage area.
摘要翻译：本发明提供了一种非易失性半导体存储器件，其可以在不增加存储元件面积的情况下保护每个块，并且以隐藏模式访问隐藏块中的存储器单元。这种电可重写非易失性半导体存储器件包括存储保护信息的K个非易失性存储器元件，存储保护状态的非易失性存储器元件以及逻辑上划分为2K或更小块的存储区域。根据存储在K非易失性存储器元件中的信息和存储保护状态的非易失性存储元件，在存储区域中的连续块中禁止写入操作。

8. 发明授权

US5982661A Memory device 有权
标题翻译：内存设备
公开(公告)号：US5982661A
公开(公告)日：1999-11-09
申请号：US247546
申请日：1999-02-10
申请人： Junya Kawamata
发明人： Junya Kawamata
IPC分类号： G11C16/02 , G11C16/00 , G11C16/26 , G11C16/04
CPC分类号： G11C16/26
摘要： The present invention is a non-volatile memory comprising: first and second floating gate MOS transistors which are electrically written and erased and which are operatively connected between power sources serially; and an output terminal connected to the contact point of the first and second MOS transistors; wherein a first datum is stored by writing to the first MOS transistor and erasing the second MOS transistor, and a second datum is stored by erasing the first MOS transistor and writing to the second MOS transistor. With the aforementioned memory device, through current does not flow to the power source, because only one transistor will be conductive even if read voltage is applied to the control gate of both transistors. Consequently, reading time can be shortened, without leading to increased power consumption, by maintaining the control gate at the read voltage level.
摘要翻译：本发明是一种非易失性存储器，包括：第一和第二浮置栅极MOS晶体管，其被电写入和擦除，并且可串联连接在电源之间; 以及连接到第一和第二MOS晶体管的接触点的输出端子; 其中通过写入第一MOS晶体管来存储第一数据并擦除第二MOS晶体管，并且通过擦除第一MOS晶体管并写入第二MOS晶体管来存储第二数据。利用上述存储器件，通过电流不流到电源，因为即使读取电压施加到两个晶体管的控制栅极，也只有一个晶体管将导通。因此，通过将控制栅极保持在读取电压电平，可以缩短读取时间，而不会导致增加的功耗。

9. 发明授权

US07679968B2 Enhanced erasing operation for non-volatile memory 有权
标题翻译：非易失性存储器的增强擦除操作
公开(公告)号：US07679968B2
公开(公告)日：2010-03-16
申请号：US12129530
申请日：2008-05-29
申请人： Kazuki Yamauchi , Junya Kawamata , Tsutomu Nakai , Kenji Arai , Hirokazu Nagashima , Kenichi Takehana
发明人： Kazuki Yamauchi , Junya Kawamata , Tsutomu Nakai , Kenji Arai , Hirokazu Nagashima , Kenichi Takehana
IPC分类号： G11C11/34
CPC分类号： G11C16/14
摘要： Structures, methods, and systems for enhanced erasing operation for non-volatile memory are disclosed. In one embodiment, a semiconductor device which comprises a memory cell array having a plurality of non-volatile memory cells, a negative voltage generating circuit for applying a negative voltage to a word line of the memory cell array during an erasing operation of the memory cell array, and a positive voltage generating circuit for applying a positive voltage to a well of the memory cell array when the negative voltage reaches a predetermined voltage.
摘要翻译：公开了用于非易失性存储器的增强擦除操作的结构，方法和系统。在一个实施例中，一种包括具有多个非易失性存储单元的存储单元阵列的半导体器件，用于在存储器单元的擦除操作期间向存储单元阵列的字线施加负电压的负电压产生电路阵列和正电压产生电路，用于当负电压达到预定电压时，向存储单元阵列的阱施加正电压。

10. 发明授权

US06711055B2 Nonvolatile semiconductor memory device of dual-operation type with data protection function 有权
标题翻译：具有数据保护功能的双操作型非易失半导体存储器件
公开(公告)号：US06711055B2
公开(公告)日：2004-03-23
申请号：US10263646
申请日：2002-10-04
申请人： Junya Kawamata
发明人： Junya Kawamata
IPC分类号： G11C1604
CPC分类号： G11C16/22 , G11C7/24 , G11C8/12
摘要： A nonvolatile semiconductor memory device includes a plurality of banks including respective memory cell arrays independent of each other, a password storage area that is associated with one of the banks, a bank decoder which generates a bank selection signal by decoding a bank address, a first bank selection circuit which outputs a write instruction or a read instruction to the one of the banks, a plurality of second bank selection circuits which outputs a write instruction or a read instruction to the respective banks except for the one of the banks, and a command-decode-&-bank-control circuit which controls the first and second bank selection circuits such that receipt of a first command causes one of the first and second bank selection circuits selected by the bank selection signal to output a write instruction or a read instruction, and such that receipt of a second command causes the first bank selection circuit to output a write instruction independently of the bank selection signal, and causes one of the second bank selection circuits selected by the bank selection signal to output a read instruction.
摘要翻译：非易失性半导体存储器件包括多个存储体，包括彼此独立的相应存储单元阵列，与一个存储体相关联的密码存储区域，通过解码存储体地址产生存储区选择信号的存储体解码器，第一向所述一个组中的一个存储体输出写入指令或读取指令的多个第二存储体选择电路，向所述存储体中的所述存储体之外的各个存储体输出写入指令或读取指令的多个第二存储体选择电路，以及指令 - 控制所述第一和第二存储区选择电路，使得接收到第一命令使得所述存储体选择信号选择的所述第一和第二存储体选择电路中的一个输出写指令或读指令并且使得接收第二命令使得第一存储体选择电路独立于存储体选择si输出写入指令并且使得由存储体选择信号选择的第二存储体选择电路之一输出读取指令。

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