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1. 发明授权

US07787312B2 Semiconductor device and controlling method for the same 有权
标题翻译：半导体装置及其控制方法
公开(公告)号：US07787312B2
公开(公告)日：2010-08-31
申请号：US12130583
申请日：2008-05-30
申请人： Junya Kawamata , Tsutomu Nakai , Hirokazu Nagashima , Kenichi Takehana , Kenji Arai , Kazuki Yamauchi , Kazuhide Kurosaki
发明人： Junya Kawamata , Tsutomu Nakai , Hirokazu Nagashima , Kenichi Takehana , Kenji Arai , Kazuki Yamauchi , Kazuhide Kurosaki
IPC分类号： G11C7/10
CPC分类号： G11C29/74 , G11C16/0416 , H01L27/0207 , H01L27/105 , H01L27/115 , H01L27/11519 , H01L27/11526 , H01L27/11531
摘要： A semiconductor device has a plurality of bit lines BL provided in a memory cell area 101, a plurality of word lines WL provided crossing the plurality of bit lines BL, a plurality of diffusion source lines VSL provided along the plurality of word lines WL, a plurality of non-volatile active cells AC storing data, the plurality of non-volatile active cells AC being provided at cross sections of the plurality of bit lines BL and the plurality of word lines WL and being connected to the plurality of bit lines BL, the plurality of word lines WL, and the plurality of diffusion source lines VSL, and a controller simultaneously writes or reads data to and from at least two active cells AC among the plurality of active cells AC, in which the number of the plurality of active cells AC is less than that of the cross sections.
摘要翻译：半导体器件具有设置在存储单元区域101中的多个位线BL，与多个位线BL交叉设置的多个字线WL，沿多个字线WL设置的多个扩散源极线VSL，多个非易失性活动单元AC存储数据，多个非易失性活动单元AC设置在多个位线BL和多个字线WL的横截面处并连接到多个位线BL，多个字线WL和多个扩散源线VSL，以及控制器同时向多个有源单元AC中的至少两个有源单元AC写入或读取数据，其中多个活动单元AC的数量细胞AC小于截面积。

2. 发明申请

US20090010076A1 SEMICONDUCTOR DEVICE AND CONTROLLING METHOD FOR THE SAME 有权
标题翻译：半导体器件及其控制方法
公开(公告)号：US20090010076A1
公开(公告)日：2009-01-08
申请号：US12130583
申请日：2008-05-30
申请人： Junya Kawamata , Tsutomu Nakai , Hirokazu Nagashima , Kenichi Takehana , Kenji Arai , Kazuki Yamauchi , Kazuhide Kurosaki
发明人： Junya Kawamata , Tsutomu Nakai , Hirokazu Nagashima , Kenichi Takehana , Kenji Arai , Kazuki Yamauchi , Kazuhide Kurosaki
IPC分类号： G11C7/00
CPC分类号： G11C29/74 , G11C16/0416 , H01L27/0207 , H01L27/105 , H01L27/115 , H01L27/11519 , H01L27/11526 , H01L27/11531
摘要： A semiconductor device has a plurality of bit lines BL provided in a memory cell area 101, a plurality of word lines WL provided crossing the plurality of bit lines BL, a plurality of diffusion source lines VSL provided along the plurality of word lines WL, a plurality of non-volatile active cells AC storing data, the plurality of non-volatile active cells AC being provided at cross sections of the plurality of bit lines BL and the plurality of word lines WL and being connected to the plurality of bit lines BL, the plurality of word lines WL, and the plurality of diffusion source lines VSL, and a controller simultaneously writes or reads data to and from at least two active cells AC among the plurality of active cells AC, in which the number of the plurality of active cells AC is less than that of the cross sections.
摘要翻译：半导体器件具有设置在存储单元区域101中的多个位线BL，与多个位线BL交叉设置的多个字线WL，沿多个字线WL设置的多个扩散源极线VSL，多个非易失性活动单元AC存储数据，多个非易失性活动单元AC设置在多个位线BL和多个字线WL的横截面处并连接到多个位线BL，多个字线WL和多个扩散源线VSL，以及控制器同时向多个有源单元AC中的至少两个有源单元AC写入或读取数据，其中多个活动单元AC的数量细胞AC小于截面积。

3. 发明授权

US07679968B2 Enhanced erasing operation for non-volatile memory 有权
标题翻译：非易失性存储器的增强擦除操作
公开(公告)号：US07679968B2
公开(公告)日：2010-03-16
申请号：US12129530
申请日：2008-05-29
申请人： Kazuki Yamauchi , Junya Kawamata , Tsutomu Nakai , Kenji Arai , Hirokazu Nagashima , Kenichi Takehana
发明人： Kazuki Yamauchi , Junya Kawamata , Tsutomu Nakai , Kenji Arai , Hirokazu Nagashima , Kenichi Takehana
IPC分类号： G11C11/34
CPC分类号： G11C16/14
摘要： Structures, methods, and systems for enhanced erasing operation for non-volatile memory are disclosed. In one embodiment, a semiconductor device which comprises a memory cell array having a plurality of non-volatile memory cells, a negative voltage generating circuit for applying a negative voltage to a word line of the memory cell array during an erasing operation of the memory cell array, and a positive voltage generating circuit for applying a positive voltage to a well of the memory cell array when the negative voltage reaches a predetermined voltage.
摘要翻译：公开了用于非易失性存储器的增强擦除操作的结构，方法和系统。在一个实施例中，一种包括具有多个非易失性存储单元的存储单元阵列的半导体器件，用于在存储器单元的擦除操作期间向存储单元阵列的字线施加负电压的负电压产生电路阵列和正电压产生电路，用于当负电压达到预定电压时，向存储单元阵列的阱施加正电压。

4. 发明申请

US20080320208A1 SEMICONDUCTOR DEVICE AND METHOD FOR CONTROLLING THEREOF 有权
标题翻译：半导体器件及其控制方法
公开(公告)号：US20080320208A1
公开(公告)日：2008-12-25
申请号：US12139274
申请日：2008-06-13
申请人： Hirokazu Nagashima , Kazuki Yamauchi , Junya Kawamata , Tsutomu Nakai , Kenji Arai , Kenichi Takehana
发明人： Hirokazu Nagashima , Kazuki Yamauchi , Junya Kawamata , Tsutomu Nakai , Kenji Arai , Kenichi Takehana
IPC分类号： G06F12/02 , G06F12/00
CPC分类号： G06F12/0246 , G06F12/0638 , G11C16/20
摘要： A semiconductor device includes a first nonvolatile storage area including a plurality of sectors, a second nonvolatile storage area, a third nonvolatile storage area located in the first nonvolatile storage area, a fourth nonvolatile storage area located in the second nonvolatile storage area, and a control portion selecting one of a first mode and a second mode. In first mode, sectors where the third nonvolatile storage area is not located in the first nonvolatile storage area are used as a main storage area, and the second nonvolatile storage area is used to store a program or data that is read before the first nonvolatile storage area is accessed, the third nonvolatile storage area being used to store control information that controls writing, reading, and erasing of data involved in the first nonvolatile storage area or the second nonvolatile storage area. In the second mode, the first nonvolatile storage area is used as the main storage area, and the fourth nonvolatile storage area is used to store the control information.
摘要翻译：半导体器件包括：第一非易失性存储区域，包括多个扇区;第二非易失性存储区域;位于第一非易失性存储区域中的第三非易失性存储区域;位于第二非易失性存储区域中的第四非易失性存储区域;以及控制选择第一模式和第二模式之一的部分。在第一模式中，将第三非易失性存储区域不位于第一非易失性存储区域中的扇区用作主存储区域，并且第二非易失性存储区域用于存储在第一非易失性存储器之前读取的程序或数据访问第三非易失性存储区域，用于存储控制第一非易失性存储区域或第二非易失性存储区域中涉及的数据的写入，读取和擦除的控制信息。在第二模式中，将第一非易失性存储区域用作主存储区域，并且第四非易失性存储区域用于存储控制信息。

5. 发明授权

US08423705B2 Semiconductor device and method for controlling thereof 有权
标题翻译：半导体装置及其控制方法
公开(公告)号：US08423705B2
公开(公告)日：2013-04-16
申请号：US12139274
申请日：2008-06-13
申请人： Hirokazu Nagashima , Kazuki Yamauchi , Junya Kawamata , Tsutomu Nakai , Kenji Arai , Kenichi Takehana
发明人： Hirokazu Nagashima , Kazuki Yamauchi , Junya Kawamata , Tsutomu Nakai , Kenji Arai , Kenichi Takehana
IPC分类号： G06F12/02
CPC分类号： G06F12/0246 , G06F12/0638 , G11C16/20
摘要： A semiconductor device includes a first nonvolatile storage area including a plurality of sectors, a second nonvolatile storage area, a third nonvolatile storage area located in the first nonvolatile storage area, a fourth nonvolatile storage area located in the second nonvolatile storage area, and a control portion selecting one of a first mode and a second mode. In first mode, sectors where the third nonvolatile storage area is not located in the first nonvolatile storage area are used as a main storage area, and the second nonvolatile storage area is used to store a program or data that is read before the first nonvolatile storage area is accessed, the third nonvolatile storage area being used to store control information that controls writing, reading, and erasing of data involved in the first nonvolatile storage area or the second nonvolatile storage area. In the second mode, the first nonvolatile storage area is used as the main storage area, and the fourth nonvolatile storage area is used to store the control information.
摘要翻译：半导体器件包括：第一非易失性存储区域，包括多个扇区;第二非易失性存储区域;位于第一非易失性存储区域中的第三非易失性存储区域;位于第二非易失性存储区域中的第四非易失性存储区域;以及控制选择第一模式和第二模式之一的部分。在第一模式中，将第三非易失性存储区域不位于第一非易失性存储区域中的扇区用作主存储区域，并且第二非易失性存储区域用于存储在第一非易失性存储器之前读取的程序或数据访问第三非易失性存储区域，用于存储控制第一非易失性存储区域或第二非易失性存储区域中涉及的数据的写入，读取和擦除的控制信息。在第二模式中，将第一非易失性存储区域用作主存储区域，并且第四非易失性存储区域用于存储控制信息。

6. 发明申请

US20080298136A1 ENHANCED ERASING OPERATION FOR NON-VOLATILE MEMORY 有权
标题翻译：增强非易失性存储器的擦除操作
公开(公告)号：US20080298136A1
公开(公告)日：2008-12-04
申请号：US12129530
申请日：2008-05-29
申请人： Kazuki Yamauchi , Junya Kawamata , Tsutomu Nakai , Kenji Arai , Hirokazu Nagashima , Kenichi Takehana
发明人： Kazuki Yamauchi , Junya Kawamata , Tsutomu Nakai , Kenji Arai , Hirokazu Nagashima , Kenichi Takehana
IPC分类号： G11C16/14
CPC分类号： G11C16/14
摘要： Structures, methods, and systems for enhanced erasing operation for non-volatile memory are disclosed. In one embodiment, a semiconductor device which comprises a memory cell array having a plurality of non-volatile memory cells, a negative voltage generating circuit for applying a negative voltage to a word line of the memory cell array during an erasing operation of the memory cell array, and a positive voltage generating circuit for applying a positive voltage to a well of the memory cell array when the negative voltage reaches a predetermined voltage.
摘要翻译：公开了用于非易失性存储器的增强擦除操作的结构，方法和系统。在一个实施例中，一种包括具有多个非易失性存储单元的存储单元阵列的半导体器件，用于在存储器单元的擦除操作期间向存储单元阵列的字线施加负电压的负电压产生电路阵列和正电压产生电路，用于当负电压达到预定电压时，向存储单元阵列的阱施加正电压。

7. 发明授权

US5896319A Current control circuit and non-volatile semiconductor memory device having the same 失效
标题翻译：电流控制电路和具有相同功能的非易失性半导体存储器件
公开(公告)号：US5896319A
公开(公告)日：1999-04-20
申请号：US976575
申请日：1997-11-24
申请人： Kenichi Takehana
发明人： Kenichi Takehana
IPC分类号： G11C16/02 , G11C16/06 , G11C16/16 , G11C16/30 , G11C16/04
CPC分类号： G11C16/16 , G11C16/30
摘要： A current control circuit which controls currents flowing in memory cells in a non-volatile semiconductor memory device includes a circuit which controls the currents flowing in the memory cells in an erase operation so that amounts of the currents fall within a tolerable range.
摘要翻译：控制在非易失性半导体存储器件中的存储单元中流动的电流的电流控制电路包括电路，其在擦除操作中控制在存储单元中流动的电流，使得电流量落入容许范围内。

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