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1. 发明申请

US20060179100A1 System and method for performing floating point store folding 失效
标题翻译：执行浮点存储折叠的系统和方法
公开(公告)号：US20060179100A1
公开(公告)日：2006-08-10
申请号：US11054686
申请日：2005-02-09
申请人： Juergen Haess , Michael Kroener , Dung Nguyen , Lawrence Powell , Eric Schwarz , Son Dao-Trong , Raymond Yeung
发明人： Juergen Haess , Michael Kroener , Dung Nguyen , Lawrence Powell , Eric Schwarz , Son Dao-Trong , Raymond Yeung
IPC分类号： G06F7/38
CPC分类号： G06F9/3826 , G06F9/30014 , G06F9/3824 , G06F9/3838 , G06F9/3885
摘要： A system for performing floating point arithmetic operations including a plurality of stages making up a pipeline, the stages including a first stage and a last stage. The system also includes a register file adapted for receiving a store instruction for input to the pipeline, where the data associated with the store instruction is dependent on a previous operation still in the pipeline. The system further includes a store register adapted for outputting the data associated with the store instruction to memory and a control unit having instructions. The instructions are directed to inputting the store instruction into the pipeline and to providing a path for forwarding the data associated with the store instruction from the last stage in the pipeline to the store register for use by the store instruction if the previous operation immediately precedes the store operation in the pipeline and if there is a data type match between the store instruction and the previous operation. In addition, the instructions are directed to inputting the store instruction into the pipeline and to providing a path for forwarding the data associated with the store instruction from the first stage in the pipeline to the store register for use by the store instruction if the previous operation precedes the store operation by one or more stage in the pipeline and if there is a data type match between the store instruction and the previous operation.
摘要翻译：一种用于执行浮点算术运算的系统，包括构成流水线的多个级，所述级包括第一级和最后级。该系统还包括适于接收用于输入到流水线的存储指令的寄存器文件，其中与存储指令相关联的数据依赖于仍在流水线中的先前操作。该系统还包括适于将与存储指令相关联的数据输出到存储器的存储寄存器和具有指令的控制单元。这些指令旨在将存储指令输入到流水线中，并且提供一个路径，用于将与流水线中的最后一级相关联的存储指令的数据转发到存储寄存器以供存储指令使用，如果先前的操作紧接在存储操作在流水线中，并且存储指令与先前操作之间存在数据类型匹配。此外，该指令旨在将存储指令输入到流水线中，并且提供用于将与流水线中的第一级相关联的存储指令的数据转发到存储寄存器以供存储指令使用的路径，如果先前的操作在存储操作之前在流水线中的一个或多个阶段，以及存储指令和先前操作之间是否存在数据类型匹配。

2. 发明申请

US20060179286A1 System and method for processing limited out-of-order execution of floating point loads 审中-公开
标题翻译：用于处理浮点负载有限次序执行的系统和方法
公开(公告)号：US20060179286A1
公开(公告)日：2006-08-10
申请号：US11054201
申请日：2005-02-09
申请人： Juergen Haess , Michael Kroener , Dung Nguyen , Eric Schwarz , Son Dao-Trong , Raymond Yeung
发明人： Juergen Haess , Michael Kroener , Dung Nguyen , Eric Schwarz , Son Dao-Trong , Raymond Yeung
IPC分类号： G06F9/44
CPC分类号： G06F9/3867 , G06F9/3838
摘要： A system for performing limited out-of order execution of floating point loads. The system includes a plurality of stages making up a pipeline, the stages including an early stage. The system also includes a mechanism for inputting an arithmetic instruction into the pipeline, the arithmetic instruction including a result address. The mechanism also determines if the arithmetic instruction causes a write after write (WAW) condition to occur before writing a result of the arithmetic instruction to the result address. The determining includes comparing the result address to a load address associated with a load instruction subsequent to the arithmetic instruction in the pipeline. The load data associated with the load instruction was written to the load address in the early stage of the pipeline. A WAW condition occurs if the result address is equal to the load address. Writing a result of the arithmetic instruction is suppressed in response to the WAW condition occurring.
摘要翻译：用于执行浮点负载有限次序执行的系统。该系统包括构成管道的多个阶段，这些阶段包括早期阶段。该系统还包括用于将算术指令输入流水线的机构，算术指令包括结果地址。该机制还确定在将算术指令的结果写入结果地址之前，算术指令是否在写入（WAW）条件之后发生写入。确定包括将结果地址与在流水线中的算术指令之后的加载指令相关联的加载地址进行比较。与加载指令相关联的加载数据在管道的早期阶段被写入加载地址。如果结果地址等于加载地址，则会发生WAW条件。响应于发生的WAW状态，写入算术指令的结果被抑制。

3. 发明申请

US20060179097A1 System and method for a floating point unit with feedback prior to normalization and rounding 失效
标题翻译：在归一化和舍入之前具有反馈的浮点单元的系统和方法
公开(公告)号：US20060179097A1
公开(公告)日：2006-08-10
申请号：US11054110
申请日：2005-02-09
申请人： Bruce Fleischer , Juergen Haess , Michael Kroener , Martin Schmookler , Eric Schwarz , Son Dao-Trong
发明人： Bruce Fleischer , Juergen Haess , Michael Kroener , Martin Schmookler , Eric Schwarz , Son Dao-Trong
IPC分类号： G06F7/38
CPC分类号： G06F7/483 , G06F7/499 , G06F7/49936 , G06F7/49947 , G06F7/5443 , G06F2207/382
摘要： A system for performing floating point arithmetic operations including an input register adapted for receiving an operand. The system also includes a mechanism for performing a shift or masking operation in response to determining that the operand is in an un-normalized format. The system also includes instructions for performing single precision incrementing of the operand in response to determining that the operand is single precision, that the operand requires the incrementing based on the results of a previous operation and that the previous operation did not perform the incrementing. The operand was created in the previous operation. The system further includes instructions for performing double precision incrementing of the operand in response to determining that the operand is double precision, that the operand requires the incrementing based on the results of the previous operation and that the previous operation did not perform the incrementing.
摘要翻译：一种用于执行浮点算术运算的系统，包括适于接收操作数的输入寄存器。该系统还包括响应于确定操作数处于非归一化格式而执行移位或掩蔽操作的机制。该系统还包括用于响应于确定操作数是单一精度来执行操作数的单精度递增的指令，操作数需要基于先前操作的结果而增加，并且先前的操作未执行递增。操作数是在以前的操作中创建的。该系统还包括响应于确定操作数是双精度来执行操作数的双精度递增的指令，操作数需要基于先前操作的结果而增加，并且先前的操作不执行递增。

4. 发明申请

US20060179096A1 System and method for a fused multiply-add dataflow with early feedback prior to rounding 审中-公开
标题翻译：在舍入前采用早期反馈的融合乘法加法数据流的系统和方法
公开(公告)号：US20060179096A1
公开(公告)日：2006-08-10
申请号：US11055232
申请日：2005-02-10
申请人： Bruce Fleischer , Juergen Haess , Michael Kroener , Robert Montoye , Martin Schmookler , Eric Schwarz , Son Dao-Trong
发明人： Bruce Fleischer , Juergen Haess , Michael Kroener , Robert Montoye , Martin Schmookler , Eric Schwarz , Son Dao-Trong
IPC分类号： G06F7/38
CPC分类号： G06F7/483 , G06F7/49947 , G06F7/5443
摘要： A system for performing floating point arithmetic operations including an input register adapted for receiving an operand. The system also includes computer instructions for performing single precision incrementing of the operand in response to determining that the operand is single precision, that the operand requires the incrementing based on the results of a previous operation and that the previous operation did not perform the incrementing. The operand was created in the previous operation. The system further includes instructions for performing double precision incrementing of the operand in response to determining that the operand is double precision, that the operand requires the incrementing based on the results of the previous operation and that the previous operation did not perform the incrementing.
摘要翻译：一种用于执行浮点算术运算的系统，包括适于接收操作数的输入寄存器。该系统还包括用于响应于确定操作数是单精度来执行操作数的单精度递增的计算机指令，操作数基于先前操作的结果需要增加，并且先前的操作未执行递增。操作数是在以前的操作中创建的。该系统还包括响应于确定操作数是双精度来执行操作数的双精度递增的指令，操作数需要基于先前操作的结果而增加，并且先前的操作不执行递增。

5. 发明授权

US07730117B2 System and method for a floating point unit with feedback prior to normalization and rounding 失效
标题翻译：在归一化和舍入之前具有反馈的浮点单元的系统和方法
公开(公告)号：US07730117B2
公开(公告)日：2010-06-01
申请号：US11054110
申请日：2005-02-09
申请人： Bruce M. Fleischer , Juergen Haess , Michael Kroener , Martin S. Schmookler , Eric M. Schwarz , Son Dao-Trong
发明人： Bruce M. Fleischer , Juergen Haess , Michael Kroener , Martin S. Schmookler , Eric M. Schwarz , Son Dao-Trong
IPC分类号： G06F7/38 , G06F15/00
CPC分类号： G06F7/483 , G06F7/499 , G06F7/49936 , G06F7/49947 , G06F7/5443 , G06F2207/382
摘要： A system for performing floating point arithmetic operations including an input register adapted for receiving an operand. The system also includes a mechanism for performing a shift or masking operation in response to determining that the operand is in an un-normalized format. The system also includes instructions for performing single precision incrementing of the operand in response to determining that the operand is single precision, that the operand requires the incrementing based on the results of a previous operation and that the previous operation did not perform the incrementing. The operand was created in the previous operation. The system further includes instructions for performing double precision incrementing of the operand in response to determining that the operand is double precision, that the operand requires the incrementing based on the results of the previous operation and that the previous operation did not perform the incrementing.
摘要翻译：一种用于执行浮点算术运算的系统，包括适于接收操作数的输入寄存器。该系统还包括响应于确定操作数处于非归一化格式而执行移位或掩蔽操作的机制。该系统还包括用于响应于确定操作数是单一精度来执行操作数的单精度递增的指令，操作数需要基于先前操作的结果而增加，并且先前的操作未执行递增。操作数是在以前的操作中创建的。该系统还包括响应于确定操作数是双精度来执行操作数的双精度递增的指令，操作数需要基于先前操作的结果而增加，并且先前的操作不执行递增。

6. 发明授权

US07188233B2 System and method for performing floating point store folding 失效
标题翻译：执行浮点存储折叠的系统和方法
公开(公告)号：US07188233B2
公开(公告)日：2007-03-06
申请号：US11054686
申请日：2005-02-09
申请人： Juergen Haess , Michael Kroener , Dung Quoc Nguyen , Lawrence J. Powell, Jr. , Eric M. Schwarz , Son Dao-Trong , Raymond C. Yeung
发明人： Juergen Haess , Michael Kroener , Dung Quoc Nguyen , Lawrence J. Powell, Jr. , Eric M. Schwarz , Son Dao-Trong , Raymond C. Yeung
IPC分类号： G06F9/312
CPC分类号： G06F9/3826 , G06F9/30014 , G06F9/3824 , G06F9/3838 , G06F9/3885
摘要： A system for performing floating point arithmetic operations including a plurality of stages making up a pipeline, the stages including a first stage and a last stage. The system also includes a register file adapted for receiving a store instruction for input to the pipeline, where the data associated with the store instruction is dependent on a previous operation still in the pipeline. The system further includes a store register adapted for outputting the data associated with the store instruction to memory and a control unit having instructions. The instructions are directed to inputting the store instruction into the pipeline and to providing a path for forwarding the data associated with the store instruction from the last stage in the pipeline to the store register for use by the store instruction if the previous operation immediately precedes the store operation in the pipeline and if there is a data type match between the store instruction and the previous operation. In addition, the instructions are directed to inputting the store instruction into the pipeline and to providing a path for forwarding the data associated with the store instruction from the first stage in the pipeline to the store register for use by the store instruction if the previous operation precedes the store operation by one or more stage in the pipeline and if there is a data type match between the store instruction and the previous operation.
摘要翻译：一种用于执行浮点算术运算的系统，包括构成流水线的多个级，所述级包括第一级和最后级。该系统还包括适于接收用于输入到流水线的存储指令的寄存器文件，其中与存储指令相关联的数据依赖于仍在流水线中的先前操作。该系统还包括适于将与存储指令相关联的数据输出到存储器的存储寄存器和具有指令的控制单元。这些指令旨在将存储指令输入到流水线中，并且提供一个路径，用于将与流水线中的最后一级相关联的存储指令的数据转发到存储寄存器以供存储指令使用，如果先前的操作紧接在存储操作在流水线中，并且存储指令与先前操作之间存在数据类型匹配。此外，该指令旨在将存储指令输入到流水线中，并且提供用于将与流水线中的第一级相关联的存储指令的数据转发到存储寄存器以供存储指令使用的路径，如果先前的操作在存储操作之前在流水线中的一个或多个阶段，以及存储指令和先前操作之间是否存在数据类型匹配。

7. 发明授权

US5517438A Fast multiply-add instruction sequence in a pipeline floating-point processor 失效
标题翻译：快速乘法加法指令序列在流水线浮点处理器中
公开(公告)号：US5517438A
公开(公告)日：1996-05-14
申请号：US278522
申请日：1994-07-20
申请人： Son Dao-Trong , Juergen Haas , Rolf Mueller
发明人： Son Dao-Trong , Juergen Haas , Rolf Mueller
IPC分类号： G06F9/38 , G06F7/00 , G06F7/487 , G06F7/508 , G06F7/527 , G06F7/53 , G06F7/533 , G06F7/544 , G06F7/76 , G06F7/38
CPC分类号： G06F7/5443 , G06F2207/3884 , G06F7/483
摘要： A pipeline floating point processor in which the addition pipelining is reorganized so that no wait cycle is needed when the addition uses the result of an immediately foregoing multiplication (fast multiply-add instruction). The reorganization implies the following changes of an existing data flow of the pipeline floating processor: data feed-back via path ND of normalized data from the multiplier M into the aligners AL1 and AL2; shift left one digit feature on both sides of the data path for taking account of a possible leading zero digit of the product, and special zeroing of potential guard digits by Z1 and Z2; exponent build by 9 bits for overflow and underflow recognition, and due to an underflow the exponent result, is reset to zero on the fly by a true zero unit (T/C).
摘要翻译：一种流水线浮点处理器，其中重新组合加法流水线，使得当加法使用紧前相关乘法的结果（快速乘法指令）时，不需要等待周期。重组意味着流水线浮动处理器的现有数据流的以下改变：经由来自乘法器M的归一化数据的路径ND的数据反馈到对准器AL1和AL2; 考虑到产品的可能的前导零位，并且通过Z1和Z2对潜在的保护数字进行特殊归零，在数据路径的两侧左移一位数字特征; 指数由9位构成，用于溢出和下溢识别，并且由于下溢，指数结果将通过真零单位（T / C）在运行中复位为零。

8. 发明授权

US5506800A Self-checking complementary adder unit 失效
标题翻译：自检互补加法器单元
公开(公告)号：US5506800A
公开(公告)日：1996-04-09
申请号：US215997
申请日：1994-03-22
申请人： Son Dao-Trong
发明人： Son Dao-Trong
IPC分类号： G06F7/499 , G06F7/492 , G06F7/493 , G06F7/50 , G06F7/507 , G06F7/508 , G06F11/16 , G06F11/00
CPC分类号： G06F11/1608 , G06F11/10 , G06F7/507
摘要： A self-checking complementary adder unit used for high performance subtractions comprises two carry select adders (30 and 36) each of which consists of a pair of byte or digit organized ripple carry adders (31, 32 and 37, 38) generating in parallel virtual sums from true and complemented operands based on the assumption that the carry-in signal is 1 or 0. Depending on byte or digit carry signals generated by carry look ahead circuits (33, 39), partial sums are selected from the virtual sums to form a real sum. The outputs of both carry select adders are connected to a multiplexer (42) which is controlled by the high order carry-out signal from one of the carry look ahead circuits representing the sign of a real sum. The multiplexer selects one of the real sums as the result of a subtraction. A sum checker compares cross-wise the parity bits of the virtual sums from both carry select adders and also compares the related carry-out signals from both the ripple carry adders and carry look ahead circuits. The compare results are combined by a logic circuit to generate a result check signal.
摘要翻译：用于高性能减法的自检互补加法器单元包括两个进位选择加法器（30和36），每个进位选择加法器由一对字符或数字组织波纹携带加法器（31,32和37,38）组成，并行虚拟基于进位信号为1或0的假设，从真实和补充的操作数得到的总和。根据由携带前瞻电路（33,39）产生的字节或数字进位信号，从虚拟和中选择部分和一个真正的总和两个进位选择加法器的输出连接到多路复用器（42），该多路复用器（42）由表示真实和的符号的进位查看电路之一的高阶进位输出信号控制。多路复用器选择一个实数和作为减法的结果。和检查器将来自两个进位选择加法器的虚拟和的奇偶校验位进行交叉比较，并且还比较来自波纹携带加法器的相关进位输出信号并携带预先电路。比较结果由逻辑电路组合以产生结果检查信号。

9. 发明授权

US5070471A High speed multiplier which divides multiplying factor into parts and adds partial end products 失效
标题翻译：高倍数乘法器将乘法因子分为零件和部分最终产品
公开(公告)号：US5070471A
公开(公告)日：1991-12-03
申请号：US478283
申请日：1990-02-09
申请人： Son Dao-Trong , Klaus J. Getzlaff , Klaus Helwig
发明人： Son Dao-Trong , Klaus J. Getzlaff , Klaus Helwig
IPC分类号： G06F7/533 , G06F7/52 , G06F7/53
CPC分类号： G06F7/5324 , G06F7/5338
摘要： A multiplier for multiplying two binary operands is presented which comprises an encoding unit, a multiplying unit composed of two multiplying arrays, and a logic unit. The encoding unit to which the second operand is applied generates factors following the Booth algorithm. The two multiplying arrays are respectively applied with the first operand as well as with factors belonging to the higher significance digits or the lower significance digits, respectively, of the second operand. In both multiplying arrays the multiplication of the factors with the first operand into a respective partial end product is simultaneously performed. Both partial end products are applied to the logic unit which generates therefrom the end product in accordance with the algorithm used at the beginning.
摘要翻译：提出了用于乘以两个二进制操作数的乘法器，其包括编码单元，由两个乘法阵列组成的乘法单元和逻辑单元。应用第二个操作数的编码单元生成遵循布斯算法的因子。两个相乘阵列分别与第一操作数一起使用，以及分别属于第二操作数的较高有效数字或较低有效数字的因子。在两个乘法阵列中，同时执行将因子与第一操作数相乘到相应的部分最终乘积中。两个部分终端产品都被应用于逻辑单元，该逻辑单元根据开始时使用的算法生成最终产品。

10. 发明授权

US5542033A Correction and modification of microprocessor chip operations 失效
标题翻译：微处理器芯片操作的修正和修改
公开(公告)号：US5542033A
公开(公告)日：1996-07-30
申请号：US310464
申请日：1994-09-22
申请人： Son Dao-Trong , Juergen Haas , Rolf Mueller , Guenter Gerwig
发明人： Son Dao-Trong , Juergen Haas , Rolf Mueller , Guenter Gerwig
IPC分类号： G06F9/30 , G06F9/318 , G06F9/32 , G06F9/38 , G06F9/445 , G06F11/267 , G06F11/34
CPC分类号： G06F9/30145 , G06F11/2236 , G06F8/66 , G06F9/30094 , G06F9/30189 , G06F9/328 , G06F9/3836 , G06F9/3857 , G06F9/3861 , G06F9/3867
摘要： A correction of microprocessor chip design errors is achieved by identifying selected sets of instructions and/or selected sets of instruction sequences in an erroneous control flow of the microprocessor and/or by identifying selected sets of interface control and status signals. A match selectively initiates a corrective action by interfering with the instruction flow in the microprocessor chip or by requesting external control from an associated processor unit. Alternatively, a match is used for a programmable modification of interface control and status signals to adapt the chip to changes of its environment without redesign.
摘要翻译：通过在微处理器的错误控制流程中识别所选择的指令集和/或选定的指令序列集合和/或通过识别所选择的接口控制和状态信号集来实现微处理器芯片设计错误的校正。匹配通过干扰微处理器芯片中的指令流或通过从相关联的处理器单元请求外部控制来选择性地启动校正动作。或者，匹配用于接口控制和状态信号的可编程修改，以便在不重新设计的情况下使芯片适应其环境的变化。

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