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1. 发明授权

CN111221497B 一种量子元胞自动机十进制全加器有权
公开(公告)号：CN111221497B
公开(公告)日：2022-04-22
申请号：CN202010026412.8
申请日：2020-01-10
申请人：宁波大学
发明人：储著飞 , 李泽强 , 夏银水 , 王伦耀
IPC分类号： G06F7/492 , G06F7/575 , G06N10/20 , G06N10/40
摘要：本发明公开了一种量子元胞自动机十进制全加器，在不改变电路逻辑功能的前提下，通过结合表达能力更强的异或逻辑运算符以及先进的全加器进位结构，来优化QCA十进制全加器所需的逻辑结点数和逻辑深度，从而以此优化一位以及多位QCA十进制全加器电路的面积和延迟。相比于传统性能最优的全加器，本发明提出的量子元胞自动机十进制全加器性能优良，在延迟和面积方面提升明显，尤其在量子元胞自动机8位十进制全加器中优化效果更加明显，延迟和面积的提升分别为27.6%和53.4%。本发明极大降低了电路成本，同时丰富了在电路设计中的电路研究方法。本发明为基于多数逻辑和异或逻辑的算术电路设计提供了新的研究思路，对电路设计的发展有较强的实践意义。

2. 发明公开

CN111221497A 一种量子元胞自动机十进制全加器有权
公开(公告)号：CN111221497A
公开(公告)日：2020-06-02
申请号：CN202010026412.8
申请日：2020-01-10
申请人：宁波大学
发明人：储著飞 , 李泽强 , 夏银水 , 王伦耀
IPC分类号： G06F7/492 , G06F7/575 , G06N10/00
摘要：本发明公开了一种量子元胞自动机十进制全加器，在不改变电路逻辑功能的前提下，通过结合表达能力更强的异或逻辑运算符以及先进的全加器进位结构，来优化QCA十进制全加器所需的逻辑结点数和逻辑深度，从而以此优化一位以及多位QCA十进制全加器电路的面积和延迟。相比于传统性能最优的全加器，本发明提出的量子元胞自动机十进制全加器性能优良，在延迟和面积方面提升明显，尤其在量子元胞自动机8位十进制全加器中优化效果更加明显，延迟和面积的提升分别为27.6%和53.4%。本发明极大降低了电路成本，同时丰富了在电路设计中的电路研究方法。本发明为基于多数逻辑和异或逻辑的算术电路设计提供了新的研究思路，对电路设计的发展有较强的实践意义。

3. 发明公开

CN110377267A 一种基于概率计算集中序列的有符号数的加/减法器失效
公开(公告)号：CN110377267A
公开(公告)日：2019-10-25
申请号：CN201910678453.2
申请日：2019-07-25
申请人：中北大学
发明人：梁涛
IPC分类号： G06F7/492
摘要：一种基于概率计算集中序列的有符号数的加/减法器,属于集成电路领域，具体涉及一种集中序列的加/减法器。如何提供一种面向基于集中序列的有符号数的加/减法器的问题。主要用于对两个n+1位二进制有符号数进行加法或减法运算，其中，一个n+1位二进制有符号数由一位符号位SA和n位二进制数A所对应的数字位构成；另一个n+1位二进制有符号数由一位符号位SB和n位二进制数B所对应的数字位构成；符号确定模块根据接收的符号位SA和SB，获得运算方式，并根据确定的运算方式对两个n+1位二进制有符号数进行加法或减法运算。本发明主要适用于神经网络计算等既包含大量乘法运算也包含大量累加运算的场合。

4. 发明授权

CN110377267B 一种基于概率计算集中序列的有符号数的加/减法器失效
公开(公告)号：CN110377267B
公开(公告)日：2021-03-16
申请号：CN201910678453.2
申请日：2019-07-25
申请人：中北大学
发明人：梁涛
IPC分类号： G06F7/492
摘要：一种基于概率计算集中序列的有符号数的加/减法器,属于集成电路领域，具体涉及一种集中序列的加/减法器。如何提供一种面向基于集中序列的有符号数的加/减法器的问题。主要用于对两个n+1位二进制有符号数进行加法或减法运算，其中，一个n+1位二进制有符号数由一位符号位SA和n位二进制数A所对应的数字位构成；另一个n+1位二进制有符号数由一位符号位SB和n位二进制数B所对应的数字位构成；符号确定模块根据接收的符号位SA和SB，获得运算方式，并根据确定的运算方式对两个n+1位二进制有符号数进行加法或减法运算。本发明主要适用于神经网络计算等既包含大量乘法运算也包含大量累加运算的场合。

5. 发明专利

GB1533028A ARITHMETIC UNITS 未知
公开(公告)号：GB1533028A
公开(公告)日：1978-11-22
申请号：GB1838676
申请日：1976-05-05
申请人： IBM
IPC分类号： G06F7/00 , G06F7/38 , G06F7/492 , G06F7/494 , G06F7/508 , G06F11/10 , H03M13/00
摘要： 1533028 Arithmetic unit parity checking INTERNATIONAL BUSINESS MACHINES CORP 5 May 1976 [23 June 1975] 18386/76 Heading G4A An arithmetic unit 20 including output modifying circuitry 23 has a parity generator 24-27 for generating one or more parity check bits from the unmodified output of the arithmetic unit and assembling the generated parity bit(s) with the output of the modifying circuitry, whereby the parity checked output is available earlier in time than would be the case if the parity generator used the modified output. The arithmetic unit described is of the type disclosed in Specification 1,512,476 which is capable of operating on operands in zoned BCD or packed BCD format as well as binary. As well as the add six (for decimal addition) and complement (for subtraction) operations performed by an A or B operand modifier 21, 22 the zone and/or sign codes of the input operands are also modified so that carries can propagate across the sign and zone fields for BCD operations. The output corrector 23 restores the original zoned or packed BCD format. Byte parity generators.-It is shown that for each BCD digit the output of the adder has the same parity as the modified output except for digits coded 1010 and 1011 (hexadecimal A and B). The parity of the sign and zone fields (0000 or 1111 are possible adder outputs) of the unmodified output is the same as the parity of the modified (original) zone fields (1111) and positive sign fields (1111 for zoned and 1100 for packed format). The unmodified and modified sign fields have opposite parities since the negative sign is coded 1101 for both BCD formats. The parity generator/predictor described, Figs. 5- 11 (not shown) comprises AND/OR networks which invert the parity of each output byte for each of its 4-bit groups coded as hexadecimal A or B or as a negative sign. Modifications.-A second adder/subtractor operating on complement operands A, B may be provided to produce a complementary result for comparison with the true result in EXOR circuits to check that no error is introduced by the adder/subtraotors or input modifiers, Fig. 12 (not shown).

6. 发明专利

FR2315724A1 未知
公开(公告)号：FR2315724A1
公开(公告)日：1977-01-21
申请号：FR7614189
申请日：1976-05-06
申请人： IBM
发明人： GOODING DAVID N , SHIM EVERETT M
IPC分类号： G06F7/00 , G06F7/38 , G06F7/492 , G06F7/494 , G06F7/508 , G06F11/10 , H03M13/00
摘要： A digital arithmetic unit employing a binary adder for adding and subtracting multidigit binary coded decimal numbers in either zoned format or packed format and having an improved method of generating parity check bits for the resultant data bytes produced by the arithmetic unit. When using a binary adder for adding or subtracting binary coded decimal numbers, it is necessary to correct some of the data appearing at the output of the binary adder in order to obtain the correct results. The parity check bit generating circuitry of the present invention, however, works on the uncorrected data appearing at the output of the adder, but nevertheless produces the proper parity check bits for the corrected data which represents the final output for the arithmetic unit. This reduces the amount of time delay which would otherwise be caused by generating the parity check bits in a conventional manner.

7. 发明专利

SU1658143A1 ONE-DIGIT DECIMAL ADDER IN "5421" CODE 未知
公开(公告)号：SU1658143A1
公开(公告)日：1991-06-23
申请号：SU4434077
申请日：1988-02-26
申请人： TIMOSHKIN ANDREJ , TELENKOV VYACHESLAV V
发明人： TIMOSHKIN ANDREJ I , TELENKOV VYACHESLAV V
IPC分类号： G06F7/492 , G06F7/50

8. 发明专利

AU2011213795A1 Efficient cache reuse through application determined scheduling 未知
公开(公告)号：AU2011213795A1
公开(公告)日：2013-03-07
申请号：AU2011213795
申请日：2011-08-19
申请人： CANON KK
发明人： STEFANOV EKATERINA , MONAGHAN DAVID ROBERT JAMES , MORRISON PAUL WILLIAM
IPC分类号： G06F7/492
摘要： EFFICIENT CACHE REUSE THROUGH USER-LEVEL SCHEDULING 5 Disclosed is a method of determining a thread from a plurality of threads to execute a task in a multi-processor computer system. The plurality of threads is grouped into at least one subset (CG) associated with a cache memory of the computer system. The task (T) has a type determined by a set of instructions. The method obtains an execution history (440) of the subset of plurality of threads and determines (710) a weighting (Wi,Wd) for each of the 10 set of instructions and the set of data, said weightings depending on the type of the task (715;890-894). A suitability of the subset (CG) of the threads to execute the task based on the execution history and the determined weightings, is then determined. Subject to the determined suitability of the subset of threads, the method determining a thread from the subset of threads to execute the task using content of the cache memory associated with the 15 subset of threads. 5531549_1 P000399_specilodge

9. 发明专利

FR2315724B1 未知
公开(公告)号：FR2315724B1
公开(公告)日：1979-03-23
申请号：FR7614189
申请日：1976-05-06
申请人： IBM
IPC分类号： G06F7/00 , G06F7/38 , G06F7/492 , G06F7/494 , G06F7/508 , G06F11/10 , H03M13/00
摘要： A digital arithmetic unit employing a binary adder for adding and subtracting multidigit binary coded decimal numbers in either zoned format or packed format and having an improved method of generating parity check bits for the resultant data bytes produced by the arithmetic unit. When using a binary adder for adding or subtracting binary coded decimal numbers, it is necessary to correct some of the data appearing at the output of the binary adder in order to obtain the correct results. The parity check bit generating circuitry of the present invention, however, works on the uncorrected data appearing at the output of the adder, but nevertheless produces the proper parity check bits for the corrected data which represents the final output for the arithmetic unit. This reduces the amount of time delay which would otherwise be caused by generating the parity check bits in a conventional manner.

10. 实用新型

JPH0255328U 失效
公开(公告)号：JPH0255328U
公开(公告)日：1990-04-20
申请号：JP13409688
申请日：1988-10-14
IPC分类号： G06F11/10 , G06F7/492 , G06F7/494 , G06F7/50 , G06F7/508

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