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1. 发明授权

US07061782B2 Content addressable memory (CAM) for data lookups in a data processing system 失效
标题翻译：内容可寻址存储器（CAM），用于数据处理系统中的数据查找
公开(公告)号：US07061782B2
公开(公告)日：2006-06-13
申请号：US09962052
申请日：2001-09-24
申请人： Klaus Helwig
发明人： Klaus Helwig
IPC分类号： G11C15/00
CPC分类号： G11C15/04
摘要： Power consumption is reduced in a content addressable memory of a data processing system or a data processor. The content addressable memory includes at least a first single bit storage (101; 301), a word line (WL), at least one bit write line (BLWT, BLWC) and a hit/miss line (H/M), and at least a first single bit compare circuit (201; 320), the first single bit storage including at least a first output (A; A0) and the first single bit compare circuit including at least a first compare bit input (BLCT; CB 0) and two field effect transistors (113, 114; 312, 313). In order to reduce the power consumption, the first output (A; A0) of the single bit storage (101; 301) is applied to the gate of only one, a first field effect transistor (114; 312) of the two field effect transistors (113, 114; 312, 313). For an additional reduction of the power consumption, two single bit storages (101, 301) are connected to a shared compare circuit (319). In case of a mismatch, only one out of four compare nodes (C0, C1, C2, C3) of the shared compare circuit is switched high, i.e. changes its potential.
摘要翻译：数据处理系统或数据处理器的内容可寻址存储器中的功耗降低。内容可寻址存储器至少包括第一单个位存储器（101; 301），字线（WL），至少一个位写入线（BLWT，BLWC）和命中/未命中线（H / M）至少第一单比特比较电路（201; 320），所述第一单比特存储器至少包括第一输出（A; A 0）和所述第一单比特比较电路至少包括第一比较比特输入（BLCT; CB 0 ）和两个场效应晶体管（113,114; 312,313）。为了降低功耗，单位存储器（101; 301）的第一输出（A; A 0）被施加到仅一个的栅极，两个场的第一场效应晶体管（114; 312）效应晶体管（113,114; 312,313）。为了进一步降低功耗，两个单位存储器（101,301）连接到共享比较电路（319）。在不匹配的情况下，共享比较电路的四个比较节点（C 0，C 1，C 2，C 3）中只有一个被切换为高电平，即改变其电位。

2. 发明授权

US06295232B2 Dual-to-single-rail converter for the read out of static storage arrays 失效
标题翻译：用于读出静态存储阵列的双对单轨转换器
公开(公告)号：US06295232B2
公开(公告)日：2001-09-25
申请号：US09733328
申请日：2000-12-08
申请人： Juergen Pille , Klaus Helwig , Dieter Wendel
发明人： Juergen Pille , Klaus Helwig , Dieter Wendel
IPC分类号： G11C700
CPC分类号： G11C11/419 , G11C7/067
摘要： A read circuit for semiconductor storage cells (10, 50) including dual read bitlines (23, 24, 51, 52) driven by the cell to full ‘zero’ signals and ‘weak one’ signals comprises a read head circuit (53) which includes an inverter (56) in one of the bitlines (52). The inverter serves to turn a ‘weak one’ signal to a full ‘zero’ signal. A bit select circuit is integrated into the read head circuit (53) and connects the output of the inverter and the other one of the bitlines (51) through bit select switches (57, 58) to the single line output (XT1) of the read head circuit (53).
摘要翻译：包括由单元驱动到完全“零”信号和“弱”信号的双重读取位线（23,24,51,52）的半导体存储单元（10,50）的读取电路包括一个读取头电路（53）在位线（52）之一中包括逆变器（56）。逆变器用于将“弱”信号转换为完全“零”信号。一个位选择电路被集成到读取头电路53中，并通过位选择开关57,58将反相器的输出和位线51中的另一个通过位线选择开关57连接到单线输出（XT1）读头电路（53）。

3. 发明授权

US5870324A Contents-addressable memory 失效
标题翻译：内容可寻址内存
公开(公告)号：US5870324A
公开(公告)日：1999-02-09
申请号：US750765
申请日：1997-03-07
申请人： Klaus Helwig , Christoph Wandel
发明人： Klaus Helwig , Christoph Wandel
IPC分类号： G11C8/12 , G11C15/04 , G11C7/00
CPC分类号： G11C8/12 , G11C15/04
摘要： The invention relates to a contents-addressable memory (CAM) with multiple logical-memory arrays Di. The logical-memory arrays Di are distributed logically in multiple blocks Dij. The blocks Dij are physically arranged to memory arrays Di' and integrated on the chip surface. Each memory array Di' hereby has one block Dij of the logical memory arrays Di. In this way, parasitic capacities of the CAM may be minimized.
摘要翻译： PCT No.PCT / EP95 / 01460 Sec。 371日期1997年3月7日 102（e）1997年3月7日PCT PCT。1995年4月18日PCT公布。 WO96 / 33499 PCT公开日期1996年10月24日本发明涉及具有多个逻辑存储器阵列Di的内容寻址存储器（CAM）。逻辑存储器阵列Di在逻辑上分布在多个块Dij中。块Dij物理地布置到存储器阵列Di'并且集成在芯片表面上。每个存储器阵列Di'具有逻辑存储器阵列Di的一个块Dij。以这种方式，CAM的寄生电容可以被最小化。

4. 发明授权

US5070471A High speed multiplier which divides multiplying factor into parts and adds partial end products 失效
标题翻译：高倍数乘法器将乘法因子分为零件和部分最终产品
公开(公告)号：US5070471A
公开(公告)日：1991-12-03
申请号：US478283
申请日：1990-02-09
申请人： Son Dao-Trong , Klaus J. Getzlaff , Klaus Helwig
发明人： Son Dao-Trong , Klaus J. Getzlaff , Klaus Helwig
IPC分类号： G06F7/533 , G06F7/52 , G06F7/53
CPC分类号： G06F7/5324 , G06F7/5338
摘要： A multiplier for multiplying two binary operands is presented which comprises an encoding unit, a multiplying unit composed of two multiplying arrays, and a logic unit. The encoding unit to which the second operand is applied generates factors following the Booth algorithm. The two multiplying arrays are respectively applied with the first operand as well as with factors belonging to the higher significance digits or the lower significance digits, respectively, of the second operand. In both multiplying arrays the multiplication of the factors with the first operand into a respective partial end product is simultaneously performed. Both partial end products are applied to the logic unit which generates therefrom the end product in accordance with the algorithm used at the beginning.
摘要翻译：提出了用于乘以两个二进制操作数的乘法器，其包括编码单元，由两个乘法阵列组成的乘法单元和逻辑单元。应用第二个操作数的编码单元生成遵循布斯算法的因子。两个相乘阵列分别与第一操作数一起使用，以及分别属于第二操作数的较高有效数字或较低有效数字的因子。在两个乘法阵列中，同时执行将因子与第一操作数相乘到相应的部分最终乘积中。两个部分终端产品都被应用于逻辑单元，该逻辑单元根据开始时使用的算法生成最终产品。

5. 发明授权

US06353548B2 Method and data processing system for data lookups 失效
标题翻译：用于数据查找的方法和数据处理系统
公开(公告)号：US06353548B2
公开(公告)日：2002-03-05
申请号：US09746983
申请日：2000-12-22
申请人： Klaus Helwig , Hans-Werner Tast , Friedrich-Christian Wernicke
发明人： Klaus Helwig , Hans-Werner Tast , Friedrich-Christian Wernicke
IPC分类号： G11C1500
CPC分类号： G11C7/1093 , G11C7/1006 , G11C7/1072 , G11C7/1078 , G11C15/00
摘要： In order to provide a more efficient method and system for data lookups, it is proposed to provide the known CAM (100) with an additional comparator (301). The comparator (301) does not comprise a memory circuit and therefore allows a faster comparison of input data (D0 to D31) with compare data (C0 to C31) than the known compare circuit (106). In addition, it is proposed to temporarily inhibit forwarding of the output signal of the specific CAM circuit into which the input data (D0 to D31) are written, in order to avoid forwarding of a wrong match signal to the data processing system.
摘要翻译：为了提供用于数据查找的更有效的方法和系统，提出向已知的CAM（100）提供附加的比较器（301）。比较器（301）不包括存储器电路，因此允许比已知比较电路（106）更快地比较输入数据（D0至D31）与比较数据（C0至C31）。此外，建议暂时禁止写入输入数据（D0〜D31）的特定CAM电路的输出信号的转发，以避免将错误的匹配信号转发到数据处理系统。

6. 发明授权

US5363321A Digital circuit for calculating a logarithm of a number 失效
标题翻译：用于计算数字对数的数字电路
公开(公告)号：US5363321A
公开(公告)日：1994-11-08
申请号：US69954
申请日：1993-05-28
申请人： Son Dao Trong , Klaus Helwig , Markus Loch
发明人： Son Dao Trong , Klaus Helwig , Markus Loch
IPC分类号： G06F7/556 , G06F7/00
CPC分类号： G06F7/556
摘要： A digital circuit computes the logarithm of a number. The circuit makes the computation by first determining a multiplicity of factors f.sub.i from a predetermined set of factors such that the product of the multiplicity of factors f.sub.i and the number equals the base of the logarithm. A memory stores the logarithms of all the numbers in the predetermined set. The circuit then looks-up and sums the logarithms of the multiplicity of factors f.sub.i, and then subtracts the sum from one to yield the logarithm of the number.
摘要翻译：数字电路计算一个数字的对数。该电路通过首先从预定因子集合确定多项因子fi使得计算，使得多项因子f i和数量的乘积等于对数的基数。存储器存储预定集合中所有数字的对数。然后，电路查找并求和多项因子fi的对数，然后从一个减去总和以产生数字的对数。

7. 发明授权

US4811298A Decoding circuit arrangement for redundant semiconductor storage systems 失效
标题翻译：用于冗余半导体存储系统的解码电路装置
公开(公告)号：US4811298A
公开(公告)日：1989-03-07
申请号：US87489
申请日：1987-08-20
申请人： Klaus Helwig , Wolfdieter Lohlein , Minh H. Tong
发明人： Klaus Helwig , Wolfdieter Lohlein , Minh H. Tong
IPC分类号： G11C11/408 , G11C11/401 , G11C29/00 , G11C29/04 , G11C13/00
CPC分类号： G11C29/83 , G11C29/84
摘要： A decoding process and a decoding circuit arrangement for a redundant semiconductor memory is described, wherein the advantages of parallelly selecting non-defective word lines and redundant word lines at a low level are utilized for the writing as well as for the reading current in such a manner that high speed reading and writing is not affected. This is achieved in that the decoder for the redundant word lines consists of a comparator circuit and fuse-controlled switches, and that the input addresses are applied to a conventional address decoder as well as to the comparator circuit. The output of the comparator circuit is directly connected to the input of a first driver circuit for the redundant word line, and furthermore to an OR circuit which is also controlled by a read/write control circuit, and which is connected to the decoder and to a clamp circuit that is directly connected to the input of a second word line driver circuit, and continuously maintains the potential following a deselect signal applied on that level, which requires a minimum of power.
摘要翻译：描述了用于冗余半导体存储器的解码处理和解码电路装置，其中以低电平并行选择无缺陷字线和冗余字线的优点用于写入以及读取电流高速读写方式不受影响。这是因为用于冗余字线的解码器由比较器电路和熔丝控制开关组成，并且输入地址被施加到常规地址解码器以及比较器电路。比较器电路的输出直接连接到用于冗余字线的第一驱动器电路的输入，并且还连接到也由读/写控制电路控制并且连接到解码器的OR电路，钳位电路，其直接连接到第二字线驱动器电路的输入，并且连续地保持该电平上施加的取消选择信号的电位，其需要最小功率。

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