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1. 发明申请

US20060179097A1 System and method for a floating point unit with feedback prior to normalization and rounding 失效
标题翻译：在归一化和舍入之前具有反馈的浮点单元的系统和方法
公开(公告)号：US20060179097A1
公开(公告)日：2006-08-10
申请号：US11054110
申请日：2005-02-09
申请人： Bruce Fleischer , Juergen Haess , Michael Kroener , Martin Schmookler , Eric Schwarz , Son Dao-Trong
发明人： Bruce Fleischer , Juergen Haess , Michael Kroener , Martin Schmookler , Eric Schwarz , Son Dao-Trong
IPC分类号： G06F7/38
CPC分类号： G06F7/483 , G06F7/499 , G06F7/49936 , G06F7/49947 , G06F7/5443 , G06F2207/382
摘要： A system for performing floating point arithmetic operations including an input register adapted for receiving an operand. The system also includes a mechanism for performing a shift or masking operation in response to determining that the operand is in an un-normalized format. The system also includes instructions for performing single precision incrementing of the operand in response to determining that the operand is single precision, that the operand requires the incrementing based on the results of a previous operation and that the previous operation did not perform the incrementing. The operand was created in the previous operation. The system further includes instructions for performing double precision incrementing of the operand in response to determining that the operand is double precision, that the operand requires the incrementing based on the results of the previous operation and that the previous operation did not perform the incrementing.
摘要翻译：一种用于执行浮点算术运算的系统，包括适于接收操作数的输入寄存器。该系统还包括响应于确定操作数处于非归一化格式而执行移位或掩蔽操作的机制。该系统还包括用于响应于确定操作数是单一精度来执行操作数的单精度递增的指令，操作数需要基于先前操作的结果而增加，并且先前的操作未执行递增。操作数是在以前的操作中创建的。该系统还包括响应于确定操作数是双精度来执行操作数的双精度递增的指令，操作数需要基于先前操作的结果而增加，并且先前的操作不执行递增。

2. 发明申请

US20060179096A1 System and method for a fused multiply-add dataflow with early feedback prior to rounding 审中-公开
标题翻译：在舍入前采用早期反馈的融合乘法加法数据流的系统和方法
公开(公告)号：US20060179096A1
公开(公告)日：2006-08-10
申请号：US11055232
申请日：2005-02-10
申请人： Bruce Fleischer , Juergen Haess , Michael Kroener , Robert Montoye , Martin Schmookler , Eric Schwarz , Son Dao-Trong
发明人： Bruce Fleischer , Juergen Haess , Michael Kroener , Robert Montoye , Martin Schmookler , Eric Schwarz , Son Dao-Trong
IPC分类号： G06F7/38
CPC分类号： G06F7/483 , G06F7/49947 , G06F7/5443
摘要： A system for performing floating point arithmetic operations including an input register adapted for receiving an operand. The system also includes computer instructions for performing single precision incrementing of the operand in response to determining that the operand is single precision, that the operand requires the incrementing based on the results of a previous operation and that the previous operation did not perform the incrementing. The operand was created in the previous operation. The system further includes instructions for performing double precision incrementing of the operand in response to determining that the operand is double precision, that the operand requires the incrementing based on the results of the previous operation and that the previous operation did not perform the incrementing.
摘要翻译：一种用于执行浮点算术运算的系统，包括适于接收操作数的输入寄存器。该系统还包括用于响应于确定操作数是单精度来执行操作数的单精度递增的计算机指令，操作数基于先前操作的结果需要增加，并且先前的操作未执行递增。操作数是在以前的操作中创建的。该系统还包括响应于确定操作数是双精度来执行操作数的双精度递增的指令，操作数需要基于先前操作的结果而增加，并且先前的操作不执行递增。

3. 发明申请

US20060184603A1 Zero detect in partial sums while adding 审中-公开
标题翻译：零点检测部分和，而添加
公开(公告)号：US20060184603A1
公开(公告)日：2006-08-17
申请号：US11056036
申请日：2005-02-11
申请人： Son Trong , Mark Erle , Bruce Fleischer , Juergen Haess , Michael Kelly , Klaus Kroener , Martin Schmookler , Eric Schwarz
发明人： Son Trong , Mark Erle , Bruce Fleischer , Juergen Haess , Michael Kelly , Klaus Kroener , Martin Schmookler , Eric Schwarz
IPC分类号： G06F7/52
CPC分类号： G06F7/53 , G06F7/74
摘要： The present invention relates to a method and circuit for performing multiply-operations in an arithmetic unit of a computer processor. In a multiplier thereof, zero detection of the resulting product bit string (22) is needed for a proper setting of condition code and overflow status information. Zero detection according to prior art decreases the calculation speed in the multiplier. In order to provide a method and respective electronic circuit, wherein the zero detection is earlier completed, it is proposed to use a leading zero anticipation (LZA) hardware—i.e., an LZA circuit (40), which exists usually anyway in floating point processor adders for calculating the number of leading zeros for operand normalization purposes—for performing a zero detection of the product by aid of the partial results (16, 17) emerging at the output of the Wallace tree of the multiplier. MSB-most and LSB-most margin bits (24, 26) of the partial (16, 17) results which cannot be processed by the LZA circuit (40), are read directly from the final product bit string (22).
摘要翻译：本发明涉及一种用于在计算机处理器的运算单元中执行乘法运算的方法和电路。在其乘数中，为了适当地设置条件代码和溢出状态信息，需要对所得到的产品位串（22）进行零检测。根据现有技术的零检测降低了乘法器中的计算速度。为了提供一种方法和各自的电子电路，其中零检测较早完成，提出使用前导零预期（LZA）硬件即LZA电路（40），其通常在浮点处理器用于计算操作数归一化目的的前导零数量的加法器，用于通过在乘法器的华莱士树的输出处出现的部分结果（16,17）执行零检测。从最终产品位串（22）直接读取不能由LZA电路（40）处理的部分（16,17）结果的MSB最大和LSB最大的边缘位（24,26）。

4. 发明申请

US20060179090A1 System and method for converting binary to decimal 审中-公开
标题翻译：将二进制转换为十进制的系统和方法
公开(公告)号：US20060179090A1
公开(公告)日：2006-08-10
申请号：US11054232
申请日：2005-02-09
申请人： Steven Carlough , Bruce Fleischer , Wen Li , Eric Schwarz
发明人： Steven Carlough , Bruce Fleischer , Wen Li , Eric Schwarz
IPC分类号： G06F7/00
CPC分类号： H03M7/12
摘要： A method for converting from binary to decimal. The method includes receiving a binary number, the binary number including one or more sets of bits. An accumulated sum is set to zero. The accumulated sum is in a binary coded decimal (BCD) format. The following loop is repeated for each set of bits in the binary number in order from the set of bits containing the most significant bit of the binary number to the set of bits containing the least significant bit of the binary number: the accumulated sum is converted into a 5,1 code format resulting in an interim sum. The loop also includes repeating for each next bit in the set in order from the most significant bit to the least significant bit in the set: doubling the interim sum; and replacing the least significant bit of the interim sum with the next bit. The last step in the loop includes converting the interim sum into the BCD format and storing the results of the converting in the accumulated sum. Once all of the sets of bits in the binary number have been processed through the loop, the accumulated sum is output as the final result.
摘要翻译：一种从二进制转换为十进制的方法。该方法包括接收二进制数，该二进制数包括一个或多个位组。累积和设为零。累加和是二进制编码十进制（BCD）格式。从包含二进制数的最高有效位的位的集合到包含二进制数的最低有效位的位的位的顺序从二进制数中的每组位重复以下循环：累积和被转换成为5,1代码格式，产生临时总和。循环还包括从组中的最高有效位到最低有效位的顺序对集合中的每个下一个位进行重复：使中间和加倍; 并用下一位代替中间和的最低有效位。循环的最后一步包括将中间和转换为BCD格式，并将转换的结果存储在累加和中。一旦通过循环处理了二进制数的所有位组，就将输出累加和作为最终结果。

5. 发明申请

US20060179091A1 System and method for performing decimal to binary conversion 有权
标题翻译：用于执行十进制到二进制转换的系统和方法
公开(公告)号：US20060179091A1
公开(公告)日：2006-08-10
申请号：US11054233
申请日：2005-02-09
申请人： Steven Carlough , Bruce Fleischer , Wen Li , Eric Schwarz
发明人： Steven Carlough , Bruce Fleischer , Wen Li , Eric Schwarz
IPC分类号： G06F7/00
CPC分类号： H03M7/12
摘要： A method for converting from binary to decimal. The method includes receiving a binary coded decimal (BCD) number made up of one or more sets of three digits. A running sum and a running carry are set to zero. The following steps are performed for each set of three digits in the BCD number in order from the set of three digits containing the three most significant digits of the BCD number to the set of three digits containing the three least significant digits of the BCD number. The steps include: creating six partial products based on the set of three digits, the running sum and the running carry; combining the six partial products into two partial products; and storing the two partial products in the running sum and the running carry. After the loop has been performed for each set of three digits in the BCD number, the running sum and the running carry are combined into a final binary result.
摘要翻译：一种从二进制转换为十进制的方法。该方法包括接收由一个或多个三位数字组成的二进制编码十进制（BCD）号码。运行总和和运行进位设置为零。对于BCD号码中的每一组三位数字，按照从包含BCD号码三个最高有效数字的三位数字到包含BCD号码三个最低有效位数字的三位数组的顺序执行以下步骤。步骤包括：根据三位数字，运行总和和运行进位创建六个部分产品; 将六部分产品合并成两部分产品; 并将两个部分乘积存储在运行和运行中。在对BCD号码中的每组三位数进行了循环之后，运行总和和运行进位被组合成最终的二进制结果。

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