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1. 发明授权

US5542033A Correction and modification of microprocessor chip operations 失效
标题翻译：微处理器芯片操作的修正和修改
公开(公告)号：US5542033A
公开(公告)日：1996-07-30
申请号：US310464
申请日：1994-09-22
申请人： Son Dao-Trong , Juergen Haas , Rolf Mueller , Guenter Gerwig
发明人： Son Dao-Trong , Juergen Haas , Rolf Mueller , Guenter Gerwig
IPC分类号： G06F9/30 , G06F9/318 , G06F9/32 , G06F9/38 , G06F9/445 , G06F11/267 , G06F11/34
CPC分类号： G06F9/30145 , G06F11/2236 , G06F8/66 , G06F9/30094 , G06F9/30189 , G06F9/328 , G06F9/3836 , G06F9/3857 , G06F9/3861 , G06F9/3867
摘要： A correction of microprocessor chip design errors is achieved by identifying selected sets of instructions and/or selected sets of instruction sequences in an erroneous control flow of the microprocessor and/or by identifying selected sets of interface control and status signals. A match selectively initiates a corrective action by interfering with the instruction flow in the microprocessor chip or by requesting external control from an associated processor unit. Alternatively, a match is used for a programmable modification of interface control and status signals to adapt the chip to changes of its environment without redesign.
摘要翻译：通过在微处理器的错误控制流程中识别所选择的指令集和/或选定的指令序列集合和/或通过识别所选择的接口控制和状态信号集来实现微处理器芯片设计错误的校正。匹配通过干扰微处理器芯片中的指令流或通过从相关联的处理器单元请求外部控制来选择性地启动校正动作。或者，匹配用于接口控制和状态信号的可编程修改，以便在不重新设计的情况下使芯片适应其环境的变化。

2. 发明申请

US20070061392A1 Fused multiply add split for multiple precision arithmetic 有权
标题翻译：熔融乘法加分多重精度算术
公开(公告)号：US20070061392A1
公开(公告)日：2007-03-15
申请号：US11223641
申请日：2005-09-09
申请人： Guenter Gerwig , Eric Schwarz , Ronald Smith
发明人： Guenter Gerwig , Eric Schwarz , Ronald Smith
IPC分类号： G06F7/38
CPC分类号： G06F7/483 , G06F7/49936 , G06F7/5443 , G06F2207/3884
摘要： An apparatus and method for performing floating-point operations, particularly a fused multiply add operation. The apparatus includes a arithmetic logic unit adapted to produce both a high-order part (H) and a low-order part (L) of an intermediate extended result according to H, L=A*B+C, where A, B are input operands and C an addend. Each H, L part is formatted the same as the format of the input operands, and alignment of the resulting fractions is not affected by alignment of the inputs. The apparatus includes an architecture for suppressing left-alignment of the intermediate extended result, such that input operands for a subsequent A*B+C operation remain right-aligned.
摘要翻译：一种用于执行浮点运算的装置和方法，特别是融合乘法运算。该装置包括一个算术逻辑单元，适用于根据H，L = A * B + C产生中间扩展结果的高阶部分（H）和低阶部分（L），其中A，B为输入操作数和C加法。每个H，L部分的格式与输入操作数的格式相同，所得分数的对齐不受输入对齐的影响。该装置包括用于抑制中间扩展结果的左对齐的结构，使得用于后续A * B + C操作的输入操作数保持右对齐。

3. 发明授权

US08095821B2 Debugging for multiple errors in a microprocessor environment 有权
标题翻译：在微处理器环境中调试多个错误
公开(公告)号：US08095821B2
公开(公告)日：2012-01-10
申请号：US12405418
申请日：2009-03-17
申请人： Ulrich Mayer , Timothy John Slegel , Chung-Lung Kevin Shum , Frank Lehnert , Guenter Gerwig
发明人： Ulrich Mayer , Timothy John Slegel , Chung-Lung Kevin Shum , Frank Lehnert , Guenter Gerwig
IPC分类号： G06F11/00
CPC分类号： G06F11/1407 , G06F9/3863 , G06F9/3865 , G06F11/0721 , G06F11/076 , G06F11/0772
摘要： A new method and apparatus have been taught for storing error information used for debugging as generated by the initial and subsequent error occurrences. In this invention, a register with several bit ranges is used to store error information. The first bit-range is allocated to the initial error information. If the total number of the errors exceeds the capacity of the register, the last error is kept in a last bit-range. This way, precious initial error information (as well as the last error information) will be available for debugging.
摘要翻译：已经教导了一种新的方法和装置，用于存储由初始和随后的错误发生产生的用于调试的错误信息。在本发明中，使用具有多个位范围的寄存器来存储错误信息。第一个比特范围被分配给初始的错误信息。如果错误总数超过寄存器的容量，则最后一个错误将保留在最后一个位范围内。这样，宝贵的初始错误信息（以及最后一个错误信息）将可用于调试。

4. 发明授权

US07840622B2 Method and floating point unit to convert a hexadecimal floating point number to a binary floating point number 失效
标题翻译：方法和浮点单位将十六进制浮点数转换为二进制浮点数
公开(公告)号：US07840622B2
公开(公告)日：2010-11-23
申请号：US11489920
申请日：2006-07-20
申请人： Guenter Gerwig , Klaus Michael Kroener
发明人： Guenter Gerwig , Klaus Michael Kroener
IPC分类号： G06F7/00 , G06F15/00 , G06F7/38
CPC分类号： H03M7/24
摘要： Method to convert a hexadecimal floating point number (H) into a binary floating point number by using a Floating Point Unit (FPU) with fused multiply add with an A-register a B-register for two multiplicand operands and a C-register for an addend operand, wherein a leading zero counting unit (LZC) is associated to the addend C-register, wherein the difference of the leading zero result provided by the LZC and the input exponent (E) is calculated by a control unit and determines based on the Raw-Result-Exponent a force signal (F) with special conditions like ‘Exponent Overflow’, ‘Exponent Underflow’, and ‘Zero Result’.
摘要翻译：通过使用具有融合乘法的浮点单元（FPU）将十六进制浮点数（H）转换为二进制浮点数的方法，将A寄存器用于两个被乘数操作数的B寄存器和用于加法操作数，其中前置零计数单元（LZC）与加数C寄存器相关联，其中由LZC提供的前导零结果和输入指数（E）的差异由控制单元计算并基于原始结果指数具有特殊条件（如“指数溢出”，“指数下溢”和“零结果”）的力信号（F）。

5. 发明授权

US07392273B2 High-sticky calculation in pipelined fused multiply/add circuitry 有权
标题翻译：流水线融合乘法/加法电路中的高粘度计算
公开(公告)号：US07392273B2
公开(公告)日：2008-06-24
申请号：US10732039
申请日：2003-12-10
申请人： Guenter Gerwig , Juergen Haess , Klaus Michael Kroener
发明人： Guenter Gerwig , Juergen Haess , Klaus Michael Kroener
IPC分类号： G06F7/485 , G06F7/787
CPC分类号： G06F7/483 , G06F5/012 , G06F7/5443
摘要： Arithmetic processing circuits in a circuit in a floating point processor having a fused multiply/ADD circuitry. In order to avoid waiting cycles in the normalizer of the floating point arithmetic, control logic calculates in an extremely early state of the overall Multiply/Add processing. Parts of the intermediate add result are significant and have to be selected in the pre-normalizer multiplexer to be fed to the normalizer by counting the leading zero bits (LAB) of the addend in a dedicated circuit right at the beginning of the pipe. LAB is added to the shift amount (SA) that is calculated to align the addend and is then compared with the width of the incrementer. If the sum of (SA+LAB) is larger than the width of the incrementer, which is a constant value, then no significant bits are in the high-part of the intermediate result, and the pre-normalizer multiplexer selects the data from a second predetermined position, otherwise from a first predetermined position.
摘要翻译：具有融合乘法/ ADD电路的浮点处理器中的电路中的算术处理电路。为了避免浮点运算的归一化器中的等待周期，控制逻辑在整体乘法/加法处理的极早期状态下进行计算。中间加法结果的部分是重要的，必须在预归一化器多路复用器中选择，以通过在管道开头右侧的专用电路中的加数的前导零比特（LAB）进行计数来馈送到归一化器。将LAB加到被计算以对齐加数的移位量（SA），然后与增量器的宽度进行比较。如果（SA + LAB）的和大于作为常数值的增量器的宽度，则中间结果的高部分中没有有效位，并且预标准化器多路复用器选择来自第二预定位置，否则从第一预定位置。

6. 发明授权

US08516336B2 Latch arrangement for an electronic digital system, method, data processing program, and computer program product for implementing a latch arrangement 失效
标题翻译：用于电子数字系统的锁存装置，方法，数据处理程序和用于实现锁存装置的计算机程序产品
公开(公告)号：US08516336B2
公开(公告)日：2013-08-20
申请号：US13116365
申请日：2011-05-26
申请人： Michael Cremer , Guenter Gerwig , Frank Lehnert
发明人： Michael Cremer , Guenter Gerwig , Frank Lehnert
IPC分类号： H03M13/00
CPC分类号： G06F11/08
摘要： An improved latch arrangement for an electronic digital system is disclosed. The latch arrangement comprises a certain number of standard latches configured as configuration-switch latches which are modified only by shift operation and/or during Error Checking and Correction (ECC) action, and a corresponding number of standard latches configured as Error Checking and Correction (ECC) latches storing Error Checking and Correction (ECC) bit data used to check latch data of said configuration-switch latches.
摘要翻译：公开了一种用于电子数字系统的改进的锁存装置。闩锁装置包括被配置为配置开关锁存器的一定数量的标准锁存器，其仅通过移位操作和/或在错误检查和校正（ECC）动作期间被修改，以及配置为错误检查和校正的相应数量的标准锁存器 ECC）锁存器，存储用于检查所述配置开关锁存器的锁存数据的错误检查和校正（ECC）位数据。

7. 发明申请

US20100241899A1 Debugging for multiple errors in a microprocessor environment 有权
标题翻译：在微处理器环境中调试多个错误
公开(公告)号：US20100241899A1
公开(公告)日：2010-09-23
申请号：US12405418
申请日：2009-03-17
申请人： Ulrich Mayer , Timothy John Slegel , Chung-Lung Kevin Shum , Frank Lehnert , Guenter Gerwig
发明人： Ulrich Mayer , Timothy John Slegel , Chung-Lung Kevin Shum , Frank Lehnert , Guenter Gerwig
IPC分类号： G06F11/20 , G06F9/30
CPC分类号： G06F11/1407 , G06F9/3863 , G06F9/3865 , G06F11/0721 , G06F11/076 , G06F11/0772
摘要： A new method and apparatus have been taught for storing error information used for debugging as generated by the initial and subsequent error occurrences. In this invention, a register with several bit ranges is used to store error information. The first bit-range is allocated to the initial error information. If the total number of the errors exceeds the capacity of the register, the last error is kept in a last bit-range. This way, precious initial error information (as well as the last error information) will be available for debugging.
摘要翻译：已经教导了一种新的方法和装置，用于存储由初始和随后的错误发生产生的用于调试的错误信息。在本发明中，使用具有多个位范围的寄存器来存储错误信息。第一个比特范围被分配给初始的错误信息。如果错误总数超过寄存器的容量，则最后一个错误将保留在最后一个位范围内。这样，宝贵的初始错误信息（以及最后一个错误信息）将可用于调试。

8. 发明申请

US20070083583A1 Method for Calculating a Result of a Division with a Floating Point Unit with Fused Multiply-Add 失效
标题翻译：用浮点乘积计算分数结果的方法
公开(公告)号：US20070083583A1
公开(公告)日：2007-04-12
申请号：US11458405
申请日：2006-07-19
申请人： Guenter Gerwig , Holger Wetter
发明人： Guenter Gerwig , Holger Wetter
IPC分类号： G06F7/38
CPC分类号： G06F7/4873 , G06F7/5443
摘要： The invention proposes a Floating Point Unit with fused multiply-add, with one addend Method for calculating a result of a division with an A-register and a B-register for two multiplicand operands and a C-register for an addend operand, wherein a divide processor using a subtractive method for calculation with a divisor register and a partial remainder register and a multiplier associated to an subtractor uses the C-register as input, wherein while loading the fraction of the dividend through the divisor register into the partial remainder register of the divide processor a calculated shifting is applied for alignment by using the multiplier associated to the subtractor.
摘要翻译：本发明提出了一种具有融合乘法运算的浮点单元，具有一个附加方法，用于计算用于两个被乘数操作数的A寄存器和B寄存器的分频结果，以及用于加数操作数的C寄存器，其中a 用除法寄存器和部分余数寄存器进行计算的减法方法来分割处理器，与减法器相关联的乘法器使用C寄存器作为输入，其中通过除数寄存器将除数的分数加载到部分余数寄存器分频处理器通过使用与减法器相关联的乘法器来应用计算的移位用于对准。

9. 发明授权

US07873687B2 Method for calculating a result of a division with a floating point unit with fused multiply-add 失效
标题翻译：用融合乘法运算用浮点单位进行除法的结果的方法
公开(公告)号：US07873687B2
公开(公告)日：2011-01-18
申请号：US11458405
申请日：2006-07-19
申请人： Guenter Gerwig , Holger Wetter
发明人： Guenter Gerwig , Holger Wetter
IPC分类号： G06F7/487
CPC分类号： G06F7/4873 , G06F7/5443
摘要： The invention proposes a Floating Point Unit with fused multiply-add, with one addend Method for calculating a result of a division with an A-register and a B-register for two multiplicand operands and a C-register for an addend operand, wherein a divide processor using a subtractive method for calculation with a divisor register and a partial remainder register and a multiplier associated to an subtractor uses the C-register as input, wherein while loading the fraction of the dividend through the divisor register into the partial remainder register of the divide processor a calculated shifting is applied for alignment by using the multiplier associated to the subtractor.
摘要翻译：本发明提出了一种具有融合乘法运算的浮点单元，具有一个附加方法，用于计算用于两个被乘数操作数的A寄存器和B寄存器的分频结果，以及用于加数操作数的C寄存器，其中a 用除法寄存器和部分余数寄存器进行计算的减法方法来分割处理器，与减法器相关联的乘法器使用C寄存器作为输入，其中通过除数寄存器将除数的分数加载到部分余数寄存器分频处理器通过使用与减法器相关联的乘法器来应用计算的移位用于对准。

10. 发明申请

US20090204793A1 RAW Hazard Detection and Resolution for Implicitly Used Registers 审中-公开
标题翻译：用于隐式使用的寄存器的RAW危险检测和分辨率
公开(公告)号：US20090204793A1
公开(公告)日：2009-08-13
申请号：US12027880
申请日：2008-02-07
申请人： Frank Lehnert , Guenter Gerwig , Karin Rebmann , Michael Cremer , Ulrich Mayer
发明人： Frank Lehnert , Guenter Gerwig , Karin Rebmann , Michael Cremer , Ulrich Mayer
IPC分类号： G06F9/312
CPC分类号： G06F9/30163 , G06F9/30079 , G06F9/30087 , G06F9/30101 , G06F9/3838
摘要： The present invention provides a system, apparatus, and method for detecting and resolving read-after-write hazards encountered in processors following the dispatch of instructions requiring one or more implicit reads in a processor.
摘要翻译：本发明提供一种系统，装置和方法，用于检测和解决在处理器中发生在需要在处理器中的一个或多个隐式读取的指令的分派之后遇到的写后读取危险。

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