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1. 发明授权

US07759756B2 Dual-pixel full color CMOS imager 有权
标题翻译：双像素全彩CMOS成像仪
公开(公告)号：US07759756B2
公开(公告)日：2010-07-20
申请号：US12025618
申请日：2008-02-04
申请人： Jong-Jan Lee , Sakae Wada , Sheng Teng Hsu
发明人： Jong-Jan Lee , Sakae Wada , Sheng Teng Hsu
IPC分类号： H01L31/00 , H01L31/062 , H01L31/113
CPC分类号： H01L27/14647 , H01L27/14689
摘要： A dual-pixel full color complementary metal oxide semiconductor (CMOS) imager is provided, along with an associated fabrication process. Two stand-alone pixels are used for three-color detection. The first pixel is a single photodiode, and the second pixel has two photodiodes built in a stacked structure. The two photodiode stack includes an n doped substrate, a bottom photodiode, and a top photodiode. The bottom photodiode has a bottom p doped layer overlying the substrate and a bottom n doped layer cathode overlying the bottom p doped layer. The top photodiode has a top p doped layer overlying the bottom n doped layer and a top n doped layer cathode overlying the top p doped layer. The single photodiode includes the n doped substrate, a p doped layer overlying the substrate, and an n doped layer cathode overlying the p doped layer.
摘要翻译：提供了双像素全色互补金属氧化物半导体（CMOS）成像器，以及相关的制造工艺。两个独立像素用于三色检测。第一像素是单个光电二极管，第二像素具有以堆叠结构内置的两个光电二极管。两个光电二极管堆叠包括n掺杂衬底，底部光电二极管和顶部光电二极管。底部光电二极管具有覆盖衬底的底部p掺杂层和覆盖底部p掺杂层的底部n掺杂层阴极。顶部光电二极管具有覆盖底部n掺杂层的顶部p掺杂层和覆盖顶部p掺杂层的顶部n掺杂层阴极。单个光电二极管包括n掺杂衬底，覆盖衬底的p掺杂层和覆盖p掺杂层的n掺杂层阴极。

2. 发明申请

US20090194799A1 Dual-pixel Full Color CMOS Imager 有权
标题翻译：双像素全彩CMOS成像仪
公开(公告)号：US20090194799A1
公开(公告)日：2009-08-06
申请号：US12025618
申请日：2008-02-04
申请人： Jong-Jan Lee , Sakae Wada , Sheng Teng Hsu
发明人： Jong-Jan Lee , Sakae Wada , Sheng Teng Hsu
IPC分类号： H01L31/00 , H01L21/00
CPC分类号： H01L27/14647 , H01L27/14689
摘要： A dual-pixel full color complementary metal oxide semiconductor (CMOS) imager is provided, along with an associated fabrication process. Two stand-alone pixels are used for three-color detection. The first pixel is a single photodiode, and the second pixel has two photodiodes built in a stacked structure. The two photodiode stack includes an n doped substrate, a bottom photodiode, and a top photodiode. The bottom photodiode has a bottom p doped layer overlying the substrate and a bottom n doped layer cathode overlying the bottom p doped layer. The top photodiode has a top p doped layer overlying the bottom n doped layer and a top n doped layer cathode overlying the top p doped layer. The single photodiode includes the n doped substrate, a p doped layer overlying the substrate, and an n doped layer cathode overlying the p doped layer.
摘要翻译：提供了双像素全色互补金属氧化物半导体（CMOS）成像器，以及相关的制造工艺。两个独立像素用于三色检测。第一像素是单个光电二极管，第二像素具有以堆叠结构内置的两个光电二极管。两个光电二极管堆叠包括n掺杂衬底，底部光电二极管和顶部光电二极管。底部光电二极管具有覆盖衬底的底部p掺杂层和覆盖底部p掺杂层的底部n掺杂层阴极。顶部光电二极管具有覆盖底部n掺杂层的顶部p掺杂层和覆盖顶部p掺杂层的顶部n掺杂层阴极。单个光电二极管包括n掺杂衬底，覆盖衬底的p掺杂层和覆盖p掺杂层的n掺杂层阴极。

3. 发明授权

US07675056B2 Germanium phototransistor with floating body 有权
标题翻译：具有浮体的锗光电晶体管
公开(公告)号：US07675056B2
公开(公告)日：2010-03-09
申请号：US11891574
申请日：2007-08-10
申请人： Jong-Jan Lee , Sheng Teng Hsu , Jer-Shen Maa , Douglas J. Tweet
发明人： Jong-Jan Lee , Sheng Teng Hsu , Jer-Shen Maa , Douglas J. Tweet
IPC分类号： H01L29/06 , H01L31/072 , H01L31/109 , H01L31/0328 , H01L31/062 , H01L31/113 , H01L31/0232
CPC分类号： H01L31/1136 , H01L31/028 , H01L31/1808 , Y02E10/547
摘要： A floating body germanium (Ge) phototransistor and associated fabrication process are presented. The method includes: providing a silicon (Si) substrate; selectively forming an insulator layer overlying the Si substrate; forming an epitaxial Ge layer overlying the insulator layer using a liquid phase epitaxy (LPE) process; forming a channel region in the Ge layer; forming a gate dielectric, gate electrode, and gate spacers overlying the channel region; and, forming source/drain regions in the Ge layer. The LPE process involves encapsulating the Ge with materials having a melting temperature greater than a first temperature, and melting the Ge using a temperature lower than the first temperature. The LPE process includes: forming a dielectric layer overlying deposited Ge; melting the Ge; and, in response to cooling the Ge, laterally propagating an epitaxial growth front into the Ge from an underlying Si substrate surface.
摘要翻译：提出了一种浮体锗（Ge）光电晶体管及其制造工艺。该方法包括：提供硅（Si）衬底; 选择性地形成覆盖Si衬底的绝缘体层; 使用液相外延（LPE）工艺形成覆盖绝缘体层的外延Ge层; 在Ge层中形成沟道区; 形成覆盖所述沟道区的栅极电介质，栅电极和栅极间隔; 并且在Ge层中形成源/漏区。 LPE工艺包括用具有大于第一温度的熔化温度的材料包封Ge，并且使用低于第一温度的温度来熔化Ge。 LPE工艺包括：形成覆盖沉积Ge的介电层; 融化Ge; 并且响应于冷却Ge，将外延生长前沿从下面的Si衬底表面横向传播到Ge中。

4. 发明授权

US07608874B2 Fully isolated photodiode stack 失效
标题翻译：全隔离光电二极管堆叠
公开(公告)号：US07608874B2
公开(公告)日：2009-10-27
申请号：US11657152
申请日：2007-01-24
申请人： Jong-Jan Lee , Douglas J. Tweet , Sheng Teng Hsu
发明人： Jong-Jan Lee , Douglas J. Tweet , Sheng Teng Hsu
IPC分类号： H01L31/062 , H01L31/113
CPC分类号： H01L27/14647 , H01L27/1463 , H01L27/14689
摘要： An array of fully isolated multi-junction complimentary metal-oxide-semiconductor (CMOS) filterless color imager cells is provided, together with an associated fabrication method. The method provides a bulk silicon (Si) substrate. A plurality of color imager cells are formed, either in the Si substrate, or in a single epitaxial Si layer formed over the substrate. Each color imager cell includes a photodiode set with a first, second, and third photodiode formed as a stacked multi-junction structure. A U-shaped (in cross-section) well liner, fully isolates the photodiode set from adjacent photodiode sets in the array. For example, each photodiode is formed from a p doped Si layer physically interfaced to a first wall. A well bottom physically interfaces to the first wall, and the p doped Si layer of the third, bottom-most, photodiode is part of the well bottom. Then, the photodiode sets may be formed from an n/p/n/p/n/p or n/p/p−/p/p−/p layered structure.
摘要翻译：提供了完全隔离的多结互补金属氧化物半导体（CMOS）无滤膜彩色成像器单元的阵列，以及相关的制造方法。该方法提供体硅（Si）衬底。在Si衬底中或在衬底上形成的单个外延Si层中形成多个彩色成像器单元。每个彩色成像器单元包括具有形成为堆叠多结结构的第一，第二和第三光电二极管。 U形（横截面）井衬管，将阵列中的光电二极管组与相邻的光电二极管组完全隔离。例如，每个光电二极管由物理上与第一壁物理连接的p掺杂Si层形成。阱底部与第一壁物理接口，第三，最底部的光电二极管的p掺杂Si层是阱底部的一部分。然后，光电二极管组可以由n / p / n / p / n / p或n / p / p / p / p / p层叠结构形成。

5. 发明授权

US07438759B2 Ambient environment nanowire sensor 失效
公开(公告)号：US07438759B2
公开(公告)日：2008-10-21
申请号：US11264113
申请日：2005-11-01
申请人： Fengyan Zhang , Robert A. Barrowcliff , Jong-Jan Lee , Sheng Teng Hsu
发明人： Fengyan Zhang , Robert A. Barrowcliff , Jong-Jan Lee , Sheng Teng Hsu
IPC分类号： C30B1/02
CPC分类号： B81C1/00182 , B81B2201/0214 , Y10S977/712 , Y10S977/762
摘要： An ambient environment nanowire sensor and corresponding fabrication method have been provided. The method includes: forming a substrate such as Silicon (Si) or glass; growing nanowires; depositing an insulator layer overlying the nanowires; etching to expose tips of the nanowires; forming a patterned metal electrode, with edges, overlying the tips of the nanowires; and, etching to expose the nanowires underlying the electrode edges. The nanowires can be a material such as IrO2, TiO2, InO, ZnO, SnO2, Sb2O3, or In2O3, to mane just a few examples. The insulator layer can be a spin-on glass (SOG) or low-k dielectric. In one aspect, the resultant structure includes exposed nanowires grown from the doped substrate regions and an insulator core with embedded nanowires. In a different aspect, the method forms a growth promotion layer overlying the substrate. The resultant structure includes exposed nanowires grown from the selectively formed growth promotion layer.

6. 发明授权

US07351995B2 Floating body germanium phototransistor having a photo absorption threshold bias region 有权
标题翻译：具有光吸收阈值偏置区域的浮体锗光电晶体管
公开(公告)号：US07351995B2
公开(公告)日：2008-04-01
申请号：US11894938
申请日：2007-08-22
申请人： Sheng Teng Hsu , Jong-Jan Lee , Jer-Shen Maa , Douglas J. Tweet
发明人： Sheng Teng Hsu , Jong-Jan Lee , Jer-Shen Maa , Douglas J. Tweet
IPC分类号： H01L29/06 , H01L31/072 , H01L31/109 , H01L31/0328 , H01L31/062 , H01L31/113 , H01L31/0232
CPC分类号： H01L31/1136
摘要： A floating body germanium (Ge) phototransistor with a photo absorption threshold bias region, and an associated fabrication process are presented. The method includes: providing a p-doped Silicon (Si) substrate; selectively forming an insulator layer overlying a first surface of the Si substrate; forming an epitaxial Ge layer overlying the insulator layer; forming a channel region in the Ge layer; forming a gate dielectric, gate electrode, and gate spacers; forming source/drain (S/D) regions in the Ge layer; and, forming a photo absorption threshold bias region in the Ge layer, adjacent the channel region. In one aspect, the second S/D region has a length, longer than the first S/D length. The photo absorption threshold bias region underlies the second S/D region. Alternately, the second S/D region is separated from the channel by an offset, and the photo absorption threshold bias region is the offset in the Ge layer, after a light p-doping.
摘要翻译：提出了具有光吸收阈值偏置区域的浮体锗（Ge）光电晶体管，以及相关的制造工艺。该方法包括：提供p掺杂硅（Si）衬底; 选择性地形成覆盖在所述Si衬底的第一表面上的绝缘体层; 形成覆盖绝缘体层的外延Ge层; 在Ge层中形成沟道区; 形成栅极电介质，栅电极和栅极间隔物; 在Ge层中形成源极/漏极（S / D）区域; 并且在Ge层中形成邻近沟道区的光吸收阈值偏置区域。在一个方面，第二S / D区域具有比第一S / D长度更长的长度。光吸收阈值偏置区域位于第二S / D区域的下方。或者，第二S / D区域与沟道分离偏移，光吸收阈值偏置区域是在光p掺杂之后的Ge层中的偏移。

7. 发明授权

US07233036B1 Double-junction filterless CMOS color imager cell 失效
标题翻译：双路无滤芯CMOS彩色成像单元
公开(公告)号：US07233036B1
公开(公告)日：2007-06-19
申请号：US11499081
申请日：2006-08-04
申请人： Sheng Teng Hsu , Jong-Jan Lee
发明人： Sheng Teng Hsu , Jong-Jan Lee
IPC分类号： H01L31/62 , H01L31/113
CPC分类号： H01L27/14647 , H01L27/14603 , H01L27/14632 , H01L27/14645 , H01L27/14683 , H01L27/14689
摘要： A double-junction complimentary metal-oxide-semiconductor (CMOS) filterless color imager cell is provided. The imager cell is fabricated from a silicon-on-insulator (SOI) substrate including a silicon (Si) substrate, a silicon dioxide insulator overlying the substrate, and a Si top layer overlying the insulator. A photodiode set is formed in the SOI substrate, including a first and second photodiode formed as a double-junction structure in the Si substrate. A third photodiode is formed in the Si top layer. A (imager sensing) transistor set is formed in the top Si layer. The transistor set is connected to the photodiode set and detects an independent output signal for each photodiode. The transistor set may be an eight-transistor (8T), a nine-transistor (9T), or an eleven-transistor (11T) cell.
摘要翻译：提供了一种双结互补金属氧化物半导体（CMOS）无滤色彩色成像单元。成像器单元由包括硅（Si）衬底，覆盖衬底的二氧化硅绝缘体和覆盖绝缘体的Si顶层的绝缘体上硅（SOI）衬底制造。在SOI衬底中形成光电二极管组，包括在Si衬底中形成为双结结构的第一和第二光电二极管。在Si顶层中形成第三光电二极管。在顶部Si层中形成A（成像器感测）晶体管组。晶体管组连接到光电二极管组，并检测每个光电二极管的独立输出信号。晶体管组可以是八晶体管（8T），九晶体管（9T）或十一晶体管（11T）单元。

8. 发明授权

US06583000B1 Process integration of Si1-xGex CMOS with Si1-xGex relaxation after STI formation 失效
标题翻译： STI形成后Si1-xGex CMOS与Si1-xGex弛豫过程的整合
公开(公告)号：US06583000B1
公开(公告)日：2003-06-24
申请号：US10072183
申请日：2002-02-07
申请人： Sheng Teng Hsu , Jong-Jan Lee , Jer-shen Maa , Douglas James Tweet
发明人： Sheng Teng Hsu , Jong-Jan Lee , Jer-shen Maa , Douglas James Tweet
IPC分类号： H01L218238
CPC分类号： H01L21/823807 , H01L21/76224 , H01L21/823878
摘要： A method of forming a CMOS device includes preparing a silicon substrate, including forming plural device regions on the substrate; epitaxially forming a strained SiGe layer on the substrate, wherein the SiGe layer has a germanium content of between about 20% and 40%; forming a silicon cap layer epitaxially on the SiGe layer; depositing a gate oxide layer; depositing a first polysilicon layer; implanting H+ ions to a depth below the SiGe layer; forming a trench by shallow trench isolation which extends into the substrate; annealing the structure at a temperature of between about 700° C. to 900° C. for between about five minutes to sixty minutes; depositing an oxide layer and a second polysilicon layer, thereby filling the trench; planarizing the structure to the top of the level of the portion of the second polysilicon layer which is located in the trench; and completing the CMOS device.
摘要翻译：形成CMOS器件的方法包括制备硅衬底，包括在衬底上形成多个器件区域; 在衬底上外延地形成应变SiGe层，其中SiGe层的锗含量在约20％和40％之间; 在SiGe层上外延地形成硅帽层; 沉积栅氧化层; 沉积第一多晶硅层; 将H +离子注入SiGe层以下的深度; 通过延伸到衬底中的浅沟槽隔离形成沟槽; 在约700℃至900℃的温度下退火结构约5分钟至60分钟; 沉积氧化物层和第二多晶硅层，从而填充沟槽; 将结构平面化到位于沟槽中的第二多晶硅层的部分的顶部的顶部; 并完成CMOS设备。

9. 发明授权

US06562703B1 Molecular hydrogen implantation method for forming a relaxed silicon germanium layer with high germanium content 失效
标题翻译：用于形成具有高锗含量的松弛硅锗层的分子氢注入方法
公开(公告)号：US06562703B1
公开(公告)日：2003-05-13
申请号：US10099374
申请日：2002-03-13
申请人： Jer-Shen Maa , Douglas J. Tweet , Sheng Teng Hsu , Jong-Jan Lee
发明人： Jer-Shen Maa , Douglas J. Tweet , Sheng Teng Hsu , Jong-Jan Lee
IPC分类号： H01L21265
CPC分类号： H01L21/263 , H01L21/02381 , H01L21/0245 , H01L21/02502 , H01L21/0251 , H01L21/02532 , H01L21/02694 , H01L29/1054 , Y10S438/933
摘要： A method is provided for forming a relaxed silicon germanium layer with a high germanium content on a silicon substrate. The method comprises: depositing a single-crystal silicon (Si) buffer layer overlying the silicon substrate; depositing a layer of single-crystal silicon germanium (Si1−xGex) overlying the Si buffer layer having a thickness of 1000 to 5000 Å; implanting the Si1−xGex layer with ionized molecular hydrogen (H2+) a projected range of approximately 100 to 300 Å into the underlying Si buffer layer; optionally, implanting the Si1−xGex layer with a species selected such as boron, He, or Si; annealing; and, in response to the annealing, converting the Si1−xGex layer to a relaxed Si1−xGex layer. Optionally, after annealing, an additional layer of single-crystal Si1−xGex having a thickness of greater than 1000 Å can be deposited overlying the relaxed layer of Si1−xGex.
摘要翻译：提供了一种在硅衬底上形成具有高锗含量的松弛硅锗层的方法。该方法包括：沉积覆盖硅衬底的单晶硅（Si）缓冲层; 沉积覆盖厚度为1000至5000的Si缓冲层的单晶硅锗层（Si1-xGex）; 将具有离子化分子氢（H 2 +）的Si 1-x Ge x层投射到下面的Si缓冲层中约100至300埃的投影范围; 任选地，将Si1-xGex层用诸如硼，氦或硅的物质进行注入; 退火; 并且响应于退火，将Si1-xGex层转化为弛豫的Si1-xGex层。任选地，在退火之后，可以沉积厚度大于的附加层的单晶Si1-xGex覆盖在Si1-xGex的松弛层上。

10. 发明授权

US06510073B1 Two transistor ferroelectric non-volatile memory 失效
标题翻译：两个晶体管铁电非易失性存储器
公开(公告)号：US06510073B1
公开(公告)日：2003-01-21
申请号：US10062850
申请日：2002-01-31
申请人： Jong-Jan Lee , Sheng Teng Hsu
发明人： Jong-Jan Lee , Sheng Teng Hsu
IPC分类号： G11C1122
CPC分类号： G11C11/22
摘要： A two transistor ferroelectric non-volatile memory cell includes a ferroelectric capacitor connected to a word line and having an upper electrode and a lower electrode; a first MOS transistor having a linear capacitor located at a gate oxide region thereof, wherein a gate of the first MOS transistor is connected to the lower electrode of said ferroelectric capacitor and wherein a drain of the first transistor is connected to a bit line; a second MOS transistor having a gate connected to a programming line, a drain connected to the lower electrode of the ferroelectric capacitor, and a source connected to a ground and the source of the first transistor; wherein, when a positive pulse is applied to the word line and to the programming line, a charge is placed on the ferroelectric capacitor and the ferroelectric capacitor is decoupled from the MOS linear capacitor by connecting the bottom electrode of the ferroelectric capacitor to the ground state. When a positive pulse is applied to the word line and a positive pulse is applied to the programming line, a “1” state is created. When a negative pulse is applied to the word line and a positive pulse is applied to the programming line, a “0” state is created.
摘要翻译：双晶体管铁电非易失性存储单元包括连接到字线并具有上电极和下电极的铁电电容器; 第一MOS晶体管，其具有位于其栅极氧化物区域处的线性电容器，其中所述第一MOS晶体管的栅极连接到所述铁电电容器的下电极，并且所述第一晶体管的漏极连接到位线; 第二MOS晶体管，具有连接到编程线的栅极，连接到铁电电容器的下电极的漏极和连接到地的源极和第一晶体管的源极; 其中，当对字线和编程线施加正脉冲时，通过将铁电电容器的底部电极连接到基态，将铁电电容器放置在铁电电容器上，并将铁电电容器与MOS线性电容器分离。当正脉冲施加到字线并且正脉冲施加到编程线时，产生“1”状态。当对字线施加负脉冲并且向编程线施加正脉冲时，产生“0”状态。

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