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1. 发明授权

US07759756B2 Dual-pixel full color CMOS imager 有权
标题翻译：双像素全彩CMOS成像仪
公开(公告)号：US07759756B2
公开(公告)日：2010-07-20
申请号：US12025618
申请日：2008-02-04
申请人： Jong-Jan Lee , Sakae Wada , Sheng Teng Hsu
发明人： Jong-Jan Lee , Sakae Wada , Sheng Teng Hsu
IPC分类号： H01L31/00 , H01L31/062 , H01L31/113
CPC分类号： H01L27/14647 , H01L27/14689
摘要： A dual-pixel full color complementary metal oxide semiconductor (CMOS) imager is provided, along with an associated fabrication process. Two stand-alone pixels are used for three-color detection. The first pixel is a single photodiode, and the second pixel has two photodiodes built in a stacked structure. The two photodiode stack includes an n doped substrate, a bottom photodiode, and a top photodiode. The bottom photodiode has a bottom p doped layer overlying the substrate and a bottom n doped layer cathode overlying the bottom p doped layer. The top photodiode has a top p doped layer overlying the bottom n doped layer and a top n doped layer cathode overlying the top p doped layer. The single photodiode includes the n doped substrate, a p doped layer overlying the substrate, and an n doped layer cathode overlying the p doped layer.
摘要翻译：提供了双像素全色互补金属氧化物半导体（CMOS）成像器，以及相关的制造工艺。两个独立像素用于三色检测。第一像素是单个光电二极管，第二像素具有以堆叠结构内置的两个光电二极管。两个光电二极管堆叠包括n掺杂衬底，底部光电二极管和顶部光电二极管。底部光电二极管具有覆盖衬底的底部p掺杂层和覆盖底部p掺杂层的底部n掺杂层阴极。顶部光电二极管具有覆盖底部n掺杂层的顶部p掺杂层和覆盖顶部p掺杂层的顶部n掺杂层阴极。单个光电二极管包括n掺杂衬底，覆盖衬底的p掺杂层和覆盖p掺杂层的n掺杂层阴极。

2. 发明申请

US20090194799A1 Dual-pixel Full Color CMOS Imager 有权
标题翻译：双像素全彩CMOS成像仪
公开(公告)号：US20090194799A1
公开(公告)日：2009-08-06
申请号：US12025618
申请日：2008-02-04
申请人： Jong-Jan Lee , Sakae Wada , Sheng Teng Hsu
发明人： Jong-Jan Lee , Sakae Wada , Sheng Teng Hsu
IPC分类号： H01L31/00 , H01L21/00
CPC分类号： H01L27/14647 , H01L27/14689
摘要： A dual-pixel full color complementary metal oxide semiconductor (CMOS) imager is provided, along with an associated fabrication process. Two stand-alone pixels are used for three-color detection. The first pixel is a single photodiode, and the second pixel has two photodiodes built in a stacked structure. The two photodiode stack includes an n doped substrate, a bottom photodiode, and a top photodiode. The bottom photodiode has a bottom p doped layer overlying the substrate and a bottom n doped layer cathode overlying the bottom p doped layer. The top photodiode has a top p doped layer overlying the bottom n doped layer and a top n doped layer cathode overlying the top p doped layer. The single photodiode includes the n doped substrate, a p doped layer overlying the substrate, and an n doped layer cathode overlying the p doped layer.
摘要翻译：提供了双像素全色互补金属氧化物半导体（CMOS）成像器，以及相关的制造工艺。两个独立像素用于三色检测。第一像素是单个光电二极管，第二像素具有以堆叠结构内置的两个光电二极管。两个光电二极管堆叠包括n掺杂衬底，底部光电二极管和顶部光电二极管。底部光电二极管具有覆盖衬底的底部p掺杂层和覆盖底部p掺杂层的底部n掺杂层阴极。顶部光电二极管具有覆盖底部n掺杂层的顶部p掺杂层和覆盖顶部p掺杂层的顶部n掺杂层阴极。单个光电二极管包括n掺杂衬底，覆盖衬底的p掺杂层和覆盖p掺杂层的n掺杂层阴极。

3. 发明授权

US07811913B2 Method of fabricating a low, dark-current germanium-on-silicon pin photo detector 有权
标题翻译：制造低，暗电流硅 - 硅引脚光电探测器的方法
公开(公告)号：US07811913B2
公开(公告)日：2010-10-12
申请号：US11312967
申请日：2005-12-19
申请人： Jong-Jan Lee , Douglas J. Tweet , Jer-Shen Maa , Sheng Teng Hsu
发明人： Jong-Jan Lee , Douglas J. Tweet , Jer-Shen Maa , Sheng Teng Hsu
IPC分类号： H01L21/265
CPC分类号： H01L31/105 , H01L31/1808 , H01L31/1864 , Y02E10/50 , Y02P70/521 , Y10S438/933
摘要： A method of fabricating a low, dark-current germanium-on-silicon PIN photo detector includes preparing a P-type silicon wafer; implanting the P-type silicon wafer with boron ions; activating the boron ions to form a P+ region on the silicon wafer; forming a boron-doped germanium layer on the P+ silicon surface; depositing an intrinsic germanium layer on the boron-doped germanium layer; cyclic annealing, including a relatively high temperature first anneal step and a relatively low temperature second anneal step; repeating the first and second anneal steps for about twenty cycles, thereby forcing crystal defects to the P+ germanium layer; implanting ions in the surface of germanium layer to form an N+ germanium surface layer and a PIN diode; activating the N+ germanium surface layer by thermal anneal; and completing device according to known techniques to form a low dark-current germanium-on-silicon PIN photodetector.
摘要翻译：制造低，暗电流锗硅PIN光检测器的方法包括制备P型硅晶片; 用硼离子注入P型硅晶片; 激活硼离子以在硅晶片上形成P +区; 在P +硅表面上形成硼掺杂锗层; 在硼掺杂的锗层上沉积本征锗层; 循环退火，包括相对高温的第一退火步骤和相对低温的第二退火步骤; 重复第一和第二退火步骤约20个循环，由此迫使晶体缺陷到P +锗层; 在锗层表面注入离子以形成N +锗表面层和PIN二极管; 通过热退火来活化N +锗表面层; 并根据已知技术完成器件以形成低暗电流锗硅PIN光电探测器。

4. 发明授权

US07651883B2 High energy implant photodiode stack 失效
标题翻译：高能注入光电二极管叠层
公开(公告)号：US07651883B2
公开(公告)日：2010-01-26
申请号：US11801320
申请日：2007-05-09
申请人： Jong-Jan Lee , Douglas J. Tweet , Sheng Teng Hsu
发明人： Jong-Jan Lee , Douglas J. Tweet , Sheng Teng Hsu
IPC分类号： H01L21/00
CPC分类号： H01L27/14647 , H01L27/1463 , H01L27/14689
摘要： An array of fully isolated multi-junction complimentary metal-oxide-semiconductor (CMOS) filterless color imager cells is provided, with a corresponding fabrication process. The color imager cell array is formed from a bulk silicon (Si) substrate without an overlying epitaxial Si layer. A plurality of color imager cells are formed in the bulk Si substrate, where each color imager cell includes a photodiode set and a U-shaped well liner. The photodiode set includes first, second, and third photodiode formed as a stacked multi-junction structure, while the U-shaped well liner fully isolates the photodiode set from adjacent photodiode sets in the array. The U-shaped well liner includes a physically interfacing doped well liner bottom and first wall. The well liner bottom is interposed between the substrate and the photodiode set, and the first wall physically interfaces each doped layer of each photodiode in the photodiode set.
摘要翻译：提供了完全隔离的多结互补金属氧化物半导体（CMOS）无滤膜彩色成像器单元的阵列，具有相应的制造工艺。彩色成像器单元阵列由体硅（Si）衬底形成，而不具有上覆的外延Si层。在本体Si衬底中形成多个彩色成像器单元，其中每个彩色成像器单元包括光电二极管组和U形衬管。光电二极管组包括形成为堆叠多结结构的第一，第二和第三光电二极管，而U形阱衬套将光电二极管组与阵列中的相邻光电二极管组完全隔离。 U形井衬管包括物理接口掺杂的井筒底部和第一壁。阱衬底位于衬底和光电二极管组之间，并且第一壁物理地连接光电二极管组中每个光电二极管的每个掺杂层。

5. 发明授权

US07651880B2 Ge short wavelength infrared imager 有权
标题翻译： Ge短波长红外成像仪
公开(公告)号：US07651880B2
公开(公告)日：2010-01-26
申请号：US11592465
申请日：2006-11-04
申请人： Douglas J. Tweet , Jer-Shen Maa , Jong-Jan Lee , Sheng Teng Hsu
发明人： Douglas J. Tweet , Jer-Shen Maa , Jong-Jan Lee , Sheng Teng Hsu
IPC分类号： H01L25/00
CPC分类号： H01L31/1055 , H01L27/14643 , H01L27/14689
摘要： A germanium (Ge) short wavelength infrared (SWIR) imager and associated fabrication process are provided. The imager comprises a silicon (Si) substrate with doped wells. An array of pin diodes is formed in a relaxed Ge-containing film overlying the Si substrate, each pin diode having a flip-chip interface. There is a Ge/Si interface, and a doped Ge-containing buffer interposed between the Ge-containing film and the Ge/Si interface. An array of Si CMOS readout circuits is bonded to the flip-chip interfaces. Each readout circuit has a zero volt diode bias interface.
摘要翻译：提供锗（Ge）短波长红外（SWIR）成像器和相关制造工艺。该成像器包括具有掺杂阱的硅（Si）衬底。在位于Si衬底上的松弛的含Ge膜中形成一个pin二极管阵列，每个pin二极管具有倒装芯片接口。存在Ge / Si界面和插入含Ge膜和Ge / Si界面之间的含掺杂Ge的缓冲层。 Si CMOS读出电路阵列结合到倒装芯片接口。每个读出电路都具有零伏二极管偏置接口。

6. 发明申请

US20090173933A1 Thermal Sensor with a Silicon/Germanium Superlattice Structure 有权
标题翻译：具有硅/锗超晶格结构的热传感器
公开(公告)号：US20090173933A1
公开(公告)日：2009-07-09
申请号：US12236480
申请日：2008-09-23
申请人： Jer-Shen Maa , Jinke Tang , Jong-Jan Lee , Douglas J. Tweet , Sheng Teng Hsu
发明人： Jer-Shen Maa , Jinke Tang , Jong-Jan Lee , Douglas J. Tweet , Sheng Teng Hsu
IPC分类号： H01L29/15
CPC分类号： H01L31/035254 , B82Y20/00 , H01L27/14649 , H01L31/028 , H01L31/101 , H01L31/1804 , Y02P70/521
摘要： A silicon/germanium (SiGe) superlattice thermal sensor is provided with a corresponding fabrication method. The method forms an active CMOS device in a first Si substrate, and a SiGe superlattice structure on a second Si-on-insulator (SOI) substrate. The first substrate is bonded to the second substrate, forming a bonded substrate. An electrical connection is formed between the SiGe superlattice structure and the CMOS device, and a cavity is formed between the SiGe superlattice structure and the bonded substrate.
摘要翻译：硅/锗（SiGe）超晶格热传感器具有相应的制造方法。该方法在第一Si衬底中形成有源CMOS器件，并在第二绝缘体上（SOI）衬底上形成SiGe超晶格结构。第一基板与第二基板接合，形成接合基板。在SiGe超晶格结构和CMOS器件之间形成电连接，并且在SiGe超晶格结构和键合衬底之间形成空穴。

7. 发明授权

US07470573B2 Method of making CMOS devices on strained silicon on glass 失效
标题翻译：在玻璃上的应变硅上制造CMOS器件的方法
公开(公告)号：US07470573B2
公开(公告)日：2008-12-30
申请号：US11060878
申请日：2005-02-18
申请人： Jong-Jan Lee , Jer-Shen Maa , Douglas J. Tweet , Yoshi Ono , Sheng Teng Hsu
发明人： Jong-Jan Lee , Jer-Shen Maa , Douglas J. Tweet , Yoshi Ono , Sheng Teng Hsu
IPC分类号： H01L21/30 , H01L21/84
CPC分类号： H01L27/127 , H01L27/1214 , H01L27/1266 , H01L29/7842 , H01L29/78621
摘要： A method of making CMOS devices on strained silicon on glass includes preparing a glass substrate, including forming a strained silicon layer on the glass substrate; forming a silicon oxide layer by plasma oxidation of the strained silicon layer; depositing a layer of doped polysilicon on the silicon oxide layer; forming a polysilicon gate; implanting ions to form a LDD structure; depositing and forming a spacer dielectric on the gate structure; implanting and activation ions to form source and drain structures; depositing a layer of metal film; annealing the layer of metal film to form salicide on the source, drain and gate structures; removing any unreacted metal film; depositing a layer of interlayer dielectric; and forming contact holes and metallizing.
摘要翻译：在玻璃上的应变硅上制造CMOS器件的方法包括制备玻璃衬底，包括在玻璃衬底上形成应变硅层; 通过应变硅层的等离子体氧化形成氧化硅层; 在氧化硅层上沉积掺杂多晶硅层; 形成多晶硅栅极; 注入离子以形成LDD结构; 在栅极结构上沉积和形成间隔电介质; 植入和激活离子以形成源和漏结构; 沉积一层金属膜; 退火金属膜层，在源极，漏极和栅极结构上形成硅化物; 去除任何未反应的金属膜; 沉积层间电介质层; 并形成接触孔和金属化。

8. 发明授权

US07384837B2 Method for isolating silicon germanium dislocation regions in strained-silicon CMOS applications 有权
标题翻译：在应变硅CMOS应用中分离硅锗位错区的方法
公开(公告)号：US07384837B2
公开(公告)日：2008-06-10
申请号：US11073185
申请日：2005-03-03
申请人： Sheng Teng Hsu , Jong-Jan Lee , Douglas J. Tweet , Jer-shen Maa
发明人： Sheng Teng Hsu , Jong-Jan Lee , Douglas J. Tweet , Jer-shen Maa
IPC分类号： H01L21/8238
CPC分类号： H01L29/1054 , H01L21/76224 , H01L21/823807 , H01L21/823842 , H01L21/823878 , H01L27/1203 , H01L29/78645
摘要： A dual gate strained-Si MOSFET with thin SiGe dislocation regions and a method for fabricating the same are provided. The method forms a first layer of relaxed SiGe overlying a substrate, having a thickness of less than 5000 Å; forms a second layer of relaxed SiGe overlying the substrate and adjacent to the first layer of SiGe, having a thickness of less than 5000 Å; forms a layer of strained-Si overlying the first and second SiGe layers; forms a shallow trench isolation region interposed between the first SiGe layer and the second SiGe layer; forms an p-well in the substrate and the overlying first layer of SiGe; forming forms a p-well in the substrate and the overlying second layer of SiGe; forms channel regions, in the strained-Si, and forms PMOS and NMOS transistor source and drain regions.
摘要翻译：提供具有薄SiGe位错区域的双栅应变Si MOSFET及其制造方法。该方法形成覆盖衬底的第一层松弛SiGe，厚度小于5000; 形成覆盖衬底并且邻近第一SiGe层的第二层松弛SiGe，其厚度小于5000; 形成层叠在第一和第二SiGe层上的应变层; 形成介于第一SiGe层和第二SiGe层之间的浅沟槽隔离区; 在衬底和SiGe的上覆第一层中形成p阱; 在衬底和SiGe的上覆第二层中形成p阱; 在应变Si中形成沟道区，并形成PMOS和NMOS晶体管的源极和漏极区。

9. 发明授权

US07378309B2 Method of fabricating local interconnects on a silicon-germanium 3D CMOS 有权
标题翻译：在硅 - 锗3D CMOS上制造局部互连的方法
公开(公告)号：US07378309B2
公开(公告)日：2008-05-27
申请号：US11376542
申请日：2006-03-15
申请人： Jong-Jan Lee , Paul J. Schuele , Sheng Teng Hsu , Jer-Shen Maa
发明人： Jong-Jan Lee , Paul J. Schuele , Sheng Teng Hsu , Jer-Shen Maa
IPC分类号： H01L21/8234
CPC分类号： H01L21/823871 , H01L21/02532 , H01L21/02667 , H01L21/28525 , H01L21/76895 , H01L27/11 , H01L27/1108
摘要： A method of fabricating local interconnect on a silicon-germanium 3D CMOS includes fabricating an active silicon CMOS device on a silicon substrate. An insulator layer is deposited on the silicon substrate and a seed window is opened through the insulator layer to the silicon substrate and to a silicon CMOS device gate. A germanium thin film is deposited on the insulator layer and into windows, forming a contact between the germanium thin film and the silicon device. The germanium thin film is encapsulated in a dielectric material. The wafer is heated at a temperature sufficient to flow the germanium, while maintaining the other layers in a solid condition. The wafer is cooled to solidify the germanium as single crystal germanium and as polycrystalline germanium, which provides local interconnects. Germanium CMOS devices may be fabricated on the single crystal germanium thin film.
摘要翻译：在硅 - 锗3D CMOS上制造局部互连的方法包括在硅衬底上制造有源硅CMOS器件。绝缘体层沉积在硅衬底上，并且晶种窗通过绝缘体层向硅衬底和硅CMOS器件栅极打开。在绝缘体层和窗口上沉积锗薄膜，形成锗薄膜和硅器件之间的接触。锗薄膜被封装在电介质材料中。在足以使锗流动的温度下加热晶片，同时将其它层保持在固体状态。将晶片冷却以将锗固化为单晶锗和作为多晶锗，其提供局部互连。可以在单晶锗薄膜上制造锗CMOS器件。

10. 发明申请

US20080067499A1 Silicon/germanium superlattice thermal sensor 失效
公开(公告)号：US20080067499A1
公开(公告)日：2008-03-20
申请号：US11522003
申请日：2006-09-15
申请人： Jer-Shen Maa , Jinke Tang , Jong-Jan Lee , Douglas J. Tweet , Sheng Teng Hsu
发明人： Jer-Shen Maa , Jinke Tang , Jong-Jan Lee , Douglas J. Tweet , Sheng Teng Hsu
IPC分类号： H01L29/06 , H01L21/00
CPC分类号： H01L31/035254 , B82Y20/00 , H01L27/14649 , H01L31/028 , H01L31/101 , H01L31/1804 , Y02P70/521
摘要： A silicon/germanium (SiGe) superlattice thermal sensor is provided with a corresponding fabrication method. The method forms an active CMOS device in a first Si substrate, and a SiGe superlattice structure on a second Si-on-insulator (SOI) substrate. The first substrate is bonded to the second substrate, forming a bonded substrate. An electrical connection is formed between the SiGe superlattice structure and the CMOS device, and a cavity is formed between the SiGe superlattice structure and the bonded substrate.

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