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1. 发明授权

US06825535B2 Field effect transistor formed on SOI substrate 失效
标题翻译：在SOI衬底上形成场效应晶体管
公开(公告)号：US06825535B2
公开(公告)日：2004-11-30
申请号：US10284203
申请日：2002-10-31
申请人： Noriyuki Miura
发明人： Noriyuki Miura
IPC分类号： H01L21265
CPC分类号： H01L29/458 , H01L29/41733 , H01L29/78618
摘要： A field effect transistor comprises a silicon layer formed on an insulator, a diffused layer formed by diffusing dopant from a part of a surface of the silicon layer up to the insulator, a silicide layer formed toward the insulator side from a surface of the diffused layer so as to have a thickness less than or equal to that of the diffused layer, a contact conductive layer formed on the surface of the silicide layer, a gate insulating layer formed on the silicon layer, a gate electrode formed on the gate insulating layer and a sidewall formed on a side surface of the gate electrode. The shortest distance X between surfaces opposed to each other, of the contact conductive layer and the sidewall satisfies a relation represented by the following expression (1): R(slc)×106×(1+Tslc/Tsoi)≦X≦200/rs. Expression (1)
摘要翻译：场效应晶体管包括形成在绝缘体上的硅层，通过将掺杂剂从硅层的表面的一部分扩散到绝缘体而形成的扩散层，从扩散层的表面向绝缘体侧形成的硅化物层使其厚度小于或等于扩散层的厚度，形成在硅化物层的表面上的接触导电层，形成在硅层上的栅极绝缘层，形成在栅极绝缘层上的栅电极和形成在栅电极的侧表面上的侧壁。接触导电层和侧壁彼此相对的表面之间的最短距离X满足由以下表达式（1）表示的关系：

2. 发明授权

US06573166B2 Method of fabricating a LDD with different resistance value 有权
公开(公告)号：US06573166B2
公开(公告)日：2003-06-03
申请号：US09681990
申请日：2001-07-03
申请人： Chin-Yang Chen
发明人： Chin-Yang Chen
IPC分类号： H01L21265
CPC分类号： H01L29/6659 , H01L21/823814 , H01L21/823857
摘要： A method of fabricating lightly doped drains (LDD) of different resistance values starts by providing a semiconductor wafer, the semiconductor wafer having a first active area and a second active area positioned on the substrate. Secondly, a first gate and a second gate are formed on the first active area and the second active area, respectively. A first ion implantation process is then performed to implant dopants of a first electric type on a surface of portions of the substrate within the second active area, followed by performing a second ion implantation process to implant dopants of a second electric type on a surface of portions of the substrate within the first active area and second active area. Finally, the dopants of each electric type are activated to form a first LDD and a second LDD adjacent to the first gate and the second gate, respectively, the first LDD and the second LDD being of different resistance values.

3. 发明授权

US06559038B2 Method for growing p-n heterojunction-based structures utilizing HVPE techniques 有权
公开(公告)号：US06559038B2
公开(公告)日：2003-05-06
申请号：US09860651
申请日：2001-05-18
申请人： Audrey E. Nikolaev , Yuri V. Melnik , Konstantin V. Vassilevski , Vladimir A. Dmitriev
发明人： Audrey E. Nikolaev , Yuri V. Melnik , Konstantin V. Vassilevski , Vladimir A. Dmitriev
IPC分类号： H01L21265
CPC分类号： C30B25/02 , B82Y10/00 , B82Y30/00 , C30B29/40 , C30B29/403 , C30B29/406 , H01L21/0237 , H01L21/02378 , H01L21/02458 , H01L21/02505 , H01L21/0254 , H01L21/02543 , H01L21/02546 , H01L21/02579 , H01L21/0259 , H01L21/0262 , H01L31/0304 , H01L31/105 , H01L33/007 , Y02E10/544
摘要： A method for fabricating p-type, i-type, and n-type III-V compound materials using HVPE techniques is provided. If desired, these materials can be grown directly onto the surface of a substrate without the inclusion of a low temperature buffer layer. By growing multiple layers of differing conductivity, a variety of different device structures can be fabricated including simple p-n homojunction and heterojunction structures as well as more complex structures in which the p-n junction, either homojunction or heterojunction, is interposed between a pair of wide band gap material layers. The provided method can also be used to fabricate a device in which a non-continuous quantum dot layer is grown within the p-n junction. The quantum dot layer is comprised of a plurality of quantum dot regions, each of which is typically between approximately 20 and 30 Angstroms per axis. The quantum dot layer is preferably comprised of AlxByInzGa1−x−y−zN, InGaN1−a−bPaAsb, or AlxByInzGa1−x−y−zN1−a−bPaAsb.

4. 发明授权

US06551910B2 Method of manufacturing solid-state image pickup device 有权
公开(公告)号：US06551910B2
公开(公告)日：2003-04-22
申请号：US09837252
申请日：2001-04-18
申请人： Masanori Ohashi
发明人： Masanori Ohashi
IPC分类号： H01L21265
CPC分类号： H01L27/14887 , H01L27/14656 , H01L27/14689
摘要： In a method of manufacturing a solid-state image pickup device having a virtual gate structure, in a process of forming a profile of a sensor portion, when ion implantation to form a p+ type layer at a substrate surface side is carried out while the ion implantation direction is tilted with respect to the substrate surface, the ion implantation is divisively carried out at plural times and from multiple ion implantation directions so that the total dose amount is matched, whereby impurities can be implanted into any area of the sensor portion and thus no impurities-unformed area occurs.

5. 发明授权

US06406983B1 Process for the thermal annealing of implantation-doped silicon carbide semiconductors 失效
标题翻译：注入掺杂碳化硅半导体的热退火工艺
公开(公告)号：US06406983B1
公开(公告)日：2002-06-18
申请号：US09538797
申请日：2000-03-30
申请人： Karlheinz Hölzlein , Roland Rupp , Arno Wiedenhofer
发明人： Karlheinz Hölzlein , Roland Rupp , Arno Wiedenhofer
IPC分类号： H01L21265
CPC分类号： H01L21/046 , C30B29/36 , C30B33/00
摘要： A process for the thermal annealing of implantation-doped silicon carbide semiconductors in a gas stream brings practically no carbon to the silicon carbide semiconductor. In one embodiment, a container, a carrier, radiation shields and a baseplate are composed of a metal or a metal compound such as, for example, tantalum or tantalum carbide, at least at locations which come into contact with the gas stream.
摘要翻译：用于气体流中注入掺杂碳化硅半导体的热退火的方法对碳化硅半导体几乎不产生碳。在一个实施例中，至少在与气流接触的位置处，容器，载体，辐射屏蔽和基板由金属或金属化合物例如钽或碳化钽组成。

6. 发明授权

US06368946B1 Manufacture of a semiconductor device with an epitaxial semiconductor zone 失效
标题翻译：具有外延半导体区域的半导体器件的制造
公开(公告)号：US06368946B1
公开(公告)日：2002-04-09
申请号：US08822747
申请日：1997-03-24
申请人： Ronald Dekker , Cornelis E. Timmering , Doede Terpstra , Wiebe B. De Boer
发明人： Ronald Dekker , Cornelis E. Timmering , Doede Terpstra , Wiebe B. De Boer
IPC分类号： H01L21265
CPC分类号： H01L29/66287 , H01L21/02381 , H01L21/0245 , H01L21/02532 , H01L21/02639
摘要： A method of manufacturing a semiconductor device with an epitaxial semiconductor zone, whereby a first layer of insulating material, a first layer of non-monocrystalline silicon, and a second layer of insulating material are provided in that order on a surface of a silicon wafer, a window with a steep wall is etched through the second layer of insulating material and the first layer of non-monocrystalline silicon, the wall of the window is provided with a protective layer, the first insulating layer is selectively etched away within the window and below an edge of the first layer of non-monocrystalline silicon adjoining the window such that both the edge of the first layer of non-monocrystalline silicon itself and the surface of the wafer become exposed within the window and below said edge, semiconductor material is selectively deposited such that the epitaxial semiconductor zone is formed on the exposed surface of the wafer, and an edge of polycrystalline semiconductor material connected to the epitaxial semiconductor zone is formed on the exposed edge of the first layer of non-monocrystalline silicon, an insulating spacer layer is provided on the proctective layer on the wall of the window, and a second layer of non-monocrystalline silicon is deposited. The provision of a top layer of a material on which non-monocrystalline semiconductor material will grow during the selective deposition of the semiconductor material, which top layer is provided on the second layer of insulating material before the selective deposition of the semiconductor material, achieves that the selective deposition process can be better monitored.
摘要翻译：制造具有外延半导体区域的半导体器件的方法，其中第一绝缘材料层，第一非晶硅层和第二绝缘材料层依次设置在硅晶片的表面上，通过绝缘材料的第二层和非单晶硅的第一层蚀刻具有陡峭壁的窗口，窗口的壁设置有保护层，第一绝缘层被选择性地蚀刻在窗口内并在窗口下方邻接窗口的非单晶硅第一层的边缘使得第一层非单晶硅本身的边缘和晶片的表面两者都在窗口内部和所述边缘的下方露出，半导体材料被选择性地沉积如外延半导体区形成在晶片的暴露表面上，并连接多晶半导体材料的边缘在第一非晶硅单层的暴露边缘上形成外延半导体区，在窗口壁上的保护层上提供绝缘间隔层，并沉积第二层非单晶硅。在选择性沉积半导体材料的选择性沉积期间，在半导体材料的选择性沉积之前，提供非单晶半导体材料将在其上生长的材料的顶层，该半导体材料在半导体材料的选择性沉积之前设置在第二绝缘材料层上，可以更好地监测选择性沉积过程。

7. 发明授权

US06362082B1 Methodology for control of short channel effects in MOS transistors 有权
公开(公告)号：US06362082B1
公开(公告)日：2002-03-26
申请号：US09342030
申请日：1999-06-28
申请人： Brian S. Doyle , Brian Roberds
发明人： Brian S. Doyle , Brian Roberds
IPC分类号： H01L21265
CPC分类号： H01L29/0649 , H01L21/26506 , H01L21/26533 , H01L29/0653 , H01L29/7842
摘要： A method of improving short channel effects in a transistor. First, a substance is implanted in a substrate. The substrate is then annealed such that the implanted substance forms at least one void in the substrate. Then, a transistor having a source, a drain, and a channel region is formed on the substrate, wherein the at least one void is in the channel region of the transistor.

8. 发明授权

US06352912B1 Reduction of reverse short channel effects by deep implantation of neutral dopants 有权
标题翻译：通过深度植入中性掺杂剂减少反向短通道效应
公开(公告)号：US06352912B1
公开(公告)日：2002-03-05
申请号：US09539527
申请日：2000-03-30
申请人： Jeffrey Scott Brown , Stephen Scott Furkay , Robert J. Gauthier, Jr. , Dale Warner Martin , James Albert Slinkman
发明人： Jeffrey Scott Brown , Stephen Scott Furkay , Robert J. Gauthier, Jr. , Dale Warner Martin , James Albert Slinkman
IPC分类号： H01L21265
CPC分类号： H01L29/1054 , H01L21/26506 , H01L21/26586 , H01L29/105 , H01L29/1079 , H01L29/66575
摘要： A FET with reduced reverse short channel effects is described, as well as a method to make said FET. Germanium is implanted throughout a semiconductor substrate at an intensity and dose such that a peak ion concentration is created below the source and drain of the FET. The germanium can be implanted prior to gate and source and drain formation, and reduces the reverse short channel effect normally seen in FETs. The short channel effect normally occurring in FETs is not negatively impacted by the germanium implant.
摘要翻译：描述了具有减小的反向短通道效应的FET，以及制造所述FET的方法。以强度和剂量将锗植入整个半导体衬底，使得在FET的源极和漏极之下产生峰值离子浓度。锗可以在栅极和源极和漏极形成之前被植入，并且减少FET中通常看到的反向短沟道效应。通常在FET中发生的短沟道效应不会受到锗植入物的负面影响。

9. 发明授权

US06335264B1 Controlled cleavage thin film separation process using a reusable substrate 有权
标题翻译：使用可重复使用的基材的受控裂解薄膜分离方法
公开(公告)号：US06335264B1
公开(公告)日：2002-01-01
申请号：US09663043
申请日：2000-09-15
申请人： Francois J. Henley , Nathan W. Cheung
发明人： Francois J. Henley , Nathan W. Cheung
IPC分类号： H01L21265
CPC分类号： H01L21/187 , B81C1/0038 , B81C2201/0191 , B81C2201/0192 , H01L21/2007 , H01L21/2236 , H01L21/26506 , H01L21/304 , H01L21/7624 , H01L21/76254 , H01L21/7813 , Y10S117/915 , Y10S156/93 , Y10S438/974 , Y10S438/977 , Y10T156/11 , Y10T156/1158 , Y10T156/19 , Y10T428/21 , Y10T428/24893 , Y10T428/249956
摘要： A technique for forming films of material (12) from a donor substrate (10). The technique has a step of introducing energetic particles (22) through a surface of a donor substrate (10) to a selected depth (20) underneath the surface, where the particles have a relatively high concentration to define donor substrate material (12) above the selected depth. Energy is provided to a selected region of the substrate to cleave a thin film of material from the donor substrate. Particles are introduced again into the donor substrate underneath a fresh surface of the donor substrate. A second thin film of material is then cleaved from the donor substrate.
摘要翻译：一种从供体衬底（10）形成材料（12）的薄膜的技术。该技术具有将能量粒子（22）通过供体衬底（10）的表面引入到表面下方的选定深度（20）的步骤，其中颗粒具有相对高的浓度以限定上述施主衬底材料（12）所选深度。能量被提供到衬底的选定区域以从施主衬底切割材料薄膜。将颗粒再次引入供体底物的供体底物的新鲜表面下方。然后从供体基材上切下第二薄膜材料。

10. 发明授权

US06207515B1 Method of fabricating buried source to shrink chip size in memory array 失效
标题翻译：在存储器阵列中制造掩埋源以收缩芯片尺寸的方法
公开(公告)号：US06207515B1
公开(公告)日：2001-03-27
申请号：US09085611
申请日：1998-05-27
申请人： Chia-Ta Hsieh , Jenn Tsao , Di-Son Kuo , Yai-Fen Lin , Hung-Cheng Sung
发明人： Chia-Ta Hsieh , Jenn Tsao , Di-Son Kuo , Yai-Fen Lin , Hung-Cheng Sung
IPC分类号： H01L21265
CPC分类号： H01L29/0847 , H01L21/76895 , H01L27/1052 , H01L27/112 , H01L29/0649 , H01L29/66636
摘要： A method is provided for forming buried source line in semiconductor devices. It is known in the art to form buried contacts on the surface of a semiconductor substrate. The present invention discloses a method of fabricating a semiconductor device, particularly a memory cell, having both the source region and the source line buried within the substrate. The source line is formed in a trench in the substrate over the source region. The trench walls are augmented with voltage anti-punch-through protection. The trench also provides the attendant advantages of extended sidewall area, smaller sheet resistance, and yet smaller cell area, therefore, smaller chip size, and faster access time as claimed in the embodiments of this invention. The buried source disclosed here is integrated with source line which is also buried within the substrate.
摘要翻译：提供一种用于在半导体器件中形成掩埋源极线的方法。在本领域中已知在半导体衬底的表面上形成掩埋触点。本发明公开了一种制造半导体器件的方法，特别是具有埋入衬底内的源极区和源极线两者的存储单元。源极线形成在源极区域上的衬底中的沟槽中。沟槽壁增强了电压抗穿透保护。沟槽还提供了延伸的侧壁区域，较小的薄层电阻以及更小的单元面积，因此，更小的芯片尺寸和更快的访问时间，如本发明的实施例所要求的优点。这里公开的掩埋源与源极线集成，该源极线也被埋在衬底内。

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