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1. 发明授权

US5650763A Non-linear reciprocating device 失效
标题翻译：非线性往复运动装置
公开(公告)号：US5650763A
公开(公告)日：1997-07-22
申请号：US657126
申请日：1996-06-03
申请人： John M. McKee , Gerald Eugene Brinkley , Philip P. Macnak , James Gregory Mittel
发明人： John M. McKee , Gerald Eugene Brinkley , Philip P. Macnak , James Gregory Mittel
IPC分类号： B06B1/04 , G08B6/00 , H04B3/36 , H04Q1/30
CPC分类号： G08B6/00
摘要： A non-linear reciprocating device (100, 200) includes an armature (12) including non-linear suspension members (14, 16); a compliant contactor (50, 72), coupled to a power source (BT), and further coupled to the armature (12) for generating an interrupting signal; an electromagnetic driver (25), coupled to the non-linear suspension members (14, 16) for effecting an electromagnetic field in response to the interrupting signal; and a magnetic motional mass (18) suspended by the non-linear suspension members (14, 16), and coupled to the electromagnetic field for generating a reciprocating movement of the magnetic motional mass (18) which is transformed through the non-linear suspension members (14, 16) and the electromagnetic driver (25) into tactile energy. The compliant contactor can be either a single pole compliant contactor (50) or double pole compliant contactor (72).
摘要翻译：非线性往复运动装置（100,200）包括包括非线性悬挂构件（14,16）的电枢（12）; 耦合到电源（BT）的柔性接触器（50,72），并且还耦合到电枢（12）以产生中断信号; 耦合到所述非线性悬挂构件（14,16）的电磁驱动器（25），用于响应于所述中断信号实现电磁场; 以及由所述非线性悬挂构件（14,16）悬挂的磁性运动质量块（18），并且耦合到所述电磁场以产生所述磁运动质量块（18）的往复运动，所述磁运动质量块（18）通过所述非线性悬架成员（14,16）和电磁驱动器（25）成为触觉能量。柔性接触器可以是单极兼容接触器（50）或双极兼容接触器（72）。

2. 发明授权

US5828295A Mode tracking transducer driver for a non-linear transducer 失效
标题翻译：用于非线性传感器的模式跟踪传感器驱动器
公开(公告)号：US5828295A
公开(公告)日：1998-10-27
申请号：US707543
申请日：1996-09-04
申请人： James Gregory Mittel , John M. McKee , Darrell Curtis Weber
发明人： James Gregory Mittel , John M. McKee , Darrell Curtis Weber
IPC分类号： B06B1/04 , G08B6/00 , H04B3/36 , H04Q1/30
CPC分类号： G08B6/00
摘要： A mode tracking transducer driver (100) for a non-linear electromagnetic transducer (102) includes a voltage controlled oscillator (104) coupled within a phase lock loop to a transducer driver (106) and a mode detector (112, 108). The voltage controlled oscillator (104) generates a variable frequency output signal, and is responsive to a frequency control signal for controlling the frequency of the output signal. The transducer driver (106) generates a transducer drive signal (502) which is coupled to the non-linear electromagnetic transducer (102) to generate a tactile alert. The mode detector (112, 108) detects a mode change between at least the first operating mode and the second operating mode of the non-linear electromagnetic transducer (102), and in response thereto generates the frequency control signal (118) which establishes a quasi-resonant frequency (204) at which the tactile energy delivered by the non-linear electromagnetic transducer (102) is maximized.
摘要翻译：用于非线性电磁换能器（102）的模式跟踪传感器驱动器（100）包括耦合在相位锁定环内的压控振荡器（104）到换能器驱动器（106）和模式检测器（112,108）。压控振荡器（104）产生可变频率输出信号，并响应于控制输出信号频率的频率控制信号。换能器驱动器（106）产生耦合到非线性电磁换能器（102）以产生触觉警报的换能器驱动信号（502）。模式检测器（112,108）检测非线性电磁换能器（102）的至少第一操作模式和第二操作模式之间的模式变化，响应于此产生频率控制信号（118），其建立由非线性电磁换能器（102）传递的触觉能量最大化的准谐振频率（204）。

3. 发明授权

US5841822A Band-pass sigma-delta converter and commutating filter therefor 失效
标题翻译：带通Σ-Δ转换器和换向滤波器
公开(公告)号：US5841822A
公开(公告)日：1998-11-24
申请号：US982179
申请日：1997-12-01
申请人： James Gregory Mittel , Raymond Louis Barrett, Jr. , Walter Davis
发明人： James Gregory Mittel , Raymond Louis Barrett, Jr. , Walter Davis
IPC分类号： H03H19/00 , H03M3/02 , H04B1/10
CPC分类号： H03H19/004 , H03M3/404 , H03M3/43 , H03M3/454
摘要： A communication receiver (600) utilizes a band-pass sigma-delta converter (100) for receiving a radio signal. The band-pass sigma-delta converter (100) includes a comparator (106) coupled to an adder-filter (101) for making a comparison between a predetermined reference level (110) and an intermediate signal (125), and for generating a comparison result signal (114) responsive to the comparison. A storage element (108) is used for storing the comparison result signal (114) for a predetermined delay period, thereby producing a clocked output signal (118). The adder-filter (101) is coupled to an analog signal (103) and to the clocked output signal (118) for subtracting the clocked output signal (118) from the analog signal (103) to produce a difference signal (120) that is filtered by a commutating filter (400) for generating the intermediate signal (125) responsive to the difference signal (120).
摘要翻译：通信接收机（600）利用带通Σ-Δ转换器（100）来接收无线电信号。带通Σ-Δ转换器（100）包括耦合到加法器滤波器（101）的比较器（106），用于在预定参考电平（110）和中间信号（125）之间进行比较，并且用于产生比较结果信号（114）响应于比较。存储元件（108）用于在预定的延迟周期内存储比较结果信号（114），从而产生时钟输出信号（118）。加法器滤波器（101）耦合到模拟信号（103）和时钟输出信号（118），用于从模拟信号（103）中减去时钟输出信号（118）以产生差分信号（120），其中，通过换向滤波器（400）进行滤波，用于响应差分信号（120）产生中间信号（125）。

4. 发明授权

US5789987A Low-noise frequency synthesizer 失效
标题翻译：低噪音频率合成器
公开(公告)号：US5789987A
公开(公告)日：1998-08-04
申请号：US589362
申请日：1996-01-22
申请人： James Gregory Mittel , Scott Humphreys
发明人： James Gregory Mittel , Scott Humphreys
IPC分类号： H03L7/07 , H03L7/093 , H03L7/06 , H03C1/06
CPC分类号： H03L7/0805 , H03L7/07 , H03L7/093
摘要： A frequency synthesizer (100) is utilized for producing an output signal (124) which is phase locked to a reference signal (110) operating at a reference frequency. The frequency synthesizer (100) comprises a main phase lock loop (PLL) (102), and a tracker PLL (128). The main PLL (102) includes a phase detector (112), two frequency dividers (108, 126), a loop filter (116), a notch filter (118), and a controlled oscillator (122). The tracker PLL (128) phase locks to the reference signal (110), and biases the notch filter (118) in order to maintain an accurate lock on the notch frequency which is proportional to the reference frequency. All circuits are integrated in the same monolithic device in order to track parametric tolerances such as transconductances of the operational transconductance devices included in the tracker PLL (128) and the notch filter (118).
摘要翻译：频率合成器（100）用于产生与参考频率工作的参考信号（110）相位锁定的输出信号（124）。频率合成器（100）包括主锁相环（PLL）（102）和跟踪器PLL（128）。主PLL（102）包括相位检测器（112），两个分频器（108,126），环路滤波器（116），陷波滤波器（118）和受控振荡器（122）。跟踪器PLL（128）相锁定到参考信号（110），并且偏置陷波滤波器（118），以便保持与参考频率成比例的陷波频率的准确锁定。所有电路都集成在相同的单片设备中，以便跟踪参数公差，例如包括在跟踪器PLL（128）和陷波滤波器（118）中的工作跨导器件的跨导。

5. 发明授权

US06356142B1 Digital filter tune loop 有权
标题翻译：数字滤波器调谐回路
公开(公告)号：US06356142B1
公开(公告)日：2002-03-12
申请号：US09666037
申请日：2000-09-20
申请人： James Gregory Mittel
发明人： James Gregory Mittel
IPC分类号： H03K500
CPC分类号： H03J3/08 , H03J3/16 , H03J2200/07 , H03L7/089
摘要： A digital tuning circuit (100) for a filter (120) has a filter input and a filter output and employs a switchable element array (122). The filter includes a tuning signal generator (104) that generates a tuning signal (106) that is delivered to the filter input and a clock circuit (102) that generates a periodic stream of pulses. The digital tuning circuit includes a delay circuit (110), a phase comparator (130) and an integrating up-down counter (140). The delay circuit (110) is responsive to the tuning signal generator (104) and delays the tuning signal (106) by a predetermined amount corresponding to the nominal delay through the filter (120). The integrating up-down counter (140) counts pulses in a first direction when the phase comparator (130) generates the first value and counts pulses in a second direction, opposite from the first direction, when the phase comparator (130) generates the second value. The integrating up-down counter (140) generates a binary word having a value corresponding to a number of counts that the integrating up-down counter (140) performs and is coupled to the switchable element array (122) so that a number of switchable elements is electrically coupled to the filter (120). The number of switchable elements corresponds to the value of the binary word.
摘要翻译：用于滤波器（120）的数字调谐电路（100）具有滤波器输入和滤波器输出，并采用可切换元件阵列（122）。滤波器包括调谐信号发生器（104），其产生被传送到滤波器输入端的调谐信号（106）和产生周期性脉冲流的时钟电路（102）。数字调谐电路包括延迟电路（110），相位比较器（130）和积分递减计数器（140）。延迟电路（110）响应于调谐信号发生器（104），并将调谐信号（106）延迟与通过滤波器（120）的标称延迟相对应的预定量。当相位比较器（130）生成第一值时，积分递减计数器（140）在第一方向上对脉冲进行计数，并且当相位比较器（130）产生第二值时，在与第一方向相反的第二方向上计数脉冲值。积分递减计数器（140）产生具有对应于积分递减计数器（140）所执行并被耦合到可切换元件阵列（122）的计数数量的值的二进制字，使得可切换的数量元件电耦合到过滤器（120）。可切换元件的数量对应于二进制字的值。

6. 发明授权

US06839387B1 Self-dithering sigma-delta converter and communication device incorporating same 失效
标题翻译：自抖动Σ-Δ转换器和包含其的通信装置
公开(公告)号：US06839387B1
公开(公告)日：2005-01-04
申请号：US09517113
申请日：2000-03-07
申请人： James Gregory Mittel
发明人： James Gregory Mittel
IPC分类号： H03M3/00 , H03M3/02 , H04B14/06
CPC分类号： H03M3/328 , H03M3/43 , H03M3/454 , H03M3/458 , H03M3/50 , H03M7/3008 , H03M7/3028 , H03M7/304
摘要： A sigma-delta converter operates over a predetermined bandwidth and includes a feedback loop comprising a forward path and a feedback path. The forward path includes, in series, a summer, a filter, and a comparator. The comparator produces an output signal that is fed back to a negative input of the summer via the feedback path. The sigma-delta converter also includes at least one instability generator positioned in the forward path and/or the feedback path. The instability generator generates one or more out-of-band instabilities in the feedback loop to substantially improve the in-band signal-to-noise performance of the converter for input signal amplitudes near a low end of the converter's dynamic range. The converter may be employed as an A/D converter, a D/D converter, or a D/A converter in a receiver and/or a transmitter of a wireless communication device.
摘要翻译： Σ-Δ转换器在预定带宽上工作，并且包括包括正向路径和反馈路径的反馈回路。正向路径包括一个夏季，一个滤波器和一个比较器。比较器产生经由反馈路径反馈到加法器的负输入端的输出信号。 Σ-Δ转换器还包括位于正向路径和/或反馈路径中的至少一个不稳定性发生器。不稳定性发生器在反馈回路中产生一个或多个带外不稳定性，以基本上改善转换器对于转换器动态范围的低端附近的输入信号幅度的带内信噪比性能。转换器可以用作无线通信设备的接收机和/或发射机中的A / D转换器，D / D转换器或D / A转换器。

7. 发明授权

US5787125A Apparatus for deriving in-phase and quadrature-phase baseband signals from a communication signal 失效
标题翻译：用于从通信信号导出同相和正交相位基带信号的装置
公开(公告)号：US5787125A
公开(公告)日：1998-07-28
申请号：US643646
申请日：1996-05-06
申请人： James Gregory Mittel
发明人： James Gregory Mittel
IPC分类号： H03C3/40 , H03D3/00 , H04L27/22 , H04L27/38
CPC分类号： H04L27/38 , H03C3/40 , H04L27/22 , H03D3/006 , H03D3/007
摘要： In-phase (I) and quadrature-phase (Q) baseband signals (312, 314) are derived from a digitized signal (318) having a sampling rate. The digitized signal is band pass filtered (604) to produce a band passed signal (320), and the band passed signal is delayed (606) to produce a delayed band passed signal (322). The band passed signal and the delayed band passed signal are decimated (608) by a predetermined amount to produce, respectively, a decimated signal (328) and a decimated delayed signal (330). The decimated signal and the decimated delayed signal are low pass filtered (610) to produce, respectively, the I and Q baseband signals.
摘要翻译：从具有采样率的数字化信号（318）导出同相（I）和正交相（Q）基带信号（312,314）。数字化信号被带通滤波（604）以产生带通信号（320），并且带通信号被延迟（606）以产生延迟的带通信号（322）。频带通过信号，延迟频带通过信号被抽取（608）预定量，以分别产生抽取信号（328）和抽取延迟信号（330）。抽取信号和抽取延迟信号被低通滤波（610），分别产生I和Q基带信号。

8. 发明授权

US5768315A Band-pass sigma-delta converter and commutating filter therefor 失效
公开(公告)号：US5768315A
公开(公告)日：1998-06-16
申请号：US684716
申请日：1996-07-22
申请人： James Gregory Mittel , Raymond Louis Barrett, Jr. , Walter Davis
发明人： James Gregory Mittel , Raymond Louis Barrett, Jr. , Walter Davis
IPC分类号： H03H19/00 , H03M3/02 , H04B14/06
CPC分类号： H03H19/004 , H03M3/404 , H03M3/43 , H03M3/454
摘要： A communication receiver (600) utilizes a band-pass sigma-delta converter (100) for receiving a radio signal. The band-pass sigma-delta converter (100) includes a comparator (106) coupled to an adder-filter (101) for making a comparison between a predetermined reference level (110) and an intermediate signal (125), and for generating a comparison result signal (114) responsive to the comparison. A storage element (108) is used for storing the comparison result signal (114) for a predetermined delay period, thereby producing a clocked output signal (118). The adder-filter (101) is coupled to an analog signal (103) and to the clocked output signal (118) for subtracting the clocked output signal (118) from the analog signal (103) to produce a difference signal (120) that is filtered by a commutating filter (400) for generating the intermediate signal (125) responsive to the difference signal (120).

9. 发明授权

US5734974A Selective call receivers with stepwise variable gain control 失效
标题翻译：具有逐步变量增益控制的选择性呼叫接收机
公开(公告)号：US5734974A
公开(公告)日：1998-03-31
申请号：US625435
申请日：1996-03-27
申请人： Edgar Herbert Callaway, Jr. , James Gregory Mittel , Vance Howard Peterson , Burkhard Dick , Knud Holtvoeth , Wilfried Knop
发明人： Edgar Herbert Callaway, Jr. , James Gregory Mittel , Vance Howard Peterson , Burkhard Dick , Knud Holtvoeth , Wilfried Knop
IPC分类号： H03G1/00 , H03G3/20 , H03G3/30 , H04B1/16 , H04B1/06
CPC分类号： H03G3/3073 , H03G1/0088
摘要： A receiver (100) for receiving an input signal and generating an output signal therefrom has a switchable gain circuit (104) with a stepwise variable gain control (118), a local oscillator (106) and an automatic gain control (AGC) detector (114) with a response for detecting a level of the output signal and generating an AGC signal indicative of the level of the output signal and a state machine (116) being responsive to the AGC signal generating a control signal at the stepwise variable gain control to increase or decrease a gain of the switchable gain circuit in discrete stepwise steps.
摘要翻译：一种用于接收输入信号并从其产生输出信号的接收器（100）具有带有逐步可变增益控制（118），本地振荡器（106）和自动增益控制（AGC）检测器（118）的可切换增益电路（104） 114），具有用于检测输出信号的电平并产生指示输出信号的电平的AGC信号的响应，以及状态机（116）响应于在步进可变增益控制下产生控制信号的AGC信号，在离散步进步骤中增加或减少可切换增益电路的增益。

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