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1. 发明授权

US5841822A Band-pass sigma-delta converter and commutating filter therefor 失效
标题翻译：带通Σ-Δ转换器和换向滤波器
公开(公告)号：US5841822A
公开(公告)日：1998-11-24
申请号：US982179
申请日：1997-12-01
申请人： James Gregory Mittel , Raymond Louis Barrett, Jr. , Walter Davis
发明人： James Gregory Mittel , Raymond Louis Barrett, Jr. , Walter Davis
IPC分类号： H03H19/00 , H03M3/02 , H04B1/10
CPC分类号： H03H19/004 , H03M3/404 , H03M3/43 , H03M3/454
摘要： A communication receiver (600) utilizes a band-pass sigma-delta converter (100) for receiving a radio signal. The band-pass sigma-delta converter (100) includes a comparator (106) coupled to an adder-filter (101) for making a comparison between a predetermined reference level (110) and an intermediate signal (125), and for generating a comparison result signal (114) responsive to the comparison. A storage element (108) is used for storing the comparison result signal (114) for a predetermined delay period, thereby producing a clocked output signal (118). The adder-filter (101) is coupled to an analog signal (103) and to the clocked output signal (118) for subtracting the clocked output signal (118) from the analog signal (103) to produce a difference signal (120) that is filtered by a commutating filter (400) for generating the intermediate signal (125) responsive to the difference signal (120).
摘要翻译：通信接收机（600）利用带通Σ-Δ转换器（100）来接收无线电信号。带通Σ-Δ转换器（100）包括耦合到加法器滤波器（101）的比较器（106），用于在预定参考电平（110）和中间信号（125）之间进行比较，并且用于产生比较结果信号（114）响应于比较。存储元件（108）用于在预定的延迟周期内存储比较结果信号（114），从而产生时钟输出信号（118）。加法器滤波器（101）耦合到模拟信号（103）和时钟输出信号（118），用于从模拟信号（103）中减去时钟输出信号（118）以产生差分信号（120），其中，通过换向滤波器（400）进行滤波，用于响应差分信号（120）产生中间信号（125）。

2. 发明授权

US5768315A Band-pass sigma-delta converter and commutating filter therefor 失效
公开(公告)号：US5768315A
公开(公告)日：1998-06-16
申请号：US684716
申请日：1996-07-22
申请人： James Gregory Mittel , Raymond Louis Barrett, Jr. , Walter Davis
发明人： James Gregory Mittel , Raymond Louis Barrett, Jr. , Walter Davis
IPC分类号： H03H19/00 , H03M3/02 , H04B14/06
CPC分类号： H03H19/004 , H03M3/404 , H03M3/43 , H03M3/454
摘要： A communication receiver (600) utilizes a band-pass sigma-delta converter (100) for receiving a radio signal. The band-pass sigma-delta converter (100) includes a comparator (106) coupled to an adder-filter (101) for making a comparison between a predetermined reference level (110) and an intermediate signal (125), and for generating a comparison result signal (114) responsive to the comparison. A storage element (108) is used for storing the comparison result signal (114) for a predetermined delay period, thereby producing a clocked output signal (118). The adder-filter (101) is coupled to an analog signal (103) and to the clocked output signal (118) for subtracting the clocked output signal (118) from the analog signal (103) to produce a difference signal (120) that is filtered by a commutating filter (400) for generating the intermediate signal (125) responsive to the difference signal (120).

3. 发明授权

US5880619A Low power precision voltage splitter 失效
标题翻译：低功率精密分压器
公开(公告)号：US5880619A
公开(公告)日：1999-03-09
申请号：US990548
申请日：1997-12-15
申请人： Raymond Louis Barrett, Jr. , Barry W. Herold , Grazyna A. Pajunen
发明人： Raymond Louis Barrett, Jr. , Barry W. Herold , Grazyna A. Pajunen
IPC分类号： G05F3/24 , G05F1/10 , G05F3/316
CPC分类号： G05F3/247
摘要： A voltage splitter circuit (100) that generates a one-half supply voltage includes a first switched operational transconductance amplifier (switched OTA) (120), a first transistor switch (110) that is controlled by a first clock signal (108) to periodically switch a first supply voltage (135) to a non-inverting input (118) of the first switched OTA, a second switched OTA (115), a second transistor switch (105) that is controlled by an inverted second clock signal (104) to periodically switch a second supply voltage (130) to a non-inverting input (114) of the second switched OTA, a commutating capacitor (112) coupled between the non-inverting input of the first switched OTA and the non-inverting input of the second switched OTA, a first filter capacitor (145) coupled to an output (121) of the first switched OTA, a second filter capacitor (140) coupled to an output (116) of the second switched OTA, and a third switched OTA (125). The first and second clock signals are non-overlapping.
摘要翻译：产生二分之一电源电压的分压器电路（100）包括第一开关操作跨导放大器（开关OTA）（120），由第一时钟信号（108）控制的第一晶体管开关（110）将第一电源电压（135）切换到第一开关OTA的非反相输入端（118），第二开关OTA（115），由反相第二时钟信号（104）控制的第二晶体管开关（105）周期性地将第二电源电压（130）切换到第二开关OTA的非反相输入端（114）;耦合在第一开关OTA的非反相输入端和第一开关OTA的非反相输入端之间的整流电容器（112）第二开关OTA，耦合到第一开关OTA的输出（121）的第一滤波电容器（145），耦合到第二开关OTA的输出端（116）的第二滤波电容器（140）和第三开关OTA （125）。第一和第二时钟信号是不重叠的。

4. 发明授权

US5793825A Method and apparatus for extending an operating frequency range of an instantaneous phase-frequency detector 失效
标题翻译：用于延长瞬时相位频率检测器的工作频率范围的方法和装置
公开(公告)号：US5793825A
公开(公告)日：1998-08-11
申请号：US610034
申请日：1996-03-04
申请人： Scott Robert Humphreys , Raymond Louis Barrett, Jr. , Barry W. Herold
发明人： Scott Robert Humphreys , Raymond Louis Barrett, Jr. , Barry W. Herold
IPC分类号： H03L7/093 , H03D3/24 , H03L7/00 , H04L27/14
CPC分类号： H03L7/093
摘要： A method is used by a detector (102) for extending the operating frequency range of a phase lock loop (100). The detector (102) detects a phase-frequency difference between a reference signal (109) and a generated signal (108) of the phase lock loop (100). The detector (102) includes a divider (202) for counting transitions of the generated signal (108) and a logic element (204) and counter (212) for detecting when the frequency of the generated signal (108) is such that the divider (202) operates outside its linear frequency range in relation to a predetermined transition of the reference signal (109). The detector (102) further includes a register (206) for recording a phase value of the divider (202) coincident with the predetermined transition, or a constant phase value (304, 306) when the frequency of the generated signal (108) is operating outside of the linear range of the divider (202).
摘要翻译：检测器（102）使用一种方法来扩展锁相环（100）的工作频率范围。检测器（102）检测参考信号（109）和锁相环（100）的产生信号（108）之间的相位 - 频率差。检测器（102）包括用于对生成的信号（108）和逻辑元件（204）和计数器（212）的转换进行计数的分频器（202），用于检测所产生的信号（108）的频率何时使分频器（202）相对于参考信号（109）的预定转换在其线性频率范围之外操作。检测器（102）还包括一个寄存器（206），用于当所产生的信号（108）的频率为（108）为...时，用于记录与预定转换一致的分频器的相位值或恒定相位值（304,306）操作在分压器（202）的线性范围之外。

5. 发明授权

US10869519B2 MEMS valve actuator system and method 有权
公开(公告)号：US10869519B2
公开(公告)日：2020-12-22
申请号：US15648021
申请日：2017-07-12
申请人： Raymond Louis Barrett, Jr.
发明人： Raymond Louis Barrett, Jr.
IPC分类号： A42B3/12 , F16K31/00 , F16K99/00 , A42B3/28 , A61B5/00 , A61B5/11
CPC分类号： A42B3/122 , A42B3/121 , A42B3/281 , A61B5/4064 , F16K31/004 , F16K99/0048 , A61B5/002 , A61B5/1114 , A61B5/6803 , A61B2503/10 , A61B2562/0219 , A61B2562/04 , F16K2099/0082
摘要： A micro-electro-mechanical (MEMS) exhaust valve-based impact attenuating fluid filled cell for use in cushioning impact and decelerating of a wearer's body portion (e.g. head, shoulder, torso, etc.) after an impact. In combination with the use of accelerometers, pressure sensors, location and other electronics supply signals to a microcontroller, the controlled opening/closing of said exhaust valve (resulting in the expelling of said fluids with an optional combination with cell refill means) when certain parameters exceed a threshold. Individuals who engage in activities that carry a risk of injury to the head from impact in the normal course of the activity could, in combination with regular exams, benefit from a system that produces and updates a kinematic 3D model of the individual's head, including brain matter, cerebrospinal fluid paths, arterial and venous blood flow pathways, as well as the skull, supporting connective tissues and other biological structures in the head suitable for interaction with exogenous stimuli prepared from hypothetical or actual recorded impact events.

6. 发明授权

US5640681A Boot-strapped cascode current mirror 失效
标题翻译：引导带状共源共栅电流镜
公开(公告)号：US5640681A
公开(公告)日：1997-06-17
申请号：US149886
申请日：1993-11-10
申请人： Raymond Louis Barrett, Jr. , Barry Wayne Herold , Grazyna A. Pajunen
发明人： Raymond Louis Barrett, Jr. , Barry Wayne Herold , Grazyna A. Pajunen
IPC分类号： G05F3/26 , H04B7/00 , G05F3/16
CPC分类号： G05F3/262
摘要： A cascode current mirror circuit includes a cascode connected input stage (401) that operates to conduct an input current (400) in response to an input voltage of an input signal coupled to an effective transconductance of the cascode connected input stage (401). An input mirroring transistor (404) operates to control a mirror reference current (406) in response to the input voltage of the input signal. A diode connected transistor (409) coupled to a second control node of the cascode connected input stage (410) generates a control bias proportional to the mirror reference current (406) and to the input signal. A cascode connected output stage (411) has a first control node (413) coupled to the input signal and a second control node (414) coupled to the diode connected transistor (409) and the second control node (410) of the cascode connected input stage (401) for establishing an output current (415) that is substantially equivalent to the input current (400).
摘要翻译：共源共栅电流镜电路包括共源共栅连接的输入级（401），其操作以响应耦合到共源共栅连接的输入级（401）的有效跨导的输入信号的输入电压来传导输入电流（400）。输入镜像晶体管（404）用于响应于输入信号的输入电压来控制镜参考电流（406）。耦合到共源共栅连接的输入级（410）的第二控制节点的二极管连接晶体管（409）产生与镜参考电流（406）成比例的控制偏置和输入信号。级联连接的输出级（411）具有耦合到输入信号的第一控制节点（413）和耦合到二极管连接的晶体管（409）的第二控制节点（414）和连接的共源共栅的第二控制节点（410）输入级（401），用于建立基本上等于输入电流（400）的输出电流（415）。

7. 发明授权

US5754598A Method and apparatus for controlling a phase lock loop 失效
标题翻译：用于控制锁相环的方法和装置
公开(公告)号：US5754598A
公开(公告)日：1998-05-19
申请号：US652054
申请日：1996-05-23
申请人： Raymond Louis Barrett, Jr. , Barry W. Herold , Grazyna Anna Pajunen
发明人： Raymond Louis Barrett, Jr. , Barry W. Herold , Grazyna Anna Pajunen
IPC分类号： H03L7/089 , H03L7/093 , H03L7/183 , H03D3/18 , H03D3/24
CPC分类号： H03L7/183 , H03L7/089 , H03L7/093
摘要： A phase lock loop of a synthesizer (143) is controlled by applying (506) modern optimal control techniques for a predetermined period in a computing engine (222), in response to an error being introduced into a signal of the phase lock loop, and by utilizing (510) classical control techniques for controlling the phase lock loop after the predetermined period.
摘要翻译：响应于引入到锁相环的信号中的误差，在计算引擎（222）中应用（506）现有的最优控制技术来控制合成器（143）的锁相环，并且通过利用（510）经典控制技术来控制预定时段之后的锁相环。

8. 发明授权

US5651037A Apparatus for preforming discrete-time analog queuing and computing in a communication system 失效
标题翻译：用于在通信系统中预处理离散时间模拟排队和计算的装置
公开(公告)号：US5651037A
公开(公告)日：1997-07-22
申请号：US538930
申请日：1995-10-04
申请人： Raymond Louis Barrett, Jr. , Barry W. Herold , Grazyna Anna Pajunen
发明人： Raymond Louis Barrett, Jr. , Barry W. Herold , Grazyna Anna Pajunen
IPC分类号： F02B75/02 , H03J1/00 , H03D3/24
CPC分类号： H03J1/0008 , F02B2075/027
摘要： A communication receiver (100) utilizing a synthesizer (143) employs a discrete-time phase locked loop which includes a reference oscillator (135), a phase error detector (202), a discrete-time analog computing element (206), an integrator (210), a controlled frequency generator (211, 212), and a frequency divider (214). The discrete-time analog computing element implements a discrete-time analog lead-lag network circuit. This circuit includes a clock and logic circuit (216), at least one discrete-time analog queuing element (218), and an analog computing engine (222). The queuing element (218) includes N analog signal lines, N analog storage lines, N control lines, and N.sup.2 controllable switches. Each controllable switch is coupled between each of the N analog signal lines and each of the N analog storage lines. In addition, N charge storage elements are coupled between each of the N analog storage lines and a common circuit node. The N control lines control the controllable switches in a predetermined sequence.
摘要翻译：利用合成器（143）的通信接收机（100）采用离散时间锁相环，其包括参考振荡器（135），相位误差检测器（202），离散时间模拟计算元件（206），积分器（210），受控频率发生器（211,212）和分频器（214）。离散时间模拟计算元件实现离散时间模拟超前延迟网络电路。该电路包括时钟和逻辑电路（216），至少一个离散时间模拟排队元件（218）和模拟计算引擎（222）。排队元件（218）包括N个模拟信号线，N个模拟存储线，N个控制线和N2个可控开关。每个可控开关耦合在N个模拟信号线和N个模拟存储线中的每一个之间。此外，N个电荷存储元件耦合在N个模拟存储线中的每一个和公共电路节点之间。 N个控制线以预定的顺序控制可控开关。

9. 发明授权

US5644743A Hybrid analog-digital phase error detector 失效
标题翻译：混合模拟数字相位误差检测器
公开(公告)号：US5644743A
公开(公告)日：1997-07-01
申请号：US567387
申请日：1995-12-04
申请人： Raymond Louis Barrett, Jr. , Barry W. Herold , Grazyna Anna Pajunen , Walter L. Davis
发明人： Raymond Louis Barrett, Jr. , Barry W. Herold , Grazyna Anna Pajunen , Walter L. Davis
IPC分类号： H03D13/00 , H03L7/087 , H03D3/24
CPC分类号： H03L7/087 , H03D13/00
摘要： A hybrid analog-digital phase error detector (107) is utilized for detecting a phase error between first and second clock signals (132, 104). Digital and analog phase error detectors (108, 116) are connected to the first and second clock signals (132, 104), and are utilized for producing digital and analog phase error values (110, 118). The digital and analog controllers (112, 120) connected to the digital and analog phase error detectors (108, 116) execute digital and analog control algorithms based on the digital and analog phase error values (110, 118) to produce digital and analog control signals (114, 122). A summer (124) connected to the outputs of the digital and analog controllers (112, 120) combines the analog control signal (122) and the digital control signal (114) to produce a composite control signal (126) representing the phase error.
摘要翻译：混合模拟数字相位误差检测器（107）用于检测第一和第二时钟信号（132,104）之间的相位误差。数字和模拟相位误差检测器（108,116）连接到第一和第二时钟信号（132,104），并用于产生数字和模拟相位误差值（110,118）。连接到数字和模拟相位误差检测器（108,116）的数字和模拟控制器（112,120）基于数字和模拟相位误差值（110,118）执行数字和模拟控制算法，以产生数字和模拟控制信号（114,122）。连接到数字和模拟控制器（112,120）的输出的加法器（124）组合模拟控制信号（122）和数字控制信号（114）以产生表示相位误差的复合控制信号（126）。

10. 发明授权

US06275540B1 Selective call receiver having an apparatus for modifying an analog signal to a digital signal and method therefor 失效
标题翻译：具有用于将模拟信号修改为数字信号的装置的选择性呼叫接收机及其方法
公开(公告)号：US06275540B1
公开(公告)日：2001-08-14
申请号：US08941913
申请日：1997-10-01
申请人： Raymond Louis Barrett, Jr. , James G. Mittel , Barry W. Herold
发明人： Raymond Louis Barrett, Jr. , James G. Mittel , Barry W. Herold
IPC分类号： H04L2706
CPC分类号： H04B1/0003 , H03M3/40 , H03M3/43 , H03M3/456 , H04B1/30
摘要： A selective call receiver (500) includes a radio receiver (501) and a processor (508). The radio receiver includes an antenna (502), a combination circuit (204), a bandpass filter (208), mixers (212, 214), analog-to-digital converters (222, 224), digital mixers (234, 236), a second combination circuit (242), and a digital-to-analog converter (246). The combination circuit receives an analog signal from the antenna and combines the same with an analog feedback signal generated by the digital-to-analog converter. The bandpass filter filters the output of the combination circuit and supplies its output to the mixers which down-convert the signal to baseband signals. These signals are modified by the analog-to-digital converters to digital signals which are up-converted by the digital mixers. The outputs of the digital mixers are combined by the second combination circuit to a digital output that is modified by the digital-to-analog converter to the analog feedback signal.
摘要翻译：选呼接收机（500）包括无线接收机（501）和处理器（508）。无线电接收机包括天线（502），组合电路（204），带通滤波器（208），混频器（212,214），模拟 - 数字转换器（222,224），数字混频器（234,236），第二组合电路（242）和数模转换器（246）。组合电路从天线接收模拟信号，并将其与数模转换器产生的模拟反馈信号相组合。带通滤波器对组合电路的输出进行滤波，并将其输出提供给将信号下变频为基带信号的混频器。这些信号被模数转换器修改为由数字混频器进行上变频的数字信号。数字混频器的输出由第二组合电路组合到由数模转换器修改为模拟反馈信号的数字输出。

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