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1. 发明授权

US5789987A Low-noise frequency synthesizer 失效
标题翻译：低噪音频率合成器
公开(公告)号：US5789987A
公开(公告)日：1998-08-04
申请号：US589362
申请日：1996-01-22
申请人： James Gregory Mittel , Scott Humphreys
发明人： James Gregory Mittel , Scott Humphreys
IPC分类号： H03L7/07 , H03L7/093 , H03L7/06 , H03C1/06
CPC分类号： H03L7/0805 , H03L7/07 , H03L7/093
摘要： A frequency synthesizer (100) is utilized for producing an output signal (124) which is phase locked to a reference signal (110) operating at a reference frequency. The frequency synthesizer (100) comprises a main phase lock loop (PLL) (102), and a tracker PLL (128). The main PLL (102) includes a phase detector (112), two frequency dividers (108, 126), a loop filter (116), a notch filter (118), and a controlled oscillator (122). The tracker PLL (128) phase locks to the reference signal (110), and biases the notch filter (118) in order to maintain an accurate lock on the notch frequency which is proportional to the reference frequency. All circuits are integrated in the same monolithic device in order to track parametric tolerances such as transconductances of the operational transconductance devices included in the tracker PLL (128) and the notch filter (118).
摘要翻译：频率合成器（100）用于产生与参考频率工作的参考信号（110）相位锁定的输出信号（124）。频率合成器（100）包括主锁相环（PLL）（102）和跟踪器PLL（128）。主PLL（102）包括相位检测器（112），两个分频器（108,126），环路滤波器（116），陷波滤波器（118）和受控振荡器（122）。跟踪器PLL（128）相锁定到参考信号（110），并且偏置陷波滤波器（118），以便保持与参考频率成比例的陷波频率的准确锁定。所有电路都集成在相同的单片设备中，以便跟踪参数公差，例如包括在跟踪器PLL（128）和陷波滤波器（118）中的工作跨导器件的跨导。

2. 发明授权

US07064591B1 Coarse tuning for fractional-N synthesizers 有权
$Coarse tuning for fractional-N synthesizers$
标题翻译：分数N合成器的粗调
公开(公告)号：US07064591B1
公开(公告)日：2006-06-20
申请号：US10901669
申请日：2004-07-29
申请人： Scott Humphreys , Ryan Bunch
发明人： Scott Humphreys , Ryan Bunch
IPC分类号： H03L7/06
CPC分类号： H03L7/10 , H03J2200/10 , H03L7/193 , H03L7/1974
摘要： An improved coarse tuning process for fractional-N frequency synthesizers is provided. In general, a coarse tuning circuit controls a phase lock loop (PLL) of a frequency synthesizer such that the phase lock loop operates in an integer division mode during coarse tuning, thereby eliminating jitter due to fractional-N operation during coarse tuning. The coarse tuning circuit includes divide value generation circuitry that provides an integer divide value to an N divider of the PLL during coarse tuning and a fractional-N sequence to the N divider during fractional-N operation.
摘要翻译：提供了一种用于分数N频率合成器的改进的粗调程序。通常，粗调电路控制频率合成器的锁相环（PLL），使得在粗调谐期间锁相环以整数分频模式工作，从而消除了在粗调谐期间由于分数-N运算引起的抖动。粗调电路包括分频值产生电路，其在粗调谐期间向PLL的N分频器提供整数分频值，并且在小数N运算期间向N分频器提供分数N序列。

3. 发明申请

US20060197613A1 Frequency modulation linearization system for a Fractional-N Offset PLL 有权
标题翻译：用于分数N偏移PLL的频率调制线性化系统
公开(公告)号：US20060197613A1
公开(公告)日：2006-09-07
申请号：US11415808
申请日：2006-05-02
申请人： Ryan Bunch , Alexander Hietala , Scott Humphreys
发明人： Ryan Bunch , Alexander Hietala , Scott Humphreys
IPC分类号： H03L7/00
CPC分类号： H03L7/1976 , H03C3/0966 , H03L7/23 , H03L2207/12
摘要： A linearization system is provided for a Fractional-N Offset Phase Locked Loop (FN-OPLL) in a frequency or phase modulation system. In general, the linearization system processes a modulation signal to provide a linearized modulation signal to a fractional-N divider in a reference path of the FN-OPLL such that a frequency or phase modulation component at the output of the FN-OPLL is substantially linear with respect to the modulation signal.
摘要翻译：在频率或相位调制系统中为分数N偏移锁相环（FN-OPLL）提供线性化系统。通常，线性化系统处理调制信号以向FN-OPLL的参考路径中的分数N分频器提供线性调制信号，使得FN-OPLL的输出处的频率或相位调制分量基本上是线性的相对于调制信号。

4. 发明申请

US20060170505A1 FRACTIONAL-N OFFSET PHASE LOCKED LOOP 有权
标题翻译：分段相位锁相环
公开(公告)号：US20060170505A1
公开(公告)日：2006-08-03
申请号：US11047258
申请日：2005-01-31
申请人： Scott Humphreys , Ryan Bunch , Barry Hunt , Alexander Wayne Hietala
发明人： Scott Humphreys , Ryan Bunch , Barry Hunt , Alexander Wayne Hietala
IPC分类号： H03L7/00
CPC分类号： H03L7/1976 , H03C3/0966 , H03L7/23 , H03L2207/12
摘要： A fractional-N offset phase locked loop (FN-OPLL) is provided. The FN-OPLL includes a fractional divider, a phase detector, a loop filter, a voltage controlled oscillator (VCO), and feedback circuitry. Combiner circuitry combines an initial fractional divide value and a modulation signal to provide a combined fractional divide value. Based on the combined fractional divide value, the fractional-N divider divides a reference frequency and provides a divided reference frequency to the phase detector. The phase detector compares a phase of the divided reference frequency to a phase of a feedback signal to provide a comparison signal. The comparison signal is filtered by the loop filter to provide a control signal to the VCO, where the control signal controls a frequency of an output signal of the VCO. The output signal is processed by the feedback circuitry to provide the feedback signal to the phase detector.
摘要翻译：提供了一个分数N偏移锁相环（FN-OPLL）。 FN-OPLL包括分数分频器，相位检测器，环路滤波器，压控振荡器（VCO）和反馈电路。组合器电路组合初始分数除法值和调制信号以提供组合分数除数值。基于组合分数除法，分数N分频器划分参考频率，并向相位检测器提供分频参考频率。相位检测器将分频参考频率的相位与反馈信号的相位进行比较，以提供比较信号。比较信号由环路滤波器滤波，以向VCO提供控制信号，其中控制信号控制VCO的输出信号的频率。输出信号由反馈电路处理，以将反馈信号提供给相位检测器。

5. 发明授权

US06573782B2 Sigma delta FM ratio detector 有权
公开(公告)号：US06573782B2
公开(公告)日：2003-06-03
申请号：US09769941
申请日：2001-01-26
申请人： Raymond Louis Barrett, Jr. , Barry Herold , Scott Humphreys
发明人： Raymond Louis Barrett, Jr. , Barry Herold , Scott Humphreys
IPC分类号： H03D302
CPC分类号： H03D3/02
摘要： A circuit (100) for generating a ratio signal indicating a ratio of frequency error to signal magnitude of an input signal includes an FM ratio detector (110) and a sigma-delta analog-to-digital converter (130). The FM ratio detector (110) is responsive to the input signal and generates a magnitude signal and an error signal. The magnitude signal is representative of a magnitude of the input signal and the error signal is representative of a frequency error of the input signal relative to a preselected frequency. The sigma-delta analog-to-digital converter (130), which is responsive to the filtered magnitude signal and the filtered error signal, generates a stream of logic “1's” and logic “0's” that are indicative of a ratio of the filtered error signal to the filtered magnitude signal. Thus, the sigma-delta analog-to-digital converter generates the ratio signal (132).

6. 发明授权

US6087894A Low power precision current reference 失效
标题翻译：低功率精密电流参考
公开(公告)号：US6087894A
公开(公告)日：2000-07-11
申请号：US32877
申请日：1998-03-02
申请人： Raymond Louis Barrett, Jr. , Barry W. Herold , Scott Humphreys , Lawrence L. Case
发明人： Raymond Louis Barrett, Jr. , Barry W. Herold , Scott Humphreys , Lawrence L. Case
IPC分类号： G05F3/26 , G05F3/02
CPC分类号： G05F3/262
摘要： A first complementary metal oxide semiconductor (CMOS) current reference circuit (100, 500) has a first and a second current mirror (110, 150) and is implemented using one of bulk wafer technology and silicon on insulator (SOI) technology. The first current mirror (110) has an output stage (130) that includes at least one cascode coupled field effect transistor (FET) (125) having one of a source tied well (when implemented using bulk wafer technology) or a source tied body (when implemented using SOI technology). A second CMOS current reference circuit (600, 800) has a first and a second current mirror (650, 610) and is implemented using SOI technology. The first current mirror (650) has a first bias FET (161) having a gate tied body.
摘要翻译：第一互补金属氧化物半导体（CMOS）电流参考电路（100,500）具有第一和第二电流镜（110,150），并且使用体晶片技术和绝缘体上硅（SOI）技术之一来实现。第一电流镜（110）具有输出级（130），该输出级包括至少一个共源共栅耦合场效应晶体管（FET）（125），其具有源极连接（当使用体晶片技术实现时）或源极体（使用SOI技术实现时）。第二CMOS电流参考电路（600,800）具有第一和第二电流镜（650,610），并且使用SOI技术来实现。第一电流镜（650）具有具有门接合体的第一偏置FET（161）。

7. 发明授权

US07274229B1 Coarse tuning for fractional-N synthesizers 有权
$Coarse tuning for fractional-N synthesizers$
标题翻译：分数N合成器的粗调
公开(公告)号：US07274229B1
公开(公告)日：2007-09-25
申请号：US11472889
申请日：2006-06-22
申请人： Scott Humphreys , Ryan Bunch
发明人： Scott Humphreys , Ryan Bunch
IPC分类号： H03L7/06
CPC分类号： H03L7/10 , H03J2200/10 , H03L7/193 , H03L7/1974
摘要： An improved coarse tuning process for fractional-N frequency synthesizers is provided. In general, a coarse tuning circuit controls a phase lock loop (PLL) of a frequency synthesizer such that the phase lock loop operates in an integer division mode during coarse tuning, thereby eliminating jitter due to fractional-N operation during coarse tuning. The coarse tuning circuit includes divide value generation circuitry that provides an integer divide value to an N divider of the PLL during coarse tuning and a fractional-N sequence to the N divider during fractional-N operation.
摘要翻译：提供了一种用于分数N频率合成器的改进的粗调程序。通常，粗调电路控制频率合成器的锁相环（PLL），使得在粗调谐期间锁相环以整数分频模式工作，从而消除了在粗调谐期间由于分数-N运算引起的抖动。粗调电路包括分频值产生电路，其在粗调谐期间向PLL的N分频器提供整数分频值，并且在小数N运算期间向N分频器提供分数N序列。

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