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    • 4. 发明授权
    • Low power precision current reference
    • 低功率精密电流参考
    • US6087894A
    • 2000-07-11
    • US32877
    • 1998-03-02
    • Raymond Louis Barrett, Jr.Barry W. HeroldScott HumphreysLawrence L. Case
    • Raymond Louis Barrett, Jr.Barry W. HeroldScott HumphreysLawrence L. Case
    • G05F3/26G05F3/02
    • G05F3/262
    • A first complementary metal oxide semiconductor (CMOS) current reference circuit (100, 500) has a first and a second current mirror (110, 150) and is implemented using one of bulk wafer technology and silicon on insulator (SOI) technology. The first current mirror (110) has an output stage (130) that includes at least one cascode coupled field effect transistor (FET) (125) having one of a source tied well (when implemented using bulk wafer technology) or a source tied body (when implemented using SOI technology). A second CMOS current reference circuit (600, 800) has a first and a second current mirror (650, 610) and is implemented using SOI technology. The first current mirror (650) has a first bias FET (161) having a gate tied body.
    • 第一互补金属氧化物半导体(CMOS)电流参考电路(100,500)具有第一和第二电流镜(110,150),并且使用体晶片技术和绝缘体上硅(SOI)技术之一来实现。 第一电流镜(110)具有输出级(130),该输出级包括至少一个共源共栅耦合场效应晶体管(FET)(125),其具有源极连接(当使用体晶片技术实现时)或源极体 (使用SOI技术实现时)。 第二CMOS电流参考电路(600,800)具有第一和第二电流镜(650,610),并且使用SOI技术来实现。 第一电流镜(650)具有具有门接合体的第一偏置FET(161)。
    • 5. 发明授权
    • Two's complement digital to analog converter
    • 二进制补码数模转换器
    • US5805095A
    • 1998-09-08
    • US781252
    • 1997-01-10
    • Scott Robert HumphreysRaymond Louis Barrett, Jr.Lawrence Loren Case
    • Scott Robert HumphreysRaymond Louis Barrett, Jr.Lawrence Loren Case
    • H03M1/66
    • H03M1/66
    • A two's complement digital to analog converter (300) is for converting a two's complement binary value to an analog output current, and includes a control circuit (310) which generates controlled value bits, a digital to analog current converter (DACC) (320), and an augmenter (330). The DACC (320) generates a DACC analog current which is a portion of the analog output current and which has an absolute value which is related to the binary value of the controlled value bits. The augmenter (330), which is coupled to a most significant bit of the two's complement binary value, generates a portion of the analog output current by modifying the absolute value of the DACC analog current by a least significant bit current increment when the most significant bit indicates a negative value of the two's complement binary value.
    • 二进制补码数模转换器(300)用于将二进制补码二进制值转换为模拟输出电流,并且包括产生受控值位的控制电路(310),数模转换器(DACC)(320) ,以及增强器(330)。 DACC(320)产生作为模拟输出电流的一部分的DACC模拟电流,其具有与控制值位的二进制值相关的绝对值。 耦合到二进制补码二进制值的最高有效位的增益器(330)通过在最高有效位电流增量时修改DACC模拟电流的绝对值来产生模拟输出电流的一部分 位表示二进制补码二进制值的负值。
    • 8. 发明授权
    • Band-pass sigma-delta converter and commutating filter therefor
    • 带通Σ-Δ转换器和换向滤波器
    • US5841822A
    • 1998-11-24
    • US982179
    • 1997-12-01
    • James Gregory MittelRaymond Louis Barrett, Jr.Walter Davis
    • James Gregory MittelRaymond Louis Barrett, Jr.Walter Davis
    • H03H19/00H03M3/02H04B1/10
    • H03H19/004H03M3/404H03M3/43H03M3/454
    • A communication receiver (600) utilizes a band-pass sigma-delta converter (100) for receiving a radio signal. The band-pass sigma-delta converter (100) includes a comparator (106) coupled to an adder-filter (101) for making a comparison between a predetermined reference level (110) and an intermediate signal (125), and for generating a comparison result signal (114) responsive to the comparison. A storage element (108) is used for storing the comparison result signal (114) for a predetermined delay period, thereby producing a clocked output signal (118). The adder-filter (101) is coupled to an analog signal (103) and to the clocked output signal (118) for subtracting the clocked output signal (118) from the analog signal (103) to produce a difference signal (120) that is filtered by a commutating filter (400) for generating the intermediate signal (125) responsive to the difference signal (120).
    • 通信接收机(600)利用带通Σ-Δ转换器(100)来接收无线电信号。 带通Σ-Δ转换器(100)包括耦合到加法器滤波器(101)的比较器(106),用于在预定参考电平(110)和中间信号(125)之间进行比较,并且用于产生 比较结果信号(114)响应于比较。 存储元件(108)用于在预定的延迟周期内存储比较结果信号(114),从而产生时钟输出信号(118)。 加法器滤波器(101)耦合到模拟信号(103)和时钟输出信号(118),用于从模拟信号(103)中减去时钟输出信号(118)以产生差分信号(120),其中, 通过换向滤波器(400)进行滤波,用于响应差分信号(120)产生中间信号(125)。
    • 9. 发明授权
    • Boot-strapped cascode current mirror
    • 引导带状共源共栅电流镜
    • US5640681A
    • 1997-06-17
    • US149886
    • 1993-11-10
    • Raymond Louis Barrett, Jr.Barry Wayne HeroldGrazyna A. Pajunen
    • Raymond Louis Barrett, Jr.Barry Wayne HeroldGrazyna A. Pajunen
    • G05F3/26H04B7/00G05F3/16
    • G05F3/262
    • A cascode current mirror circuit includes a cascode connected input stage (401) that operates to conduct an input current (400) in response to an input voltage of an input signal coupled to an effective transconductance of the cascode connected input stage (401). An input mirroring transistor (404) operates to control a mirror reference current (406) in response to the input voltage of the input signal. A diode connected transistor (409) coupled to a second control node of the cascode connected input stage (410) generates a control bias proportional to the mirror reference current (406) and to the input signal. A cascode connected output stage (411) has a first control node (413) coupled to the input signal and a second control node (414) coupled to the diode connected transistor (409) and the second control node (410) of the cascode connected input stage (401) for establishing an output current (415) that is substantially equivalent to the input current (400).
    • 共源共栅电流镜电路包括共源共栅连接的输入级(401),其操作以响应耦合到共源共栅连接的输入级(401)的有效跨导的输入信号的输入电压来传导输入电流(400)。 输入镜像晶体管(404)用于响应于输入信号的输入电压来控制镜参考电流(406)。 耦合到共源共栅连接的输入级(410)的第二控制节点的二极管连接晶体管(409)产生与镜参考电流(406)成比例的控制偏置和输入信号。 级联连接的输出级(411)具有耦合到输入信号的第一控制节点(413)和耦合到二极管连接的晶体管(409)的第二控制节点(414)和连接的共源共栅的第二控制节点(410) 输入级(401),用于建立基本上等于输入电流(400)的输出电流(415)。