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1. 发明授权

US08193846B2 Selectable delay pulse generator 有权
标题翻译：可选延迟脉冲发生器
公开(公告)号：US08193846B2
公开(公告)日：2012-06-05
申请号：US12510200
申请日：2009-07-27
申请人： John L. Fagan , Mark Bossard
发明人： John L. Fagan , Mark Bossard
IPC分类号： H03H11/26
CPC分类号： H03K7/08 , H03K5/133 , H03K2005/00058 , H03K2005/00156
摘要： A programmable pulse generator having a clock signal delay chain, multiplexer, and reduced voltage charge circuit. The clock delay chain comprises a plurality of propagated delays, coupled to the multiplexer. The multiplexer selects a particular clock delay signal from a plurality of delay chain taps. The multiplexer is driven by a tap select register coupled to a state machine. The state machine controls the programmable pulse output, encoding the data by varying the pulse width and delay between pulses. The delay of pulse outputs from the multiplexer are reduced by coupling a reduced voltage pre-charge circuit to the multiplexer.
摘要翻译：一种可编程脉冲发生器，具有时钟信号延迟链，多路复用器和降压充电电路。时钟延迟链包括耦合到多路复用器的多个传播延迟。复用器从多个延迟链抽头中选择特定的时钟延迟信号。复用器由耦合到状态机的分接选择寄存器驱动。状态机控制可编程脉冲输出，通过改变脉冲宽度和脉冲之间的延迟对数据进行编码。通过将降低的电压预充电电路耦合到多路复用器来减少来自多路复用器的脉冲输出的延迟。

2. 发明授权

US4103348A Volatile and nonvolatile random access memory cell 失效
标题翻译：挥发性和非易失性随机存取存储器单元
公开(公告)号：US4103348A
公开(公告)日：1978-07-25
申请号：US828577
申请日：1977-08-29
申请人： John L. Fagan
发明人： John L. Fagan
IPC分类号： G11C11/403 , G11C14/00 , G11C16/04 , H03K3/356 , G11C11/40
CPC分类号： G11C11/403 , G11C14/00 , G11C16/0466 , H03K3/356008
摘要： A random access memory cell for storing information in both volatile and nonvolatile form is described incorporating a dual gate variable threshold transistor, a capacitor, and three field effect transistors. The dual gate variable threshold transistor may include a fixed threshold and a variable threshold field effect transistor.

3. 发明授权

US07283011B2 Method for performing dual phase pulse modulation 有权
标题翻译：执行双相脉冲调制的方法
公开(公告)号：US07283011B2
公开(公告)日：2007-10-16
申请号：US10836705
申请日：2004-04-29
申请人： Daniel S. Cohen , Daniel J. Meyer , John L. Fagan
发明人： Daniel S. Cohen , Daniel J. Meyer , John L. Fagan
IPC分类号： H03K7/04
CPC分类号： H04L25/4902
摘要： A modulation method, referred to as dual phase pulse modulation (DPPM), represents digital data as a series of high and low pulses whose widths represent groups of M data bits, with both the high and low pulses representing successive M-bit groups. Each of the 2M possible data values for a group of M data bits uniquely corresponds to one of 2M distinct pulse widths. This modulation method is essentially clockless, with data being decoded from a signal by detecting each pulse's width with respect to the last transition. Power consumption is reduced by having M data bits represented for each pulse transition, and by using both the high and low pulses to represent data.
摘要翻译：被称为双相位脉冲调制（DPPM）的调制方法将数字数据表示为一系列高和低脉冲，其宽度表示M个数据位组，高脉冲和低脉冲都表示连续的M位组。一组M个数据位的2个M个可能数据值中的每一个唯一地对应于2个不同脉冲宽度中的一个。该调制方法本质上是无时钟的，其中通过相对于最后的转换检测每个脉冲的宽度，从信号中解码数据。通过为每个脉冲转换表示M个数据位，并通过同时使用高和低脉冲来表示数据来降低功耗。

4. 发明授权

US4160291A Precharge circuitry for an electrically alterable non-volatile memory 失效
标题翻译：用于电可更换非易失性存储器的前置电路
公开(公告)号：US4160291A
公开(公告)日：1979-07-03
申请号：US929626
申请日：1978-07-31
申请人： Philip C. Smith , John L. Fagan
发明人： Philip C. Smith , John L. Fagan
IPC分类号： G11C5/02 , G11C8/10 , G11C11/30 , G11C11/34 , G11C16/04 , G11C16/08 , H03K3/356 , H03K19/0185 , G11C7/00
CPC分类号： G11C16/08 , G11C11/30 , G11C16/0466 , G11C5/025 , G11C8/10 , H03K19/01855 , H03K3/356008
摘要： An improved electrically alterable non-volatile memory for storing information is described incorporating an array of memory cells composed of variable threshold field effect transistors, means for writing and reading information into and out of the array which includes precharged circuitry to provide predetermined voltages on the gate, source and drain electrodes of the transistors in the array before writing or reading and row decode circuitry on both sides of the array to permit closer spacing of the variable threshold transistors in the array.

5. 发明授权

US07482837B2 System and method for combining signals on a differential I/O link 有权
标题翻译：用于在差分I / O链路上组合信号的系统和方法
公开(公告)号：US07482837B2
公开(公告)日：2009-01-27
申请号：US11401205
申请日：2006-04-10
申请人： John L. Fagan
发明人： John L. Fagan
IPC分类号： H03K19/0175
CPC分类号： H04L25/0272 , H04L25/4904 , H04L25/4915
摘要： System and method for combining signals on a differential signal provided over a communication link. In one aspect, a system for providing a differential communication link includes a signal combination circuit that receives a data signal and a clock signal and outputs a modulated differential signal on a differential link, where the modulated differential signal includes a differential data signal having an offset modulated at a frequency of the clock signal. A receiving circuit receives the modulated differential signal and senses and recovers the data signal and the clock signal therefrom.
摘要翻译：在通过通信链路提供的差分信号上组合信号的系统和方法。一方面，一种用于提供差分通信链路的系统包括：信号组合电路，其接收数据信号和时钟信号，并在差分链路上输出经调制的差分信号，其中调制差分信号包括具有偏移量的差分数据信号以时钟信号的频率进行调制。接收电路接收经调制的差分信号，并从中感测并恢复数据信号和时钟信号。

6. 发明授权

US07471132B2 Reduced voltage pre-charge multiplexer 有权
标题翻译：降压预充电多路复用器
公开(公告)号：US07471132B2
公开(公告)日：2008-12-30
申请号：US11559810
申请日：2006-11-14
申请人： John L. Fagan , Mark A. Bossard
发明人： John L. Fagan , Mark A. Bossard
IPC分类号： H03K3/017
CPC分类号： H03K17/693
摘要： An electronic device selects one of a plurality of input signals for coupling to an output channel. Individual pulldowns provide a separate pathway for each input, and are coupled to a common node which: is pre-charged to a voltage less than a system voltage. Each pulldown is coupled to a select line for gating an associated input signal.
摘要翻译：电子设备选择用于耦合到输出通道的多个输入信号中的一个。单个下拉为每个输入提供单独的路径，并且耦合到公共节点，其被预充电到小于系统电压的电压。每个下拉连接到用于选通相关联的输入信号的选择线。

7. 发明授权

US07233185B2 Vernier circuit for fine control of sample time 有权
标题翻译：游标电路用于精细控制采样时间
公开(公告)号：US07233185B2
公开(公告)日：2007-06-19
申请号：US10837478
申请日：2004-04-29
申请人： John L. Fagan , Mark A. Bossard , Daniel S. Cohen
发明人： John L. Fagan , Mark A. Bossard , Daniel S. Cohen
IPC分类号： H03H11/26
CPC分类号： H03K5/133 , H03K2005/00058 , H03K2005/00156
摘要： A vernier time shifting circuit is used for fine-tuning capture of a clock signal and/or a data signal to compensate for fluctuations produced by the system or other variations within non-time invariant parts of the chip. Other variations can include process, temperature, or voltage differences. The vernier sample time shifting circuit allows shifting the signal in small steps to allow for optimal sampling.
摘要翻译：游标时移电路用于微调时钟信号和/或数据信号的捕获，以补偿由系统产生的波动或芯片非时不变部分内的其他变化。其他变化可以包括工艺，温度或电压差。游标采样时移电路允许以小步进移动信号以允许最佳采样。

8. 发明申请

US20090284296A1 SELECTABLE DELAY PULSE GENERATOR 有权
标题翻译：可选延迟脉冲发生器
公开(公告)号：US20090284296A1
公开(公告)日：2009-11-19
申请号：US12510200
申请日：2009-07-27
申请人： John L. Fagan , Mark A. Bossard
发明人： John L. Fagan , Mark A. Bossard
IPC分类号： H03H11/26
CPC分类号： H03K7/08 , H03K5/133 , H03K2005/00058 , H03K2005/00156
摘要： A programmable pulse generator having a clock signal delay chain, multiplexer, and reduced voltage charge circuit. The clock delay chain comprises a plurality of propagated delays, coupled to the multiplexer. The multiplexer selects a particular clock delay signal from a plurality of delay chain taps. The multiplexer is driven by a tap select register coupled to a state machine. The state machine controls the programmable pulse output, encoding the data by varying the pulse width and delay between pulses. The delay of pulse outputs from the multiplexer are reduced by coupling a reduced voltage pre-charge circuit to the multiplexer.
摘要翻译：一种可编程脉冲发生器，具有时钟信号延迟链，多路复用器和降压充电电路。时钟延迟链包括耦合到多路复用器的多个传播延迟。复用器从多个延迟链抽头中选择特定的时钟延迟信号。复用器由耦合到状态机的分接选择寄存器驱动。状态机控制可编程脉冲输出，通过改变脉冲宽度和脉冲之间的延迟对数据进行编码。通过将降低的电压预充电电路耦合到多路复用器来减少来自多路复用器的脉冲输出的延迟。

9. 发明授权

US07260151B2 Dual phase pulse modulation system 有权
标题翻译：双相脉冲调制系统
公开(公告)号：US07260151B2
公开(公告)日：2007-08-21
申请号：US10961980
申请日：2004-10-08
申请人： Daniel S. Cohen , John L. Fagan
发明人： Daniel S. Cohen , John L. Fagan
IPC分类号： H04B14/04
CPC分类号： H04L25/4902 , H03M5/08 , H04L25/4904 , H04N1/00127 , H04N2201/0015 , H04N2201/0065
摘要： A system configured to transmit and receive data signals over a data link in serial fashion using dual phase pulse modulation (DPPM) is described. The data link may be, for example, a one or two wire unshielded twisted pair (UTP) cable. An exemplary system includes a configurable interface able to accept parallel data from an external source, such as a microprocessor or an imaging device. The interface is externally programmable for a particular data format. An encoder is coupled to the configurable interface and converts parallel data into serial output data, the serial output data having high and low data pulses with each of the high and low data pulses encoded to have one of 2M distinct data pulse widths. The system further includes a decoder coupled to the configurable interface, which is able to convert the serial input data into parallel data.
摘要翻译：描述了被配置为通过数据链路以串行方式使用双相位脉冲调制（DPPM）来发送和接收数据信号的系统。数据链路可以是例如一根或两根非屏蔽双绞线（UTP）电缆。示例性系统包括能够接收来自诸如微处理器或成像设备的外部源的并行数据的可配置接口。该界面可外部编程为特定的数据格式。编码器耦合到可配置接口并将并行数据转换为串行输出数据，串行输出数据具有高和低数据脉冲，其中高和低数据脉冲中的每一个被编码为具有2 / 不同的数据脉冲宽度。该系统还包括耦合到可配置接口的解码器，其能够将串行输入数据转换为并行数据。

10. 发明授权

US07157958B2 Reduced voltage pre-charge multiplexer 有权
标题翻译：降压预充电多路复用器
公开(公告)号：US07157958B2
公开(公告)日：2007-01-02
申请号：US10962276
申请日：2004-10-08
申请人： John L. Fagan , Mark A. Bossard
发明人： John L. Fagan , Mark A. Bossard
IPC分类号： H03K17/00
CPC分类号： H03K17/693
摘要： An electronic device selects one of a plurality of input signals for coupling to an output channel. Individual pulldowns provide a separate pathway for each input, and are coupled to a common node which is pre-charged to a voltage less than a system voltage. Each pulldown is coupled to a select line for gating an associated input signal.
摘要翻译：电子设备选择用于耦合到输出通道的多个输入信号中的一个。单个下拉为每个输入提供单独的路径，并且耦合到公共节点，其被预充电到小于系统电压的电压。每个下拉连接到用于选通相关输入信号的选择线。

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