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1. 发明授权

US07079577B2 Wide window decoder circuit for dual phase pulse modulation 有权
标题翻译：宽窗口解码电路，用于双相脉冲调制
公开(公告)号：US07079577B2
公开(公告)日：2006-07-18
申请号：US10937225
申请日：2004-09-08
申请人： Daniel S. Cohen
发明人： Daniel S. Cohen
IPC分类号： H03K9/08
CPC分类号： H04L25/4902 , H03K9/08 , H03M9/00
摘要： A dual phase pulse modulation (DPPM) decoder circuit processes a DPPM signal, which is in the form of a series of high and low pulses whose pulse widths represent successive groups of M data bits, so as to recover data carried by the signal. Each of the 2M possible data values of an M-bit group corresponds to one of 2M distinct pulse widths. Circuit blocks determine the width of each pulse by piping the DPPM signal through a short delay chain and inputting the delayed outputs and the non-delayed signal into AND logic gates, whose outputs are used to clock flip-flop registers. The registers are reset to a known state at the start of each signal pulse and toggled to an opposite state if clocked. The registered outputs are interpreted by logic to obtain the corresponding M-bit groups.
摘要翻译：双相脉冲调制（DPPM）解码器电路处理DPPM信号，DPPM信号是脉冲宽度代表M个数据位的连续组的一系列高和低脉冲的形式，以便恢复信号携带的数据。 M位组的2个M个可能数据值中的每一个对应于2个不同脉冲宽度中的一个。电路块通过将DPPM信号通过短延迟链进行管道来确定每个脉冲的宽度，并将延迟的输出和非延迟的信号输入到与逻辑门，其逻辑门的输出用于时钟触发器寄存器。寄存器在每个信号脉冲开始时被复位到已知状态，并且如果计时，则被切换到相反的状态。注册的输出由逻辑解释，以获得相应的M位组。

2. 发明授权

US06947493B2 Dual phase pulse modulation decoder circuit 有权
标题翻译：双相脉冲调制解码电路
公开(公告)号：US06947493B2
公开(公告)日：2005-09-20
申请号：US10836710
申请日：2004-04-29
申请人： Daniel S. Cohen , Daniel J. Meyer
发明人： Daniel S. Cohen , Daniel J. Meyer
IPC分类号： H03M5/08 , H04L27/04 , H04L27/12 , H04L27/20
CPC分类号： H03M5/08
摘要： A dual phase pulse modulation (DPPM) decoder circuit processes a DPPM signal, which is in the form of a series of high and low pulses whose pulse widths represent successive groups of M data bits, so as to recover data carried by the signal. Each of the 2M possible data values of an M-bit group corresponds to one of 2M distinct pulse widths. Circuit blocks determine the width of each pulse by piping the DPPM signal through a short delay chain and using the delayed outputs to clock flip-flop registers to sample the non-delayed signal. The registered output is interpreted by logic gates to obtain the corresponding M-bit groups. The decoder circuit may have two substantially identical pulse width determining blocks, one receiving the DPPM signal for measuring high pulses, and the other receiving an inverted DPPM signal for measuring the low pulses.
摘要翻译：双相脉冲调制（DPPM）解码器电路处理DPPM信号，DPPM信号是脉冲宽度代表M个数据位的连续组的一系列高和低脉冲的形式，以便恢复信号携带的数据。 M位组的2个M个可能数据值中的每一个对应于2个不同脉冲宽度中的一个。电路块通过将DPPM信号通过短延迟链进行管道来确定每个脉冲的宽度，并使用延迟的输出将时钟触发器寄存器采样到非延迟信号。注册的输出由逻辑门解释以获得相应的M位组。解码器电路可以具有两个基本上相同的脉冲宽度确定块，一个接收用于测量高脉冲的DPPM信号，另一个接收用于测量低脉冲的反相DPPM信号。

3. 发明授权

US07440515B2 System and method for controlling modulation 有权
标题翻译：用于控制调制的系统和方法
公开(公告)号：US07440515B2
公开(公告)日：2008-10-21
申请号：US10972990
申请日：2004-10-25
申请人： Mikhail Itskovich , Daniel S. Cohen
发明人： Mikhail Itskovich , Daniel S. Cohen
IPC分类号： H03C3/00 , H04L27/12
CPC分类号： H04L27/20
摘要： A system and method for controlling modulation. The system includes a plurality of modulators and a transmitting unit. The plurality of modulators decodes data from a data signal and also encodes the data into a clock signal. The transmitting unit transmits the encoded clock signal. According to the system and method disclosed herein, the present invention provides optimized coding efficiency while minimizing overall power consumption.
摘要翻译：一种用于控制调制的系统和方法。该系统包括多个调制器和发送单元。多个调制器从数据信号中解码数据，并将数据编码成时钟信号。发送单元发送编码的时钟信号。根据本文公开的系统和方法，本发明提供优化的编码效率，同时最小化总体功耗。

4. 发明授权

US08327161B2 Command decoder for microcontroller based flash memory digital controller system 有权
标题翻译：命令解码器，用于基于微控制器的闪存数字控制器系统
公开(公告)号：US08327161B2
公开(公告)日：2012-12-04
申请号：US12538781
申请日：2009-08-10
申请人： Daniel S. Cohen
发明人： Daniel S. Cohen
IPC分类号： G06F1/26
CPC分类号： G06F9/30181 , G06F15/7814 , Y02D10/12 , Y02D10/13
摘要： A command decoder used for a microcontroller based Flash memory digital controller system includes multiple subsystems, including the command decoder, which serves as the main user interface for interpreting commands from a user and managing the priority of commands and command modes. The command decoder also stores crucial information including address, data, opcodes, and various flags registers that are used by other subsystems including the program buffer, burst read module, register block, and microcontroller. In addition, the command decoder contains clock synchronization logic, controls the sleep function of the microcontroller and serves as a test mode controller.
摘要翻译：用于基于微控制器的闪存数字控制器系统的命令解码器包括多个子系统，包括命令解码器，其用作解释来自用户的命令的主用户界面，并管理命令和命令模式的优先级。命令解码器还存储关键信息，包括由包括程序缓冲器，突发读取模块，寄存器块和微控制器的其他子系统使用的地址，数据，操作码和各种标志寄存器。此外，命令解码器包含时钟同步逻辑，控制微控制器的睡眠功能，并作为测试模式控制器。

5. 发明申请

US20090122913A1 System and method for controlling modulation 有权
标题翻译：用于控制调制的系统和方法
公开(公告)号：US20090122913A1
公开(公告)日：2009-05-14
申请号：US12288573
申请日：2008-10-21
申请人： Mikhail Itskovich , Daniel S. Cohen
发明人： Mikhail Itskovich , Daniel S. Cohen
IPC分类号： H04L27/12
CPC分类号： H04L27/20
摘要： A system and method for controlling modulation. The system includes a plurality of modulators and a transmitting unit. The plurality of modulators decodes data from a data signal and also encodes the data into a clock signal. The transmitting unit transmits the encoded clock signal. According to the system and method disclosed herein, the present invention provides optimized coding efficiency while minimizing overall power consumption.
摘要翻译：一种用于控制调制的系统和方法。该系统包括多个调制器和发送单元。多个调制器从数据信号中解码数据，并将数据编码成时钟信号。发送单元发送编码的时钟信号。根据本文公开的系统和方法，本发明提供优化的编码效率，同时最小化总体功耗。

6. 发明授权

US07260151B2 Dual phase pulse modulation system 有权
标题翻译：双相脉冲调制系统
公开(公告)号：US07260151B2
公开(公告)日：2007-08-21
申请号：US10961980
申请日：2004-10-08
申请人： Daniel S. Cohen , John L. Fagan
发明人： Daniel S. Cohen , John L. Fagan
IPC分类号： H04B14/04
CPC分类号： H04L25/4902 , H03M5/08 , H04L25/4904 , H04N1/00127 , H04N2201/0015 , H04N2201/0065
摘要： A system configured to transmit and receive data signals over a data link in serial fashion using dual phase pulse modulation (DPPM) is described. The data link may be, for example, a one or two wire unshielded twisted pair (UTP) cable. An exemplary system includes a configurable interface able to accept parallel data from an external source, such as a microprocessor or an imaging device. The interface is externally programmable for a particular data format. An encoder is coupled to the configurable interface and converts parallel data into serial output data, the serial output data having high and low data pulses with each of the high and low data pulses encoded to have one of 2M distinct data pulse widths. The system further includes a decoder coupled to the configurable interface, which is able to convert the serial input data into parallel data.
摘要翻译：描述了被配置为通过数据链路以串行方式使用双相位脉冲调制（DPPM）来发送和接收数据信号的系统。数据链路可以是例如一根或两根非屏蔽双绞线（UTP）电缆。示例性系统包括能够接收来自诸如微处理器或成像设备的外部源的并行数据的可配置接口。该界面可外部编程为特定的数据格式。编码器耦合到可配置接口并将并行数据转换为串行输出数据，串行输出数据具有高和低数据脉冲，其中高和低数据脉冲中的每一个被编码为具有2 / 不同的数据脉冲宽度。该系统还包括耦合到可配置接口的解码器，其能够将串行输入数据转换为并行数据。

7. 发明授权

US07103110B2 Dual phase pulse modulation encoder circuit 有权
标题翻译：双相脉冲调制编码电路
公开(公告)号：US07103110B2
公开(公告)日：2006-09-05
申请号：US10836703
申请日：2004-04-29
申请人： Daniel S. Cohen , John L. Fagan , Mark A. Bossard
发明人： Daniel S. Cohen , John L. Fagan , Mark A. Bossard
IPC分类号： H04L27/04 , H04L27/12 , H04L27/20
CPC分类号： H03M5/08
摘要： An dual phase pulse modulation (DPPM) encoder circuit converts data into a series of high and low signal pulses, each of whose time durations or pulse widths represents a group of M data bits, with the alternating high and low pulses representing successive groups. The encoder circuit may include a set of parallel-in, serial-out shift registers that subdivide received data words into the M-bit groups, a state machine that specified the pulse durations for each received group, e.g., by incrementing a state that indicates selected signal pulse transition times, a system clock delay chain with multiple taps, a multiplexer controlled by the state machine for successively selecting different taps, and a toggle flip-flop that is clocked by the multiplexer output.
摘要翻译：双相脉冲调制（DPPM）编码器电路将数据转换为一系列高和低信号脉冲，其中每个时间持续时间或脉冲宽度表示一组M个数据位，交替的高和低脉冲表示连续的组。编码器电路可以包括一组并行的串行输出移位寄存器，其将接收到的数据字细分到M位组中，状态机指定每个接收到的组的脉冲持续时间，例如通过递增指示选择的信号脉冲转换时间，具有多个抽头的系统时钟延迟链，由状态机控制的用于连续选择不同抽头的多路复用器，以及由多路复用器输出计时的开关触发器。

8. 发明授权

US07328299B2 Interface for compressed data transfer between host system and parallel data processing system 有权
标题翻译：主机系统与并行数据处理系统之间的压缩数据传输接口
公开(公告)号：US07328299B2
公开(公告)日：2008-02-05
申请号：US10995696
申请日：2004-11-23
申请人： Alison A. Przybysz , Daniel S. Cohen
发明人： Alison A. Przybysz , Daniel S. Cohen
IPC分类号： G06F13/40 , G06F13/38 , G06F13/20
CPC分类号： H04N21/23614 , H03M9/00 , H04L7/0008 , H04L7/0045 , H04L25/14 , H04L25/4902 , H04L25/4904 , H04N21/4348
摘要： An apparatus and method for interfacing a host system having a system data bus, clock signals, and control signals to a parallel data bus is described. Setting configuration bits allows the interface apparatus to be programmed to operate as a transmitter or a receiver with selectable device interface modes. When operating as a transmitter, the interface apparatus combines and compresses the system data bus, clocks, and control signals to match the available width of the parallel data bus. When operating as a receiver, the interface receives signals from the parallel data bus and restores the original signals which were combined and compressed. The device interface modes are selectable to be compatible in different device and circuit configurations.
摘要翻译：描述了一种用于将具有系统数据总线，时钟信号和控制信号的主机系统连接到并行数据总线的装置和方法。设置配置位允许将接口设备编程为具有可选设备接口模式的发射机或接收机。当作为发射机工作时，接口装置组合并压缩系统数据总线，时钟和控制信号以匹配并行数据总线的可用宽度。当作为接收器工作时，接口从并行数据总线接收信号并恢复组合和压缩的原始信号。器件接口模式可选择，以在不同的器件和电路配置中兼容。

9. 发明授权

US07233185B2 Vernier circuit for fine control of sample time 有权
标题翻译：游标电路用于精细控制采样时间
公开(公告)号：US07233185B2
公开(公告)日：2007-06-19
申请号：US10837478
申请日：2004-04-29
申请人： John L. Fagan , Mark A. Bossard , Daniel S. Cohen
发明人： John L. Fagan , Mark A. Bossard , Daniel S. Cohen
IPC分类号： H03H11/26
CPC分类号： H03K5/133 , H03K2005/00058 , H03K2005/00156
摘要： A vernier time shifting circuit is used for fine-tuning capture of a clock signal and/or a data signal to compensate for fluctuations produced by the system or other variations within non-time invariant parts of the chip. Other variations can include process, temperature, or voltage differences. The vernier sample time shifting circuit allows shifting the signal in small steps to allow for optimal sampling.
摘要翻译：游标时移电路用于微调时钟信号和/或数据信号的捕获，以补偿由系统产生的波动或芯片非时不变部分内的其他变化。其他变化可以包括工艺，温度或电压差。游标采样时移电路允许以小步进移动信号以允许最佳采样。

10. 发明授权

US08316174B2 Microcontroller based flash memory digital controller system 有权
标题翻译：基于微控制器的闪存数字控制器系统
公开(公告)号：US08316174B2
公开(公告)日：2012-11-20
申请号：US12569778
申请日：2009-09-29
申请人： Daniel S. Cohen , Matthew Todd Wich , Jason J. Ziomek , Rocendo Bracamontes , Shude Lu
发明人： Daniel S. Cohen , Matthew Todd Wich , Jason J. Ziomek , Rocendo Bracamontes , Shude Lu
IPC分类号： G06F12/00
CPC分类号： G06F9/3879 , G06F2212/2022 , G11C16/04 , G11C29/16
摘要： Some embodiments includes a digital control system having a microcontroller to handle a first command associated with a first operation of a memory device, and circuitry coupled to the microcontroller to handle a second command associated with a second operation of the memory device without involving the microcontroller in the second operation.
摘要翻译：一些实施例包括具有微处理器以处理与存储器件的第一操作相关联的第一命令的数字控制系统，以及耦合到微控制器的电路，以处理与存储器件的第二操作相关联的第二命令，而不涉及微控制器第二个操作。

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