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1. 发明授权

US07283011B2 Method for performing dual phase pulse modulation 有权
标题翻译：执行双相脉冲调制的方法
公开(公告)号：US07283011B2
公开(公告)日：2007-10-16
申请号：US10836705
申请日：2004-04-29
申请人： Daniel S. Cohen , Daniel J. Meyer , John L. Fagan
发明人： Daniel S. Cohen , Daniel J. Meyer , John L. Fagan
IPC分类号： H03K7/04
CPC分类号： H04L25/4902
摘要： A modulation method, referred to as dual phase pulse modulation (DPPM), represents digital data as a series of high and low pulses whose widths represent groups of M data bits, with both the high and low pulses representing successive M-bit groups. Each of the 2M possible data values for a group of M data bits uniquely corresponds to one of 2M distinct pulse widths. This modulation method is essentially clockless, with data being decoded from a signal by detecting each pulse's width with respect to the last transition. Power consumption is reduced by having M data bits represented for each pulse transition, and by using both the high and low pulses to represent data.
摘要翻译：被称为双相位脉冲调制（DPPM）的调制方法将数字数据表示为一系列高和低脉冲，其宽度表示M个数据位组，高脉冲和低脉冲都表示连续的M位组。一组M个数据位的2个M个可能数据值中的每一个唯一地对应于2个不同脉冲宽度中的一个。该调制方法本质上是无时钟的，其中通过相对于最后的转换检测每个脉冲的宽度，从信号中解码数据。通过为每个脉冲转换表示M个数据位，并通过同时使用高和低脉冲来表示数据来降低功耗。

2. 发明授权

US4160291A Precharge circuitry for an electrically alterable non-volatile memory 失效
标题翻译：用于电可更换非易失性存储器的前置电路
公开(公告)号：US4160291A
公开(公告)日：1979-07-03
申请号：US929626
申请日：1978-07-31
申请人： Philip C. Smith , John L. Fagan
发明人： Philip C. Smith , John L. Fagan
IPC分类号： G11C5/02 , G11C8/10 , G11C11/30 , G11C11/34 , G11C16/04 , G11C16/08 , H03K3/356 , H03K19/0185 , G11C7/00
CPC分类号： G11C16/08 , G11C11/30 , G11C16/0466 , G11C5/025 , G11C8/10 , H03K19/01855 , H03K3/356008
摘要： An improved electrically alterable non-volatile memory for storing information is described incorporating an array of memory cells composed of variable threshold field effect transistors, means for writing and reading information into and out of the array which includes precharged circuitry to provide predetermined voltages on the gate, source and drain electrodes of the transistors in the array before writing or reading and row decode circuitry on both sides of the array to permit closer spacing of the variable threshold transistors in the array.

3. 发明申请

US20090284296A1 SELECTABLE DELAY PULSE GENERATOR 有权
标题翻译：可选延迟脉冲发生器
公开(公告)号：US20090284296A1
公开(公告)日：2009-11-19
申请号：US12510200
申请日：2009-07-27
申请人： John L. Fagan , Mark A. Bossard
发明人： John L. Fagan , Mark A. Bossard
IPC分类号： H03H11/26
CPC分类号： H03K7/08 , H03K5/133 , H03K2005/00058 , H03K2005/00156
摘要： A programmable pulse generator having a clock signal delay chain, multiplexer, and reduced voltage charge circuit. The clock delay chain comprises a plurality of propagated delays, coupled to the multiplexer. The multiplexer selects a particular clock delay signal from a plurality of delay chain taps. The multiplexer is driven by a tap select register coupled to a state machine. The state machine controls the programmable pulse output, encoding the data by varying the pulse width and delay between pulses. The delay of pulse outputs from the multiplexer are reduced by coupling a reduced voltage pre-charge circuit to the multiplexer.
摘要翻译：一种可编程脉冲发生器，具有时钟信号延迟链，多路复用器和降压充电电路。时钟延迟链包括耦合到多路复用器的多个传播延迟。复用器从多个延迟链抽头中选择特定的时钟延迟信号。复用器由耦合到状态机的分接选择寄存器驱动。状态机控制可编程脉冲输出，通过改变脉冲宽度和脉冲之间的延迟对数据进行编码。通过将降低的电压预充电电路耦合到多路复用器来减少来自多路复用器的脉冲输出的延迟。

4. 发明授权

US07260151B2 Dual phase pulse modulation system 有权
标题翻译：双相脉冲调制系统
公开(公告)号：US07260151B2
公开(公告)日：2007-08-21
申请号：US10961980
申请日：2004-10-08
申请人： Daniel S. Cohen , John L. Fagan
发明人： Daniel S. Cohen , John L. Fagan
IPC分类号： H04B14/04
CPC分类号： H04L25/4902 , H03M5/08 , H04L25/4904 , H04N1/00127 , H04N2201/0015 , H04N2201/0065
摘要： A system configured to transmit and receive data signals over a data link in serial fashion using dual phase pulse modulation (DPPM) is described. The data link may be, for example, a one or two wire unshielded twisted pair (UTP) cable. An exemplary system includes a configurable interface able to accept parallel data from an external source, such as a microprocessor or an imaging device. The interface is externally programmable for a particular data format. An encoder is coupled to the configurable interface and converts parallel data into serial output data, the serial output data having high and low data pulses with each of the high and low data pulses encoded to have one of 2M distinct data pulse widths. The system further includes a decoder coupled to the configurable interface, which is able to convert the serial input data into parallel data.
摘要翻译：描述了被配置为通过数据链路以串行方式使用双相位脉冲调制（DPPM）来发送和接收数据信号的系统。数据链路可以是例如一根或两根非屏蔽双绞线（UTP）电缆。示例性系统包括能够接收来自诸如微处理器或成像设备的外部源的并行数据的可配置接口。该界面可外部编程为特定的数据格式。编码器耦合到可配置接口并将并行数据转换为串行输出数据，串行输出数据具有高和低数据脉冲，其中高和低数据脉冲中的每一个被编码为具有2 / 不同的数据脉冲宽度。该系统还包括耦合到可配置接口的解码器，其能够将串行输入数据转换为并行数据。

5. 发明授权

US07157958B2 Reduced voltage pre-charge multiplexer 有权
标题翻译：降压预充电多路复用器
公开(公告)号：US07157958B2
公开(公告)日：2007-01-02
申请号：US10962276
申请日：2004-10-08
申请人： John L. Fagan , Mark A. Bossard
发明人： John L. Fagan , Mark A. Bossard
IPC分类号： H03K17/00
CPC分类号： H03K17/693
摘要： An electronic device selects one of a plurality of input signals for coupling to an output channel. Individual pulldowns provide a separate pathway for each input, and are coupled to a common node which is pre-charged to a voltage less than a system voltage. Each pulldown is coupled to a select line for gating an associated input signal.
摘要翻译：电子设备选择用于耦合到输出通道的多个输入信号中的一个。单个下拉为每个输入提供单独的路径，并且耦合到公共节点，其被预充电到小于系统电压的电压。每个下拉连接到用于选通相关输入信号的选择线。

6. 发明授权

US07103110B2 Dual phase pulse modulation encoder circuit 有权
标题翻译：双相脉冲调制编码电路
公开(公告)号：US07103110B2
公开(公告)日：2006-09-05
申请号：US10836703
申请日：2004-04-29
申请人： Daniel S. Cohen , John L. Fagan , Mark A. Bossard
发明人： Daniel S. Cohen , John L. Fagan , Mark A. Bossard
IPC分类号： H04L27/04 , H04L27/12 , H04L27/20
CPC分类号： H03M5/08
摘要： An dual phase pulse modulation (DPPM) encoder circuit converts data into a series of high and low signal pulses, each of whose time durations or pulse widths represents a group of M data bits, with the alternating high and low pulses representing successive groups. The encoder circuit may include a set of parallel-in, serial-out shift registers that subdivide received data words into the M-bit groups, a state machine that specified the pulse durations for each received group, e.g., by incrementing a state that indicates selected signal pulse transition times, a system clock delay chain with multiple taps, a multiplexer controlled by the state machine for successively selecting different taps, and a toggle flip-flop that is clocked by the multiplexer output.
摘要翻译：双相脉冲调制（DPPM）编码器电路将数据转换为一系列高和低信号脉冲，其中每个时间持续时间或脉冲宽度表示一组M个数据位，交替的高和低脉冲表示连续的组。编码器电路可以包括一组并行的串行输出移位寄存器，其将接收到的数据字细分到M位组中，状态机指定每个接收到的组的脉冲持续时间，例如通过递增指示选择的信号脉冲转换时间，具有多个抽头的系统时钟延迟链，由状态机控制的用于连续选择不同抽头的多路复用器，以及由多路复用器输出计时的开关触发器。

7. 发明授权

US4415993A Fast access non-volatile memory 失效
标题翻译：快速访问非易失性存储器
公开(公告)号：US4415993A
公开(公告)日：1983-11-15
申请号：US324349
申请日：1981-11-23
申请人： Philip C. Smith , John L. Fagan
发明人： Philip C. Smith , John L. Fagan
IPC分类号： G11C17/00 , G11C11/34 , G11C16/06 , G11C16/08 , G11C16/34 , G11C13/00
CPC分类号： G11C16/08 , G11C16/3418 , G11C16/3431
摘要： A memory apparatus having a row and column decoder for controlling the read and write function to a transistor memory pair. A single power/chip select pad is utilized to both power the memory and select the memory chip. External control signals are applied directly to critical internal node within the memory apparatus.
摘要翻译：一种具有用于控制对晶体管存储器对的读和写功能的行和列解码器的存储装置。使用单个电源/芯片选择焊盘来为存储器供电并选择存储器芯片。外部控制信号直接应用于存储装置内的关键内部节点。

8. 发明授权

US4159540A Memory array address buffer with level shifting 失效
标题翻译：存储器阵列地址缓冲器，具有电平转换
公开(公告)号：US4159540A
公开(公告)日：1979-06-26
申请号：US929625
申请日：1978-07-31
申请人： Philip C. Smith , John L. Fagan
发明人： Philip C. Smith , John L. Fagan
IPC分类号： G11C5/02 , G11C8/10 , G11C11/30 , G11C11/34 , G11C16/04 , G11C16/08 , H03K3/356 , H03K19/0185 , G11C8/00
CPC分类号： G11C16/08 , G11C11/30 , G11C16/0466 , G11C5/025 , G11C8/10 , H03K19/01855 , H03K3/356008
摘要： An improved electrically alterable non-volatile memory for storing information is described incorporating an array of memory cells composed of variable threshold field effect transistors, means for writing and reading information into and out of the array which includes precharged circuitry to provide predetermined voltages on the gate, source and drain electrodes of the transistors in the array before writing or reading and row decode circuitry on both sides of the array to permit closer spacing of the variable threshold transistors in the array.
摘要翻译：描述了一种用于存储信息的改进的可电气可变非易失性存储器，其结合由可变阈值场效应晶体管组成的存储器单元阵列，用于将信息写入和读出阵列的装置，该阵列包括预充电电路以在栅极上提供预定电压在写入或读取之前的阵列中的晶体管的源极和漏极电极以及阵列两侧的行解码电路，以允许阵列中的可变阈值晶体管的更紧密的间隔。

9. 发明授权

US4124900A Memory using interleaved rows to permit closer spacing 失效
标题翻译：使用交错行的存储器允许更近的间隔
公开(公告)号：US4124900A
公开(公告)日：1978-11-07
申请号：US837791
申请日：1977-09-29
申请人： Philip C. Smith , John L. Fagan
发明人： Philip C. Smith , John L. Fagan
IPC分类号： G11C5/02 , G11C8/10 , G11C11/30 , G11C11/34 , G11C16/04 , G11C16/08 , H03K3/356 , H03K19/0185 , G11C5/06 , G11C8/00
CPC分类号： G11C16/08 , G11C11/30 , G11C16/0466 , G11C5/025 , G11C8/10 , H03K19/01855 , H03K3/356008
摘要： An improved electrically alterable non-volatile memory for storing information is described incorporating an array of memory cells composed of variable threshold field effect transistors, means for writing and reading information into and out of the array which includes precharged circuitry to provide predetermined voltages on the gate, source and drain electrodes of the transistors in the array before writing or reading and row decode circuitry on both sides of the array to permit closer spacing of the variable threshold transistors in the array.
摘要翻译：描述了一种用于存储信息的改进的可电气可变非易失性存储器，其结合由可变阈值场效应晶体管组成的存储器单元阵列，用于将信息写入和读出阵列的装置，该阵列包括预充电电路以在栅极上提供预定电压在写入或读取之前的阵列中的晶体管的源极和漏极电极以及阵列两侧的行解码电路，以允许阵列中的可变阈值晶体管的更紧密的间隔。

10. 发明授权

US4085441A Monolithic implementation of a fast Fourier transform 失效
标题翻译：快速傅里叶变换的单片实现
公开(公告)号：US4085441A
公开(公告)日：1978-04-18
申请号：US744546
申请日：1976-11-24
申请人： John L. Fagan
发明人： John L. Fagan
IPC分类号： G06G7/14 , G06G7/19 , G06J1/00 , G11C11/40 , H03K5/159
CPC分类号： G06G7/1907 , G06G7/14 , G06J1/005
摘要： An improved discrete analog filter incorporating analog delay and successive arithmetic stages utilizing charge coupled devices is described which may accept an analog input signal and calculate with the arithmetic stages the fast Fourier transform of the analog input signal to provide output signals indicative of the Fourier coefficients of the input signal.
摘要翻译：描述了一种结合模拟延迟和使用电荷耦合器件的连续运算级的改进的离散模拟滤波器，其可以接受模拟输入信号并且用算术级计算模拟输入信号的快速傅立叶变换，以提供表示傅立叶系数输入信号。

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