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1. 发明申请

US20050078021A1 Dual phase pulse modulation encoder circuit 有权
标题翻译：双相脉冲调制编码电路
公开(公告)号：US20050078021A1
公开(公告)日：2005-04-14
申请号：US10836703
申请日：2004-04-29
申请人： Daniel Cohen , John Fagan , Mark Bossard
发明人： Daniel Cohen , John Fagan , Mark Bossard
IPC分类号： H03M20060101 , H03M5/06 , H03M5/08 , H04L27/04 , H04L27/12 , H04L27/20
CPC分类号： H03M5/08
摘要： An dual phase pulse modulation (DPPM) encoder circuit converts data into a series of high and low signal pulses, each of whose time durations or pulse widths represents a group of M data bits, with the alternating high and low pulses representing successive groups. The encoder circuit may include a set of parallel-in, serial-out shift registers that subdivide received data words into the M-bit groups, a state machine that specified the pulse durations for each received group, e.g., by incrementing a state that indicates selected signal pulse transition times, a system clock delay chain with multiple taps, a multiplexer controlled by the state machine for successively selecting different taps, and a toggle flip-flop that is clocked by the multiplexer output.
摘要翻译：双相脉冲调制（DPPM）编码器电路将数据转换为一系列高和低信号脉冲，其中每个时间持续时间或脉冲宽度表示一组M个数据位，交替的高和低脉冲表示连续的组。编码器电路可以包括一组并行的串行输出移位寄存器，其将接收到的数据字细分到M位组中，状态机指定每个接收到的组的脉冲持续时间，例如通过递增指示选择的信号脉冲转换时间，具有多个抽头的系统时钟延迟链，由状态机控制的用于连续选择不同抽头的多路复用器，以及由多路复用器输出计时的开关触发器。

2. 发明授权

US08193846B2 Selectable delay pulse generator 有权
标题翻译：可选延迟脉冲发生器
公开(公告)号：US08193846B2
公开(公告)日：2012-06-05
申请号：US12510200
申请日：2009-07-27
申请人： John L. Fagan , Mark Bossard
发明人： John L. Fagan , Mark Bossard
IPC分类号： H03H11/26
CPC分类号： H03K7/08 , H03K5/133 , H03K2005/00058 , H03K2005/00156
摘要： A programmable pulse generator having a clock signal delay chain, multiplexer, and reduced voltage charge circuit. The clock delay chain comprises a plurality of propagated delays, coupled to the multiplexer. The multiplexer selects a particular clock delay signal from a plurality of delay chain taps. The multiplexer is driven by a tap select register coupled to a state machine. The state machine controls the programmable pulse output, encoding the data by varying the pulse width and delay between pulses. The delay of pulse outputs from the multiplexer are reduced by coupling a reduced voltage pre-charge circuit to the multiplexer.
摘要翻译：一种可编程脉冲发生器，具有时钟信号延迟链，多路复用器和降压充电电路。时钟延迟链包括耦合到多路复用器的多个传播延迟。复用器从多个延迟链抽头中选择特定的时钟延迟信号。复用器由耦合到状态机的分接选择寄存器驱动。状态机控制可编程脉冲输出，通过改变脉冲宽度和脉冲之间的延迟对数据进行编码。通过将降低的电压预充电电路耦合到多路复用器来减少来自多路复用器的脉冲输出的延迟。

3. 发明申请

US20050077942A1 Vernier circuit for fine control of sample time 有权
标题翻译：游标电路用于精细控制采样时间
公开(公告)号：US20050077942A1
公开(公告)日：2005-04-14
申请号：US10837478
申请日：2004-04-29
申请人： John Fagan , Mark Bossard , Daniel Cohen
发明人： John Fagan , Mark Bossard , Daniel Cohen
IPC分类号： H03H11/26 , H03K5/00 , H03K5/13
CPC分类号： H03K5/133 , H03K2005/00058 , H03K2005/00156
摘要： A vernier time shifting circuit is used for fine-tuning capture of a clock signal and/or a data signal to compensate for fluctuations produced by the system or other variations within non-time invariant parts of the chip. Other variations can include process, temperature, or voltage differences. The vernier sample time shifting circuit allows shifting the signal in small steps to allow for optimal sampling.
摘要翻译：游标时移电路用于微调时钟信号和/或数据信号的捕获，以补偿系统产生的波动或芯片非时不变部分内的其他变化。其他变化可以包括工艺，温度或电压差。游标采样时移电路允许以小步进移动信号以允许最佳采样。

4. 发明申请

US20050077941A1 Selectable delay pulse generator 审中-公开
标题翻译：可选延迟脉冲发生器
公开(公告)号：US20050077941A1
公开(公告)日：2005-04-14
申请号：US10961584
申请日：2004-10-08
申请人： John Fagan , Mark Bossard
发明人： John Fagan , Mark Bossard
IPC分类号： H03H11/26 , H03K20060101 , H03K5/00 , H03K5/13 , H03K7/08
CPC分类号： H03K7/08 , H03K5/133 , H03K2005/00058 , H03K2005/00156
摘要： A programmable pulse generator having a clock signal delay chain, multiplexer, and reduced voltage charge circuit. The clock delay chain comprises a plurality of propagated delays, coupled to the multiplexer. The multiplexer selects a particular clock delay signal from a plurality of delay chain taps. The multiplexer is driven by a tap select register coupled to a state machine. The state machine controls the programmable pulse output, encoding the data by varying the pulse width and delay between pulses. The delay of pulse outputs from the multiplexer are reduced by coupling a reduced voltage pre-charge circuit to the multiplexer.
摘要翻译：一种可编程脉冲发生器，具有时钟信号延迟链，多路复用器和降压充电电路。时钟延迟链包括耦合到多路复用器的多个传播延迟。复用器从多个延迟链抽头中选择特定的时钟延迟信号。复用器由耦合到状态机的分接选择寄存器驱动。状态机控制可编程脉冲输出，通过改变脉冲宽度和脉冲之间的延迟对数据进行编码。通过将降低的电压预充电电路耦合到多路复用器来减少来自多路复用器的脉冲输出的延迟。

5. 发明申请

US20050077939A1 Reduced voltage pre-charge multiplexer 有权
标题翻译：降压预充电多路复用器
公开(公告)号：US20050077939A1
公开(公告)日：2005-04-14
申请号：US10962276
申请日：2004-10-08
申请人： John Fagan , Mark Bossard
发明人： John Fagan , Mark Bossard
IPC分类号： H03K17/693 , H03K3/017
CPC分类号： H03K17/693
摘要： An electronic device selects one of a plurality of input signals for coupling to an output channel. Individual pulldowns provide a separate pathway for each input, and are coupled to a common node which is pre-charged to a voltage less than a system voltage. Each pulldown is coupled to a select line for gating an associated input signal.
摘要翻译：电子设备选择用于耦合到输出通道的多个输入信号中的一个。单个下拉为每个输入提供单独的路径，并且耦合到公共节点，其被预充电到小于系统电压的电压。每个下拉连接到用于选通相关输入信号的选择线。

6. 发明申请

US20070069785A1 REDUCED VOLTAGE PRE-CHARGE MULTIPLEXER 有权
标题翻译：降低电压预充电多路复用器
公开(公告)号：US20070069785A1
公开(公告)日：2007-03-29
申请号：US11559810
申请日：2006-11-14
申请人： John Fagan , Mark Bossard
发明人： John Fagan , Mark Bossard
IPC分类号： H03K3/017
CPC分类号： H03K17/693
摘要： An electronic device selects one of a plurality of input signals for coupling to an output channel. Individual pulldowns provide a separate pathway for each input, and are coupled to a common node which: is pre-charged to a voltage less than a system voltage. Each pulldown is coupled to a select line for gating an associated input signal.
摘要翻译：电子设备选择用于耦合到输出通道的多个输入信号中的一个。单个下拉为每个输入提供单独的路径，并且耦合到公共节点，其被预充电到小于系统电压的电压。每个下拉连接到用于选通相关输入信号的选择线。

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