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1. 发明授权

US06316124B1 Modified InAs hall elements 失效
标题翻译：修改的InAs大厅元素
公开(公告)号：US06316124B1
公开(公告)日：2001-11-13
申请号：US09482053
申请日：2000-01-13
申请人： John Bradley Boos , Walter Kruppa , Brian R. Bennett , Ming-Jey Yang
发明人： John Bradley Boos , Walter Kruppa , Brian R. Bennett , Ming-Jey Yang
IPC分类号： B32B1500
CPC分类号： B32B15/01 , Y10T428/12528 , Y10T428/12681 , Y10T428/12736 , Y10T428/2495
摘要： This invention pertains to more sensitive and more stable electronic devices which can sense electrical and magnetic fields. The devices are characterized by InAs channels confined on both sides thereof by a wide band gap AlSb material; protective layers above the AlSb material; modulation doping above the AlSb material; and layers of the InAs channel material containing 1 to 99 mol percent antimony, with the channel material being deposited in the form of alternating monolayers of InSb and InAs, of a ternary mixture of InAsSb.
摘要翻译：本发明涉及可感测电场和磁场的更敏感和更稳定的电子装置。这些器件的特征在于通过宽带隙AlSb材料限制在其两侧的InAs通道; AlSb材料上方的保护层; AlSb材料上的调制掺杂; 和含有1至99mol％锑的InAs通道材料的层，其中通道材料以InAsb的三元混合物的InSb和InAs的交替单层形式沉积。

2. 发明授权

US6133593A Channel design to reduce impact ionization in heterostructure field-effect transistors 失效
标题翻译：通道设计，以减少异质结场场效应晶体管的影响电离
公开(公告)号：US6133593A
公开(公告)日：2000-10-17
申请号：US358649
申请日：1999-07-23
申请人： J. Brad Boos , Ming-Jey Yang , Brian R. Bennett , Doewon Park , Walter Kruppa
发明人： J. Brad Boos , Ming-Jey Yang , Brian R. Bennett , Doewon Park , Walter Kruppa
IPC分类号： H01L29/10 , H01L29/20 , H01L29/778
CPC分类号： H01L29/1029 , H01L29/7783 , H01L29/2003
摘要： Heterostructure field-effect transistors (HFETs) and other electronic devs are fabricated from a series of semiconductor layers to have reduced impact ionization. On to a first barrier layer there is added a unique second subchannel layer having high quality transport properties for reducing impact ionization. A third barrier layer having a controlled thickness to permit electrons to tunnel through the layer to the subchannel layer is added as a spacer for the fourth main channel layer. A fifth multilayer composite barrier layer is added which has at least a barrier layer in contact with the fourth channel layer and on top a sixth cap layer is applied. The device is completed by adding two ohmic contacts in a spaced apart relationship on the sixth cap layer with a Schottky gate between them which is formed in contact with the fifth barrier layer. The second subchannel layer and the fourth main channel layers are made of materials which have the proper respective energy gaps and ground state energies such that during use the transfer of hot electrons from the main channel into the subchannel is made probable to reduce impact ionization in the main channel. In the preferred AlSb/InAs-based HFETs, the use of an Is InAs subchannel layer under the main InAs channel improves the performance of the HEMTs particularly for gate lengths in the deep-submicron regime. The devices exhibit higher transconductance, lower output conductance, reduced gate leakage current, higher operating drain voltage, and improved frequency performance.
摘要翻译：异质结构场效应晶体管（HFET）和其他电子器件由一系列半导体层制造以具有减小的冲击电离。在第一阻挡层上添加了具有高质量传输性质的独特的第二子通道层，用于减少冲击电离。作为第四主沟道层的间隔物，添加具有受控厚度以允许电子穿过层到子沟道层的第三阻挡层。添加了第五多层复合阻挡层，其至少具有与第四沟道层接触的阻挡层，并且在第六层上施加第六层。通过在第六盖层上以间隔开的关系添加两个欧姆接触，在它们之间形成与第五阻挡层接触形成的肖特基门来完成该器件。第二子沟道层和第四主沟道层由具有适当的相应能隙和基态能量的材料制成，使得在使用期间，热电子从主通道转移到子通道中是有可能减少在主渠道在优选的基于AlSb / InAs的HFET中，主InAs通道下的In InAs子通道层的使用改善了HEMT的性能，特别是对于深亚微米体系中的栅极长度。器件表现出更高的跨导，更低的输出电导，降低的栅极漏电流，更高的工作漏极电压和改进的频率性能。

3. 发明授权

US07157299B2 Nanofabrication of InAs/A1Sb heterostructures 失效
标题翻译： InAs / AlSb异质结构的纳米制备
公开(公告)号：US07157299B2
公开(公告)日：2007-01-02
申请号：US10725257
申请日：2003-12-02
申请人： Ming-Jey Yang , Chia-Hung Yang
发明人： Ming-Jey Yang , Chia-Hung Yang
IPC分类号： H01L21/00
CPC分类号： B82Y10/00 , H01L21/30612 , H01L29/205 , H01L29/66462
摘要： A heterostructure comprising: a buffer layer; a bottom barrier layer formed on the buffer layer; a quantum well layer formed on the bottom barrier layer; a top barrier layer formed on the quantum well layer; and a p-doped cap layer formed on the top barrier layer; wherein a portion of the cap layer is etched to form conducting electrons in the quantum well layer below the etched portion of the cap layer. A method of etching comprising the steps of: providing a heterostructure; providing an etchant solution comprising acetic acid, hydrogen peroxide, and water; and contacting the etchant solution to the heterostructure to etch the heterostructure.
摘要翻译：一种异质结构，包括：缓冲层; 形成在缓冲层上的底部阻挡层; 形成在所述底部阻挡层上的量子阱层; 形成在量子阱层上的顶部势垒层; 以及形成在顶部阻挡层上的p掺杂帽层; 其中所述盖层的一部分被蚀刻以在所述覆盖层的蚀刻部分下方的量子阱层中形成导电电子。一种蚀刻方法，包括以下步骤：提供异质结构; 提供包含乙酸，过氧化氢和水的蚀刻剂溶液; 并使蚀刻剂溶液与异质结构接触以蚀刻异质结构。

4. 发明授权

US06703639B1 Nanofabrication for InAs/AlSb heterostructures 失效
标题翻译： InAs / AlSb异质结构的纳米制备
公开(公告)号：US06703639B1
公开(公告)日：2004-03-09
申请号：US10320419
申请日：2002-12-17
申请人： Ming-Jey Yang , Chia-Hung Yang
发明人： Ming-Jey Yang , Chia-Hung Yang
IPC分类号： H01L2906
CPC分类号： B82Y10/00 , H01L21/30612 , H01L29/205 , H01L29/66462
摘要： A heterostructure comprising: a buffer layer; a bottom barrier layer formed on the buffer layer; a quantum well layer formed on the bottom barrier layer; a top barrier layer formed on the quantum well layer; and a p-doped cap layer formed on the top barrier layer; wherein a portion of the cap layer is etched to form conducting electrons in the quantum well layer below the etched portion of the cap layer. A method of etching comprising the steps of: providing a heterostructure; providing an etchant solution comprising acetic acid, hydrogen peroxide, and water; and contacting the etchant solution to the heterostructure to etch the heterostructure.
摘要翻译：一种异质结构，包括：缓冲层; 形成在缓冲层上的底部阻挡层; 形成在所述底部阻挡层上的量子阱层; 形成在量子阱层上的顶部势垒层; 以及形成在顶部阻挡层上的p掺杂帽层; 其中所述盖层的一部分被蚀刻以在所述覆盖层的蚀刻部分下方的量子阱层中形成导电电子。一种蚀刻方法，包括以下步骤：提供异质结构; 提供包含乙酸，过氧化氢和水的蚀刻剂溶液; 并使蚀刻剂溶液与异质结构接触以蚀刻异质结构。

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