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1. 发明授权

US6133593A Channel design to reduce impact ionization in heterostructure field-effect transistors 失效
标题翻译：通道设计，以减少异质结场场效应晶体管的影响电离
公开(公告)号：US6133593A
公开(公告)日：2000-10-17
申请号：US358649
申请日：1999-07-23
申请人： J. Brad Boos , Ming-Jey Yang , Brian R. Bennett , Doewon Park , Walter Kruppa
发明人： J. Brad Boos , Ming-Jey Yang , Brian R. Bennett , Doewon Park , Walter Kruppa
IPC分类号： H01L29/10 , H01L29/20 , H01L29/778
CPC分类号： H01L29/1029 , H01L29/7783 , H01L29/2003
摘要： Heterostructure field-effect transistors (HFETs) and other electronic devs are fabricated from a series of semiconductor layers to have reduced impact ionization. On to a first barrier layer there is added a unique second subchannel layer having high quality transport properties for reducing impact ionization. A third barrier layer having a controlled thickness to permit electrons to tunnel through the layer to the subchannel layer is added as a spacer for the fourth main channel layer. A fifth multilayer composite barrier layer is added which has at least a barrier layer in contact with the fourth channel layer and on top a sixth cap layer is applied. The device is completed by adding two ohmic contacts in a spaced apart relationship on the sixth cap layer with a Schottky gate between them which is formed in contact with the fifth barrier layer. The second subchannel layer and the fourth main channel layers are made of materials which have the proper respective energy gaps and ground state energies such that during use the transfer of hot electrons from the main channel into the subchannel is made probable to reduce impact ionization in the main channel. In the preferred AlSb/InAs-based HFETs, the use of an Is InAs subchannel layer under the main InAs channel improves the performance of the HEMTs particularly for gate lengths in the deep-submicron regime. The devices exhibit higher transconductance, lower output conductance, reduced gate leakage current, higher operating drain voltage, and improved frequency performance.
摘要翻译：异质结构场效应晶体管（HFET）和其他电子器件由一系列半导体层制造以具有减小的冲击电离。在第一阻挡层上添加了具有高质量传输性质的独特的第二子通道层，用于减少冲击电离。作为第四主沟道层的间隔物，添加具有受控厚度以允许电子穿过层到子沟道层的第三阻挡层。添加了第五多层复合阻挡层，其至少具有与第四沟道层接触的阻挡层，并且在第六层上施加第六层。通过在第六盖层上以间隔开的关系添加两个欧姆接触，在它们之间形成与第五阻挡层接触形成的肖特基门来完成该器件。第二子沟道层和第四主沟道层由具有适当的相应能隙和基态能量的材料制成，使得在使用期间，热电子从主通道转移到子通道中是有可能减少在主渠道在优选的基于AlSb / InAs的HFET中，主InAs通道下的In InAs子通道层的使用改善了HEMT的性能，特别是对于深亚微米体系中的栅极长度。器件表现出更高的跨导，更低的输出电导，降低的栅极漏电流，更高的工作漏极电压和改进的频率性能。

2. 发明授权

US06316124B1 Modified InAs hall elements 失效
标题翻译：修改的InAs大厅元素
公开(公告)号：US06316124B1
公开(公告)日：2001-11-13
申请号：US09482053
申请日：2000-01-13
申请人： John Bradley Boos , Walter Kruppa , Brian R. Bennett , Ming-Jey Yang
发明人： John Bradley Boos , Walter Kruppa , Brian R. Bennett , Ming-Jey Yang
IPC分类号： B32B1500
CPC分类号： B32B15/01 , Y10T428/12528 , Y10T428/12681 , Y10T428/12736 , Y10T428/2495
摘要： This invention pertains to more sensitive and more stable electronic devices which can sense electrical and magnetic fields. The devices are characterized by InAs channels confined on both sides thereof by a wide band gap AlSb material; protective layers above the AlSb material; modulation doping above the AlSb material; and layers of the InAs channel material containing 1 to 99 mol percent antimony, with the channel material being deposited in the form of alternating monolayers of InSb and InAs, of a ternary mixture of InAsSb.
摘要翻译：本发明涉及可感测电场和磁场的更敏感和更稳定的电子装置。这些器件的特征在于通过宽带隙AlSb材料限制在其两侧的InAs通道; AlSb材料上方的保护层; AlSb材料上的调制掺杂; 和含有1至99mol％锑的InAs通道材料的层，其中通道材料以InAsb的三元混合物的InSb和InAs的交替单层形式沉积。

3. 发明授权

US5798540A Electronic devices with InAlAsSb/AlSb barrier 失效
标题翻译：具有InAlAsSb / AlSb屏障的电子设备
公开(公告)号：US5798540A
公开(公告)日：1998-08-25
申请号：US848203
申请日：1997-04-29
申请人： John Bradley Boos , Walter Kruppa , Doewon Park , Brian R. Bennett
发明人： John Bradley Boos , Walter Kruppa , Doewon Park , Brian R. Bennett
IPC分类号： H01L21/308 , H01L21/338 , H01L29/201 , H01L29/205 , H01L29/778 , H01L29/812 , H01L29/00
CPC分类号： H01L29/205 , H01L29/201 , H01L29/7783
摘要： An electronic device characterized by a GaAs substrate and a base disposed n the substrate, the base comprising InAs channel layer, AlSb layer above the channel layer, In.sub.x Al.sub.1-x As.sub.y Sb.sub.1-y layer containing at least In, Al, and As disposed above the AlSb channel layer, InAs cap layer disposed above and in contact with the In.sub.x Al.sub.1-x As.sub.y Sb.sub.1-y layer disposed below the InAs channel layer and in contact with the substrate, p.sup.+ GaSb layer disposed within the AlSb layer, Schottky gate with a pad disposed on and in contact with the In.sub.x Al.sub.1-x As.sub.y Sb.sub.1-y layer, at least one ohmic contact disposed on the InAs cap layer, and a trench extending through the base to the substrate isolating the gate bonding pad from the device and providing a gate air bridge which prevents contact between the gate and the InAs layer. The gate air bridge fabrication is accomplished by a liquid etchant containing more than half, on volume basis, of concentrated lactic acid or acetic acid with remainder hydrogen peroxide and concentrated hydrofluoric acid. The etchant attacks InAs, In.sub.x Al.sub.1-x As.sub.y Sb.sub.1-y, AlSb, and GaSb but does not attack GaAs and Au-based alloys.
摘要翻译：一种电子器件，其特征在于具有GaAs衬底和设置在衬底上的基极，所述基底包括InAs沟道层，在沟道层上方的AlSb层，InxAl1-xAsySb1-y层至少包含位于AlSb沟道上方的In，Al和As 层InAs覆盖层设置在InAs1沟道层下方并与衬底接触的In x Al 1-x As y Sb 1-y层上方并与之接触，设置在AlSb层内的p + GaSb层，具有布置在并且接触的焊盘的肖特基栅极与InxAl1-xAsySb1-y层，设置在InAs覆盖层上的至少一个欧姆接触，以及延伸穿过基底到衬底的沟槽，将栅极焊盘与器件隔离，并提供栅极空气桥，门和InAs层。门空气桥的制造是通过液体蚀刻剂来实现的，该液体蚀刻剂含有一半以上的体积基础上的浓缩乳酸或乙酸，剩余的是过氧化氢和浓缩的氢氟酸。蚀刻剂攻击InAs，InxAl1-xAsySb1-y，AlSb和GaSb，但不会侵蚀GaAs和Au基合金。

4. 发明申请

US20140264278A1 Strained InGaAs Quantum Wells for Complementary Transistors 有权
标题翻译：应变InGaAs量子阱互补晶体管
公开(公告)号：US20140264278A1
公开(公告)日：2014-09-18
申请号：US14156592
申请日：2014-01-16
申请人： Brian R. Bennett , John Bradley Boos , Theresa F. Chick , James G. Champlain
发明人： Brian R. Bennett , John Bradley Boos , Theresa F. Chick , James G. Champlain
IPC分类号： H01L29/15 , H01L29/778
CPC分类号： H01L29/7783 , B82Y10/00 , H01L27/092 , H01L29/1079 , H01L29/151 , H01L29/20 , H01L29/365 , H01L29/66462 , H01L29/778 , H01L29/7787 , H01L31/035236
摘要： An InGaAs n-channel quantum well heterostructure for use in a complementary transistor having a Sb-based p-channel. The heterostructure includes a buffer layer having a lattice constant intermediate that of the n- and p-channel materials and which is configured to accommodate the strain produced by a lattice-constant mismatch between the n-channel and p-channel materials.
摘要翻译：用于具有Sb基p沟道的互补晶体管的InGaAs n沟道量子阱异质结构。异质结构包括具有中间至n沟道材料和p沟道材料的晶格常数的缓冲层，并被构造成适应由n沟道和p沟道材料之间的晶格常数失配产生的应变。

5. 发明授权

US5426740A Signaling protocol for concurrent bus access in a multiprocessor system 失效
标题翻译：用于多处理器系统中并发总线访问的信令协议
公开(公告)号：US5426740A
公开(公告)日：1995-06-20
申请号：US181900
申请日：1994-01-14
申请人： Brian R. Bennett
发明人： Brian R. Bennett
IPC分类号： G06F13/20 , G06F13/36 , G06F13/00
CPC分类号： G06F13/20 , G06F13/36
摘要： An improved signaling protocol for use in a multiprocessor system enables concurrent access to a common system bus during an I/O bus access. This reduces the system bus idling time without introducing complexities into the system bus architecture which might otherwise reduce the overall bus bandwidth increase. The improved bus architecture uses a system generated I/O bus busy (IOBUS.sub.-- BSY-) signal to indicate to all of the processors that the I/O bus is in use and that all other I/O requests must be held until the current transaction is completed. By preventing the other processors from executing an I/O request, the system bus does not have to be remain idle and can be used for memory-to-processor and for processor-to-processor transactions while the I/O bus is in use. By reducing the amount of time that the system bus is idle, the overall system bus performance is greatly increased.
摘要翻译：在多处理器系统中使用的改进的信令协议使得在I / O总线访问期间能够同时访问公共系统总线。这减少了系统总线空闲时间，而不会将复杂性引入到系统总线架构中，否则可能会降低总线带宽增加。改进的总线架构使用系统生成的I / O总线忙（IOBUS-BSY-）信号来向所有处理器指示I / O总线正在使用，并且所有其他I / O请求必须保持，直到当前交易完成。通过防止其他处理器执行I / O请求，系统总线不必保持空闲，并且可以在使用I / O总线时用于存储器到处理器和处理器到处理器事务。通过减少系统总线空闲的时间量，总体系统总线性能大大提高。

6. 发明授权

US4900591A Method for the deposition of high quality silicon dioxide at low temperature 失效
标题翻译：在低温下沉积高品质二氧化硅的方法
公开(公告)号：US4900591A
公开(公告)日：1990-02-13
申请号：US146072
申请日：1988-01-20
申请人： Brian R. Bennett , Joseph P. Lorenzo , Kenneth Vaccaro
发明人： Brian R. Bennett , Joseph P. Lorenzo , Kenneth Vaccaro
IPC分类号： C23C16/40
CPC分类号： C23C16/402
摘要： The invention comprises a pyrolytic process for the deposition of high quality silicon dioxide at temperatures of 100.degree.-330.degree. C. Deposition is achieved by reacting silane and oxygen in the 2-12 torr pressure range, yielding deposition rates of 140 .ANG./min at 300.degree. C. and 50 .ANG./min at 120.degree. C. Measurements of refractive index (1.45-1.46), field strength (3-10.times.10.sup.6 V/cm), and resistivity (10.sup.13 -10.sup.15 -cm) indicate that the oxides are near stoichiometric SiO.sub.2. This technology appears promising the Group IV and Group III-V device applications.
摘要翻译：本发明包括用于在100-330℃的温度下沉积高质量二氧化硅的热解方法。通过在2-12乇的压力范围内使硅烷和氧气反应来实现沉积，产生140安培/分钟的沉积速率 300℃，120℃时为50安培/分钟。折射率（1.45-1.46），场强（3-10×10 6 V / cm）和电阻率（1013-1015cm）的测量表明氧化物接近化学计量的SiO2。该技术显示出有希望的是第IV组和第III-V组设备应用。

7. 发明申请

US20160092353A1 ESTABLISHING COLD STORAGE POOLS FROM AGING MEMORY 审中-公开
标题翻译：从老化记忆建立冷藏库
公开(公告)号：US20160092353A1
公开(公告)日：2016-03-31
申请号：US14496773
申请日：2014-09-25
申请人： Robert C. Swanson , Robert W. Cone , Brian R. Bennett , Vladimir Matveyenko , Paul D. Herring , Jordan A. Horwich , Tuan M. Quach , Cuong D. Dinh , Paul M. Leung , Luis E. Valdez , Joseph Hamann , Russell A. Hamann , Michael P. Pham , Caleb C. Molitoris , Kervin T. Ngo , Cory Li , Ola Fadiran , Jason R. Ng , Richard I. Guerin , Jay H. Danver , Chris Kun K. Cheung , Satish R. Natla , Rodel I. Cruz-Herrera
发明人： Robert C. Swanson , Robert W. Cone , Brian R. Bennett , Vladimir Matveyenko , Paul D. Herring , Jordan A. Horwich , Tuan M. Quach , Cuong D. Dinh , Paul M. Leung , Luis E. Valdez , Joseph Hamann , Russell A. Hamann , Michael P. Pham , Caleb C. Molitoris , Kervin T. Ngo , Cory Li , Ola Fadiran , Jason R. Ng , Richard I. Guerin , Jay H. Danver , Chris Kun K. Cheung , Satish R. Natla , Rodel I. Cruz-Herrera
IPC分类号： G06F12/06 , G06F12/12 , G06F11/30
CPC分类号： G11C29/765 , G06F11/3037 , G06F11/3055 , G06F12/0238 , G06F2201/88 , G06F2212/7202 , G06F2212/7203 , G06F2212/7206
摘要： Systems and methods may provide for detecting a pending write operation directed to a target memory region and determining whether the target memory region satisfies a degradation condition in response to the pending write operation. Additionally, the target memory region may be automatically reconfigured as a cold storage region if the target memory region satisfies the degradation condition. In one example, determining whether the target memory region satisfies the degradation condition includes updating the number of write operations directed to the target memory region based on the pending write operation and comparing the number of write operations to an offset value, wherein the degradation condition is satisfied if the number of write operations exceeds the offset value.
摘要翻译：系统和方法可以提供用于检测针对目标存储器区域的待决写入操作，并且确定目标存储器区域是否满足等待写入操作的退化条件。此外，如果目标存储器区域满足劣化条件，则可以将目标存储器区域自动重新配置为冷存储区域。在一个示例中，确定目标存储器区域是否满足劣化条件包括基于挂起的写入操作来更新针对目标存储器区域的写入操作的数量，并将写入操作的数量与偏移值进行比较，其中劣化条件是如果写操作的数量超过偏移值，则满足。

8. 发明申请

US20140339501A1 Low-Resistivity p-Type GaSb Quantum Wells for Low-Power Electronic Devices 审中-公开
标题翻译：低功耗电子器件的低电阻率p型GaSb量子阱
公开(公告)号：US20140339501A1
公开(公告)日：2014-11-20
申请号：US13895388
申请日：2013-05-16
申请人： Brian R. Bennett , Theresa F. Chick , Mario G. Ancona , John Bradley Boos
发明人： Brian R. Bennett , Theresa F. Chick , Mario G. Ancona , John Bradley Boos
IPC分类号： H01L29/12
CPC分类号： H01L29/122 , H01L29/201 , H01L29/7783
摘要： A semiconductor device including a heterostructure having at least one low-resistivity p-type GaSb quantum well is provided. The heterostructure includes a layer of InwAl1−wAs on a semi-insulating (100) InP substrate, where the InwAl1−wAs is lattice matched to InP, followed by an AlAsxSb1−x buffer layer on the InwAl1−wAs layer, an AlAsxSb1−x spacer layer on the buffer layer, a GaSb quantum well layer on the spacer layer, an AlAsxSb1−x barrier layer on the quantum well layer, an InyAl1−ySb layer on the barrier layer, and an InAs cap. The semiconductor device is suitable for use in low-power electronic devices such as field-effect transistors.
摘要翻译：提供包括具有至少一个低电阻率p型GaSb量子阱的异质结构的半导体器件。异质结构包括在半绝缘（100）InP衬底上的InwAl1-wAs层，其中InwAl1-wAs与InP晶格匹配，随后是InwAl1-wAs层上的AlAsxSb1-x缓冲层，AlAsxSb1-x 缓冲层上的间隔层，间隔层上的GaSb量子阱层，量子阱层上的AlAs x Sb 1-x势垒层，势垒层上的In y Al 1-y Sb层和InAs帽。半导体器件适用于诸如场效应晶体管的低功率电子器件。

9. 发明授权

US5900014A External means of overriding and controlling cacheability attribute of selected CPU accesses to monitor instruction and data streams 失效
标题翻译：覆盖和控制所选CPU访问的高速缓存属性的外部手段来监视指令和数据流
公开(公告)号：US5900014A
公开(公告)日：1999-05-04
申请号：US769321
申请日：1996-12-19
申请人： Brian R. Bennett
发明人： Brian R. Bennett
IPC分类号： G06F11/25 , G06F11/34 , G06F11/36 , G06F12/08 , G06F11/30
CPC分类号： G06F11/3656 , G06F11/348 , G06F12/0888 , G06F11/25 , G06F2201/885
摘要： A system for facilitating debugging of software running within an information processing unit includes an external trigger state machine which selectively overrides the cacheability attribute of a cache line. An in-circuit emulator (ICE), which is used for debugging purposes, monitors addresses read by and written to a CPU. If an address which is of interest for debugging purposes is detected by the ICE, then the ICE issues a trigger signal. The trigger signal causes the external trigger state machine to designate the cache line associated with the detected address as a non-cacheable operation (i.e., to override the cacheability attribute) . Thus, the data associated with the cache line is written out to the main memory module where the data can be observed by an ICE, rather than to an internal cache memory location where the data would be invisible to an ICE. In a preferred embodiment of the invention, the external trigger state machine is configured to operate in a pipelining environment wherein multiple requests may be outstanding at one time.
摘要翻译：用于促进在信息处理单元内运行的软件的调试的系统包括选择性地覆盖高速缓存行的高速缓存性属性的外部触发状态机。用于调试目的的在线仿真器（ICE）监控由CPU读取和写入的地址。如果由ICE检测到用于调试目的感兴趣的地址，则ICE发出触发信号。触发信号使得外部触发状态机将与检测到的地址相关联的高速缓存行指定为非高速缓存操作（即，覆盖高速缓存属性）。因此，与高速缓存线相关联的数据被写出到主存储器模块，其中可以由ICE观察数据，而不是内部高速缓冲存储器位置，其中数据将不可见于ICE。在本发明的优选实施例中，外部触发状态机被配置为在流水线环境中操作，其中多个请求可能一次可能是未完成的。

10. 发明授权

US5404464A Bus control system and method that selectively generate an early address strobe 失效
标题翻译：选择性地产生早期地址选通的总线控制系统和方法
公开(公告)号：US5404464A
公开(公告)日：1995-04-04
申请号：US16726
申请日：1993-02-11
申请人： Brian R. Bennett
发明人： Brian R. Bennett
IPC分类号： G06F12/08 , G06F13/16 , G06F12/00 , G06F13/14
CPC分类号： G06F12/0833 , G06F13/1663
摘要： An improved bus architecture system for use in a multi-processor computer system has a shared address bus and a shared data bus, and has at least two separate memory modules. The system reduces the bus latency time by allowing sequential address requests to different memory modules to begin before previous cycles are terminated. Preferably, the physical memory is mapped onto several separate memory modules which will increase the probability that concurrent address requests from different processors on the common bus are for different memory modules. The processor address determines which memory module contains the data for a new request. If the memory module addressed by the new request differs from the memory module addressed by the current request, the bus controller may issue an early address request for the new data. While the early address request for the new request is being processed, the current bus cycle for the data located in the first memory module is completed on the shared data bus. Thus, the bus latency in a tightly-coupled multi-processor system can be significantly reduced using the improved bus architecture.
摘要翻译：用于多处理器计算机系统的改进的总线架构系统具有共享地址总线和共享数据总线，并且具有至少两个单独的存储器模块。该系统通过在先前的周期结束之前允许对不同存储器模块的顺序地址请求开始来减少总线等待时间。优选地，物理存储器映射到几个单独的存储器模块上，这将增加公共总线上来自不同处理器的并发地址请求对于不同存储器模块的概率。处理器地址确定哪个内存模块包含新请求的数据。如果由新请求寻址的存储器模块与当前请求所寻址的存储器模块不同，则总线控制器可以对新数据发出早期地址请求。当正在处理对新请求的早期地址请求时，位于第一存储器模块中的数据的当前总线周期在共享数据总线上完成。因此，使用改进的总线架构可以显着减少紧耦合多处理器系统中的总线延迟。

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