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1. 发明授权

US07208753B2 Enhancement mode single electron transistor 失效
标题翻译：增强型单电子晶体管
公开(公告)号：US07208753B2
公开(公告)日：2007-04-24
申请号：US11307830
申请日：2006-02-24
申请人： Ming Yang , Chia-Hung Yang , Yuli Lyanda-Geller
发明人： Ming Yang , Chia-Hung Yang , Yuli Lyanda-Geller
IPC分类号： H01L29/06
CPC分类号： H01L29/7613 , B82Y10/00 , H01L29/127
摘要： A transistor having a bottom dielectric layer, a first layer, a second layer, a top dielectric layer, and a gate electrode. The first layer and the second layer form a composite quantum well between the bottom dielectric layer and the top dielectric layer. The first layer, the second layer, and the top dielectric layer are configured to form a hole wire in the first layer. The gate electrode is over a portion of the hole wire and divides the top dielectric layer into a source contact and a drain contact.
摘要翻译：具有底部电介质层，第一层，第二层，顶部电介质层和栅电极的晶体管。第一层和第二层在底部电介质层和顶部电介质层之间形成复合量子阱。第一层，第二层和顶部电介质层被构造成在第一层中形成孔线。栅电极在孔线的一部分上方，并将顶部电介质层分成源极触点和漏极触点。

2. 发明申请

US20070063182A1 ENHANCEMENT MODE SINGLE ELECTRON TRANSISTOR 失效
标题翻译：增强型单电子晶体管
公开(公告)号：US20070063182A1
公开(公告)日：2007-03-22
申请号：US11307830
申请日：2006-02-24
申请人： Ming Yang , Chia-Hung Yang , Yuli Lyanda-Geller
发明人： Ming Yang , Chia-Hung Yang , Yuli Lyanda-Geller
IPC分类号： H01L31/00
CPC分类号： H01L29/7613 , B82Y10/00 , H01L29/127
摘要： A transistor having a bottom dielectric layer, a first layer, a second layer, a top dielectric layer, and a gate electrode. The first layer and the second layer form a composite quantum well between the bottom dielectric layer and the top dielectric layer. The first layer, the second layer, and the top dielectric layer are configured to form a hole wire in the first layer. The gate electrode is over a portion of the hole wire and divides the top dielectric layer into a source contact and a drain contact.
摘要翻译：具有底部电介质层，第一层，第二层，顶部电介质层和栅电极的晶体管。第一层和第二层在底部电介质层和顶部电介质层之间形成复合量子阱。第一层，第二层和顶部电介质层被构造成在第一层中形成孔线。栅电极在孔线的一部分上方，并将顶部电介质层分成源极触点和漏极触点。

3. 发明授权

US07157299B2 Nanofabrication of InAs/A1Sb heterostructures 失效
标题翻译： InAs / AlSb异质结构的纳米制备
公开(公告)号：US07157299B2
公开(公告)日：2007-01-02
申请号：US10725257
申请日：2003-12-02
申请人： Ming-Jey Yang , Chia-Hung Yang
发明人： Ming-Jey Yang , Chia-Hung Yang
IPC分类号： H01L21/00
CPC分类号： B82Y10/00 , H01L21/30612 , H01L29/205 , H01L29/66462
摘要： A heterostructure comprising: a buffer layer; a bottom barrier layer formed on the buffer layer; a quantum well layer formed on the bottom barrier layer; a top barrier layer formed on the quantum well layer; and a p-doped cap layer formed on the top barrier layer; wherein a portion of the cap layer is etched to form conducting electrons in the quantum well layer below the etched portion of the cap layer. A method of etching comprising the steps of: providing a heterostructure; providing an etchant solution comprising acetic acid, hydrogen peroxide, and water; and contacting the etchant solution to the heterostructure to etch the heterostructure.
摘要翻译：一种异质结构，包括：缓冲层; 形成在缓冲层上的底部阻挡层; 形成在所述底部阻挡层上的量子阱层; 形成在量子阱层上的顶部势垒层; 以及形成在顶部阻挡层上的p掺杂帽层; 其中所述盖层的一部分被蚀刻以在所述覆盖层的蚀刻部分下方的量子阱层中形成导电电子。一种蚀刻方法，包括以下步骤：提供异质结构; 提供包含乙酸，过氧化氢和水的蚀刻剂溶液; 并使蚀刻剂溶液与异质结构接触以蚀刻异质结构。

4. 发明授权

US06703639B1 Nanofabrication for InAs/AlSb heterostructures 失效
标题翻译： InAs / AlSb异质结构的纳米制备
公开(公告)号：US06703639B1
公开(公告)日：2004-03-09
申请号：US10320419
申请日：2002-12-17
申请人： Ming-Jey Yang , Chia-Hung Yang
发明人： Ming-Jey Yang , Chia-Hung Yang
IPC分类号： H01L2906
CPC分类号： B82Y10/00 , H01L21/30612 , H01L29/205 , H01L29/66462
摘要： A heterostructure comprising: a buffer layer; a bottom barrier layer formed on the buffer layer; a quantum well layer formed on the bottom barrier layer; a top barrier layer formed on the quantum well layer; and a p-doped cap layer formed on the top barrier layer; wherein a portion of the cap layer is etched to form conducting electrons in the quantum well layer below the etched portion of the cap layer. A method of etching comprising the steps of: providing a heterostructure; providing an etchant solution comprising acetic acid, hydrogen peroxide, and water; and contacting the etchant solution to the heterostructure to etch the heterostructure.
摘要翻译：一种异质结构，包括：缓冲层; 形成在缓冲层上的底部阻挡层; 形成在所述底部阻挡层上的量子阱层; 形成在量子阱层上的顶部势垒层; 以及形成在顶部阻挡层上的p掺杂帽层; 其中所述盖层的一部分被蚀刻以在所述覆盖层的蚀刻部分下方的量子阱层中形成导电电子。一种蚀刻方法，包括以下步骤：提供异质结构; 提供包含乙酸，过氧化氢和水的蚀刻剂溶液; 并使蚀刻剂溶液与异质结构接触以蚀刻异质结构。

5. 发明授权

US6080996A Unipolar three-terminal resonant-tunneling transistor 失效
标题翻译：单极三端谐振隧穿晶体管
公开(公告)号：US6080996A
公开(公告)日：2000-06-27
申请号：US174723
申请日：1993-12-29
申请人： Chia-Hung Yang
发明人： Chia-Hung Yang
IPC分类号： H01L29/76 , H01L29/772 , H01L29/205 , H01L29/88
CPC分类号： H01L29/772 , B82Y10/00 , H01L29/7606
摘要： The present invention discloses both an n+ and a p+ unipolar, three-terminal, resonant-tunneling transistor that can be operated as a hot-electron transistor or a field effect transistor at temperatures at least as low as 77 degree Kelvin. The doped first terminal (collector or gate) is made of 3D metal or semiconductor material. An undoped insulating barrier is deposited on the first terminal. The doped electrically-contacted second terminal (emitter or source), made of a 2D semiconductor material, is deposited on the insulating barrier. An undoped double-barrier resonant-tunneling structure is deposited on the second terminal. A doped third terminal, made of 3D metal or semiconductor material, is deposited on a portion of the double-barrier resonant-tunneling structure. A doped tunneling-contact, made of 3D metal or semiconductor material, is deposited on the double-barrier resonant-tunneling structure so that the tunneling contact is isolated from the third terminal. At a temperature of at least as low as 77 degrees Kelvin, dc current gain between the third terminal and the tunneling-contact is observed when a bias voltage or current is applied to the first terminal. With a bias applied to the first terminal, majority carriers from the tunneling-contact tunnel through the double-barrier resonant-tunneling structure to the second terminal. The majority carriers propagate along the second terminal and tunnel through the double-barrier resonant-tunneling structure to the third terminal.
摘要翻译：本发明公开了可以在至少低至77开氏度的温度下作为热电子晶体管或场效应晶体管工作的n +和p +单极三端谐振隧穿晶体管。掺杂的第一端子（集电极或栅极）由3D金属或半导体材料制成。未掺杂的绝缘屏障沉积在第一端子上。由二维半导体材料制成的掺杂电接触的第二端子（发射极或源极）沉积在绝缘屏障上。未掺杂的双屏障共振隧穿结构沉积在第二端子上。由三维金属或半导体材料制成的掺杂的第三端子沉积在双屏障共振隧穿结构的一部分上。由三维金属或半导体材料制成的掺杂隧道接触层沉积在双屏障共振隧穿结构上，使隧道接触与第三端隔离。在至少低至77开氏度的温度下，当偏置电压或电流施加到第一端子时，观察到第三端子和隧道接触之间的直流电流增益。通过施加到第一端子的偏置，来自隧道接触隧道的多数载流子通过双屏障共振隧穿结构到第二端子。多数载流子沿着第二端子传播并通过双屏障共振隧道结构隧穿到第三端子。

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