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    • 6. 发明授权
    • Dynamic random access memory
    • 动态随机存取存储器
    • US06204140B1
    • 2001-03-20
    • US09275337
    • 1999-03-24
    • Ulrike GrueningJochen BeintnerScott HalleJack A. MandelmanCarl J. RadensJuergen WittmannJeffrey J. Welser
    • Ulrike GrueningJochen BeintnerScott HalleJack A. MandelmanCarl J. RadensJuergen WittmannJeffrey J. Welser
    • H01L218242
    • H01L27/10864H01L27/10861
    • A method includes forming a trench capacitor in a semiconductor body. A recess is formed in the upper portion of the capacitor with such recess having sidewalls in the semiconductor body. A first material is deposited over the sidewalls and over a bottom of the recess. A second material is deposited over the first material. A mask is provided over the second material. The mask has: a masking region to cover one portion of said recess bottom; and a window over a portion of said recess sidewall and another portion of said recess bottom to expose underlying portions of the second material. Portions of the exposed underlying portions of the second material are selectively removing while leaving substantially un-etched exposed underlying portions of the first material. The exposed portions of the first material and underlying portions of the semiconductor body are selectively removed. An isolation region is formed in the removed portions of the semiconductor body. The mask is provided over the second material with a masking region covering one portion of said recess sidewall and one portion of said recess bottom and with a window disposed over an opposite portion of said recess sidewall and an opposite portion of said recess bottom to expose underlying portions of the second material. Etching is provided into the exposed underlying portions of the semiconductor body to form a shallow trench in the semiconductor body. An insulating material is formed in the shallow trench to form a shallow trench isolation region. With such method, greater mask misalignment tolerances are permissible.
    • 一种方法包括在半导体本体中形成沟槽电容器。 在电容器的上部形成凹部,该凹槽在半导体本体中具有侧壁。 第一材料沉积在凹槽的侧壁和底部上方。 第二种材料沉积在第一种材料上。 在第二材料上提供面罩。 掩模具有:掩蔽区域,以覆盖所述凹部底部的一部分; 以及位于所述凹陷侧壁的一部分上的窗口和所述凹部底部的另一部分以暴露第二材料的下面部分。 第二材料的暴露的下部部分的部分是选择性地去除,同时留下基本未蚀刻的暴露的第一材料的下部。 选择性地去除半导体主体的第一材料和下部的暴露部分。 隔离区形成在半导体本体的去除部分中。 所述掩模设置在所述第二材料上方,具有覆盖所述凹陷侧壁的一部分和所述凹部底部的一部分的掩蔽区域,以及设置在所述凹部侧壁的相对部分上方的窗口和所述凹部底部的相对部分, 第二材料的部分。 在半导体本体的暴露的下部设置蚀刻,以在半导体本体中形成浅沟槽。 在浅沟槽中形成绝缘材料以形成浅沟槽隔离区域。 通过这种方法,允许更大的掩模不对准公差。
    • 7. 发明授权
    • Programmable SCR for LDMOS ESD protection
    • 用于LDMOS ESD保护的可编程SCR
    • US08878284B2
    • 2014-11-04
    • US13460523
    • 2012-04-30
    • Sameer PendharkarSuhail MurtazaJuergen Wittmann
    • Sameer PendharkarSuhail MurtazaJuergen Wittmann
    • H01L29/66
    • H01L29/0692H01L29/87
    • A protection circuit for a DMOS transistor comprises an anode circuit having a first heavily doped region of a first conductivity type (314) formed within and electrically connected to a first lightly doped region of the second conductivity type (310, 312). A cathode circuit having a plurality of third heavily doped regions of the first conductivity type (700) within a second heavily doped region of the second conductivity type (304). A first lead (202) is connected to each third heavily doped region (704) and connected to the second heavily doped region by at least three spaced apart connections (702) between every two third heavily doped regions. An SCR (400, 402) is connected between the anode circuit and the cathode circuit. The DMOS transistor has a drain (310, 312, 316) connected to the anode circuit and a source (304) connected to the cathode circuit.
    • 用于DMOS晶体管的保护电路包括阳极电路,其具有在第二导电类型(310,312)的第一轻掺杂区域内形成并电连接的第一导电类型的第一重掺杂区域(314)。 在第二导电类型(304)的第二重掺杂区域内具有第一导电类型(700)的多个第三重掺杂区域的阴极电路。 第一引线(202)连接到每个第三重掺杂区域(704),并且通过每两个第三重掺杂区域之间的至少三个间隔开的连接(702)连接到第二重掺杂区域。 在阳极电路和阴极电路之间连接有SCR(400,402)。 DMOS晶体管具有连接到阳极电路的漏极(310,312,316)和连接到阴极电路的源极(304)。