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1. 发明授权

US07076613B2 Cache line pre-load and pre-own based on cache coherence speculation 失效
标题翻译：缓存线预加载和基于缓存一致性推测的预先拥有
公开(公告)号：US07076613B2
公开(公告)日：2006-07-11
申请号：US10761995
申请日：2004-01-21
申请人： Jih-Kwon Peir , Steve Y. Zhang , Scott H. Robinson , Konrad Lai , Wen-Hann Wang
发明人： Jih-Kwon Peir , Steve Y. Zhang , Scott H. Robinson , Konrad Lai , Wen-Hann Wang
IPC分类号： G06F12/00
CPC分类号： G06F12/0831
摘要： The invention provides a cache management system comprising in various embodiments pre-load and pre-own functionality to enhance cache efficiency in shared memory distributed cache multiprocessor computer systems. Some embodiments of the invention comprise an invalidation history table to record the line addresses of cache lines invalidated through dirty or clean invalidation, and which is used such that invalidated cache lines recorded in an invalidation history table are reloaded into cache by monitoring the bus for cache line addresses of cache lines recorded in the invalidation history table. In some further embodiments, a write-back bit associated with each L2 cache entry records when either a hit to the same line in another processor is detected or when the same line is invalidated in another processor's cache, and the system broadcasts write-backs from the selected local cache only when the line being written back has a write-back bit that has been set.
摘要翻译：本发明提供一种缓存管理系统，其包括在各种实施例中预先加载和预先拥有的功能，以增强共享存储器分布式高速缓存多处理器计算机系统中的高速缓存效率。本发明的一些实施例包括无效历史表，用于记录通过脏或无效无效而无效的高速缓存行的行地址，并且其被使用，使得记录在无效历史表中的无效高速缓存行通过监视高速缓存的总线被重新加载到高速缓存中记录在无效历史表中的高速缓存行的行地址。在一些另外的实施例中，与每个L2高速缓存条目相关联的回写位在检测到另一个处理器中的同一行的命中时或者当另一个处理器的高速缓存中的同一行无效时记录，并且系统广播回写从所选择的本地缓存只有当正在写回的行具有已设置的回写位时。

2. 发明授权

US06725341B1 Cache line pre-load and pre-own based on cache coherence speculation 有权
标题翻译：缓存线预加载和基于缓存一致性推测的预先拥有
公开(公告)号：US06725341B1
公开(公告)日：2004-04-20
申请号：US09605239
申请日：2000-06-28
申请人： Jih-Kwon Peir , Steve Y. Zhang , Scott H. Robinson , Konrad Lai , Wen-Hann Wang
发明人： Jih-Kwon Peir , Steve Y. Zhang , Scott H. Robinson , Konrad Lai , Wen-Hann Wang
IPC分类号： G06F1200
CPC分类号： G06F12/0831
摘要： The invention provides a cache management system comprising in various embodiments pre-load and pre-own functionality to enhance cache efficiency in shared memory distributed cache multiprocessor computer systems. Some embodiments of the invention comprise an invalidation history table to record the line addresses of cache lines invalidated through dirty or clean invalidation, and which is used such that invalidated cache lines recorded in an invalidation history table are reloaded into cache by monitoring the bus for cache line addresses of cache lines recorded in the invalidation history table. In some further embodiments, a write-back bit associated with each L2 cache entry records when either a hit to the same line in another processor is detected or when the same line is invalidated in another processor's cache, and the system broadcasts write-backs from the selected local cache only when the line being written back has a write-back bit that has been set.
摘要翻译：本发明提供一种缓存管理系统，其包括在各种实施例中预先加载和预先拥有的功能，以增强共享存储器分布式高速缓存多处理器计算机系统中的高速缓存效率。本发明的一些实施例包括无效历史表，用于记录通过脏或无效无效而无效的高速缓存行的行地址，并且其被使用，使得记录在无效历史表中的无效高速缓存行通过监视高速缓存的总线被重新加载到高速缓存中记录在无效历史表中的高速缓存行的行地址。在一些另外的实施例中，与每个L2高速缓存条目相关联的回写位在检测到另一个处理器中的同一行的命中时或者当另一个处理器的高速缓存中的同一行无效时记录，并且系统广播回写从所选择的本地缓存只有当正在写回的行具有已设置的回写位时。

3. 发明授权

US06711662B2 Multiprocessor cache coherence management 有权
标题翻译：多处理器缓存一致性管理
公开(公告)号：US06711662B2
公开(公告)日：2004-03-23
申请号：US09823251
申请日：2001-03-29
申请人： Jih-Kwon Peir , Konrad Lai
发明人： Jih-Kwon Peir , Konrad Lai
IPC分类号： G06F1200
CPC分类号： G06F12/0817 , G06F2212/507
摘要： A shared-memory system includes processing modules communicating with each other through a network. Each of the processing modules includes a processor, a cache, and a memory unit that is locally accessible by the processor and remotely accessible via the network by all other processors. A home directory records states and locations of data blocks in the memory unit. A prediction facility that contains reference history information of the data blocks predicts a next requester of a number of the data blocks that have been referenced recently. The next requester is informed by the prediction facility of the current owner of the data block. As a result, the next requester can issue a request to the current owner directly without an additional hop through the home directory.
摘要翻译：共享存储器系统包括通过网络彼此通信的处理模块。每个处理模块包括处理器，高速缓存和存储器单元，其可由处理器本地访问并且可被所有其他处理器经由网络远程访问。主目录记录存储器单元中的数据块的状态和位置。包含数据块的参考历史信息的预测设备预测最近已被引用的数个数据块的下一个请求者。下一个请求者由数据块的当前所有者的预测设备通知。因此，下一个请求者可以直接向当前所有者发出请求，而无需通过主目录进行额外的跳转。

4. 发明申请

US20150006717A1 TRACKING MODE OF A PROCESSING DEVICE IN INSTRUCTION TRACING SYSTEMS 审中-公开
标题翻译：指令跟踪系统中处理设备的跟踪模式
公开(公告)号：US20150006717A1
公开(公告)日：2015-01-01
申请号：US14126313
申请日：2013-06-27
申请人： Thilo Schmitt , Peter Lachner , Beeman Strong , Ofer Levy , Thomas Toll , Matthew Merten , Tong Li , Ravi Rajwar , Konrad Lai
发明人： Thilo Schmitt , Peter Lachner , Beeman Strong , Ofer Levy , Thomas Toll , Matthew Merten , Tong Li , Ravi Rajwar , Konrad Lai
IPC分类号： H04L12/26
CPC分类号： G06F9/30189 , G06F11/3636
摘要： In accordance with embodiments disclosed herein, there is provided systems and methods for tracking the mode of processing devices in an instruction tracing system. The method may include receiving an indication of a change in a current execution mode of the processing device. The method may also include determining that the current execution mode of the received indication is different than a value of an execution mode of a first execution mode (EM) packet previously-generated by the IT module. The method may also include generating, based on the determining that the current execution mode is different, a second EM packet that provides a value of the current execution mode of the processing device to indicate the change in the execution mode for an instruction in a trace generated by the IT module. The method may further include generating transactional memory (TMX) packets having n bit mode pattern in the packet log. The n is at least two and the n bit mode indicates transaction status of the TMX operation.
摘要翻译：根据本文公开的实施例，提供了用于跟踪指令跟踪系统中的处理设备的模式的系统和方法。该方法可以包括接收处理设备的当前执行模式中的改变的指示。该方法还可以包括确定接收到的指示的当前执行模式不同于IT模块先前生成的第一执行模式（EM）分组的执行模式的值。该方法还可以包括基于确定当前执行模式不同而生成第二EM分组，其提供处理设备的当前执行模式的值以指示用于跟踪中的指令的执行模式的改变由IT模块生成。该方法还可以包括在分组日志中生成具有n位模式模式的事务存储器（TMX）分组。 n至少为2，n位模式表示TMX操作的事务状态。

5. 发明授权

US08180977B2 Transactional memory in out-of-order processors 有权
标题翻译：无序处理器中的事务性内存
公开(公告)号：US08180977B2
公开(公告)日：2012-05-15
申请号：US11394687
申请日：2006-03-30
申请人： Ravi Rajwar , Haitham H. Akkary , Konrad Lai
发明人： Ravi Rajwar , Haitham H. Akkary , Konrad Lai
IPC分类号： G06F12/00
CPC分类号： G06F9/526 , G06F9/3004 , G06F9/30087 , G06F9/3834 , G06F9/3859 , G06F9/3863 , G06F12/0802 , G06F13/1626
摘要： Methods and apparatus to provide transactional memory execution in out-of-order processors are described. In one embodiment, a stored value corresponds to the number of transactional memory access requests that are uncommitted. The stored value may be used to provide nested recovery in case of an error, fault, etc. in accordance with a described embodiment.
摘要翻译：描述了在乱序处理器中提供事务性存储器执行的方法和装置。在一个实施例中，存储的值对应于未提交的事务存储器访问请求的数量。根据所描述的实施例，存储的值可以用于在错误，故障等的情况下提供嵌套恢复。

6. 发明授权

US06507895B1 Method and apparatus for access demarcation 失效
标题翻译：访问分界的方法和装置
公开(公告)号：US06507895B1
公开(公告)日：2003-01-14
申请号：US09539665
申请日：2000-03-30
申请人： Hong Wang , Ralph Kling , Jeff Baxter , Konrad Lai
发明人： Hong Wang , Ralph Kling , Jeff Baxter , Konrad Lai
IPC分类号： G06F1202
CPC分类号： G06F12/0862 , G06F2212/6022 , G06F2212/6028
摘要： An embodiment of the present invention provides for an apparatus for memory access demarcation. Data is accessed from a first cache, which comprises a first set of addresses and corresponding data at each of the addresses in the first set. A plurality of addresses is generated for a second set of addresses. The second set of addresses follows the first set of addresses. The second set of addresses are calculated based on a fixed stride, where the second set of addresses are associated with data from a first stream. A plurality of addresses is generated for a third set of addresses. The third set of addresses follows the first set of addresses. Each address in the third set of addresses is generated by tracing a link associated with another address in the third set of addresses. The third set of addresses is associated with data from a second stream.
摘要翻译：本发明的实施例提供了一种用于存储器访问分界的装置。数据从第一高速缓存访问，第一高速缓存包括第一组地址中的第一组地址和相应的数据。为第二组地址生成多个地址。第二组地址遵循第一组地址。基于固定步幅计算第二组地址，其中第二组地址与来自第一流的数据相关联。为第三组地址生成多个地址。第三组地址遵循第一组地址。通过跟踪与第三组地址中的另一地址相关联的链接来生成第三组地址中的每个地址。第三组地址与来自第二个流的数据相关联。

7. 发明授权

US5796977A Highly pipelined bus architecture 失效
标题翻译：高度流水线总线架构
公开(公告)号：US5796977A
公开(公告)日：1998-08-18
申请号：US688238
申请日：1996-07-29
申请人： Nitin V. Sarangdhar , Gurbir Singh , Konrad Lai , Stephen S. Pawlowski , Peter D. MacWilliams , Michael W. Rhodehamel
发明人： Nitin V. Sarangdhar , Gurbir Singh , Konrad Lai , Stephen S. Pawlowski , Peter D. MacWilliams , Michael W. Rhodehamel
IPC分类号： G06F12/08 , G06F13/18 , G06F12/00 , G06F13/00
CPC分类号： G06F13/18 , G06F12/0831
摘要： A computer system incorporating a pipelined bus that maintains data coherency, supports long latency transactions and provides processor order is described. The computer system includes bus agents having in-order-queues that track multiple outstanding transactions across a system bus and that perform snoops in response to transaction requests providing snoop results and modified data within one transaction. Additionally, the system supports long latency transactions by providing deferred identifiers during transaction requests that are used to restart deferred transactions.
摘要翻译：描述了包含维护数据一致性的流水线总线的计算机系统，支持长延迟事务并提供处理器顺序。计算机系统包括总线代理，其具有在系统总线上跟踪多个未完成事务的按顺序队列，并且响应于在一个事务中提供窥探结果和修改的数据的事务请求来执行窥探。此外，系统通过在用于重新启动延迟事务的事务请求期间提供延迟标识符来支持长延迟事务。

8. 发明授权

US4823260A Mixed-precision floating point operations from a single instruction opcode 失效
标题翻译：来自单指令操作码的混合精度浮点运算
公开(公告)号：US4823260A
公开(公告)日：1989-04-18
申请号：US119547
申请日：1987-11-12
申请人： Michael T. Imel , Konrad Lai , Glenford J. Myers , Randy Steck , James Valerio
发明人： Michael T. Imel , Konrad Lai , Glenford J. Myers , Randy Steck , James Valerio
IPC分类号： G06F7/57 , G06F7/48
CPC分类号： G06F7/483 , G06F2207/3816 , G06F7/49957
摘要： Apparatus for performing mixed precision calculations in the floating point unit of a microprocessor from a single instruction opcode. 80-bit floating-point registers (44) may be specified as the source or destination address of a floating-point instruction. When the address range of the destination indicates (26) that a floating point register is addressed, the result of that operation is not rounded to the precision specified by the instruction, but is rounded (58) to extended 80-bit precision and loaded into the floating point register (FP-44). When the address range of the source indicates (26) that an FP register is addressed, the data is loaded from the FP register in extended precision, regardless of the precision specified by the instruction. In this way, real and long-real operations can be made to use extended precision numbers without explicitly specifying that in the opcode.
摘要翻译：用于从单个指令操作码在微处理器的浮点单元中执行混合精度计算的装置。可以将80位浮点寄存器（44）指定为浮点指令的源地址或目标地址。当目的地的地址范围指示（26）指定浮点寄存器时，该操作的结果不会舍入到指令指定的精度，而是舍入（58）到扩展的80位精度并加载到浮点寄存器（FP-44）。当源地址范围指示（26）FP寄存器被寻址时，无论指令指定的精度如何，数据都以扩展精度从FP寄存器加载。以这种方式，可以使用实际和长期实际的操作来使用扩展精度数字，而无需在操作码中明确指定。

9. 发明授权

US08180967B2 Transactional memory virtualization 有权
标题翻译：事务性内存虚拟化
公开(公告)号：US08180967B2
公开(公告)日：2012-05-15
申请号：US11394622
申请日：2006-03-30
申请人： Ravi Rajwar , Haitham H. Akkary , Konrad Lai
发明人： Ravi Rajwar , Haitham H. Akkary , Konrad Lai
IPC分类号： G06F12/00
CPC分类号： G06F12/0842 , G06F9/30087 , G06F9/3834 , G06F9/3859 , G06F9/467
摘要： Methods and apparatus to provide transactional memory execution in a virtualized mode are described. In one embodiment, data corresponding to a transactional memory access request may be stored in a portion of a memory after an operation corresponding to the transactional memory access request causes an overflow and a stored value may be updated for an occurrence of the overflow.
摘要翻译：描述了以虚拟化模式提供事务性存储器执行的方法和装置。在一个实施例中，对应于事务存储器访问请求的数据可以在与事务存储器访问请求相对应的操作引起溢出并且可以针对溢出的发生更新存储的值之后存储在存储器的一部分中。

10. 发明申请

US20060155967A1 Processing essential and non-essential code separately 失效
公开(公告)号：US20060155967A1
公开(公告)日：2006-07-13
申请号：US11331874
申请日：2006-01-13
申请人： Hong Wang , Ralph Kling , Yong-Fong Lee , David Berson , Michael Kozuch , Konrad Lai
发明人： Hong Wang , Ralph Kling , Yong-Fong Lee , David Berson , Michael Kozuch , Konrad Lai
IPC分类号： G06F9/30
CPC分类号： G06F9/30181 , G06F8/41 , G06F9/3879
摘要： A conjugate processor includes an instruction set architecture (ISA) visible portion having a main pipeline, and an h-flow portion having an h-flow pipeline. The binary executed on the conjugate processor includes an essential portion that is executed on the main pipeline and a non-essential portion that is executed on the h-flow pipeline. The non-essential portion includes hint calculus that is used to provide hints to the main pipeline. The conjugate processor also includes a conjugate mapping table that maps triggers to h-flow targets. Triggers can be instruction attributes, data attributes, state attributes or event attributes. When a trigger is satisfied, the h-flow code specified by the target is executed in the h-flow pipeline.

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