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1. 发明申请

US20070106833A1 Scalable distributed memory and I/O multiprocessor systems and associated methods 有权
标题翻译：可扩展分布式存储器和I / O多处理器系统及相关方法
公开(公告)号：US20070106833A1
公开(公告)日：2007-05-10
申请号：US11422542
申请日：2006-06-06
申请人： Linda Rankin , Paul Pierce , Gregory Dermer , Wen-Hann Wang , Kai Cheng , Richard Hofsheier , Nitin Borkar
发明人： Linda Rankin , Paul Pierce , Gregory Dermer , Wen-Hann Wang , Kai Cheng , Richard Hofsheier , Nitin Borkar
IPC分类号： G06F13/00
CPC分类号： G06F13/4022 , G06F13/4027
摘要： A multiprocessor system comprises at least one processing module, at least one I/O module, and an interconnect network to connect the at least one processing module with the at least one input/output module. In an example embodiment, the interconnect network comprises at least two bridges to send and receive transactions between the input/output modules and the processing module The interconnect network further comprises at least two crossbar switches to route the transactions over a high bandwidth switch connection. Using embodiments of the interconnect network allows high bandwidth communication between processing modules and I/O modules Standard processing module hardware can be used with the interconnect network without modifying the BIOS or the operating system. Furthermore, using the interconnect network of embodiments of the present invention is non-invasive to the processor motherboard. The processor memory bus, clock, and reset logic all remain intact.
摘要翻译：多处理器系统包括至少一个处理模块，至少一个I / O模块和互连网络，以将所述至少一个处理模块与所述至少一个输入/输出模块连接。在示例实施例中，互连网络包括用于在输入/输出模块和处理模块之间发送和接收事务的至少两个桥接器。互连网络还包括至少两个交叉开关以通过高带宽交换机连接路由交易。使用互连网络的实施例允许处理模块和I / O模块之间的高带宽通信标准处理模块硬件可以与互连网络一起使用，而无需修改BIOS或操作系统。此外，使用本发明的实施例的互连网络对于处理器主板是非侵入性的。处理器内存总线，时钟和复位逻辑都保持不变。

2. 发明授权

US07076613B2 Cache line pre-load and pre-own based on cache coherence speculation 失效
标题翻译：缓存线预加载和基于缓存一致性推测的预先拥有
公开(公告)号：US07076613B2
公开(公告)日：2006-07-11
申请号：US10761995
申请日：2004-01-21
申请人： Jih-Kwon Peir , Steve Y. Zhang , Scott H. Robinson , Konrad Lai , Wen-Hann Wang
发明人： Jih-Kwon Peir , Steve Y. Zhang , Scott H. Robinson , Konrad Lai , Wen-Hann Wang
IPC分类号： G06F12/00
CPC分类号： G06F12/0831
摘要： The invention provides a cache management system comprising in various embodiments pre-load and pre-own functionality to enhance cache efficiency in shared memory distributed cache multiprocessor computer systems. Some embodiments of the invention comprise an invalidation history table to record the line addresses of cache lines invalidated through dirty or clean invalidation, and which is used such that invalidated cache lines recorded in an invalidation history table are reloaded into cache by monitoring the bus for cache line addresses of cache lines recorded in the invalidation history table. In some further embodiments, a write-back bit associated with each L2 cache entry records when either a hit to the same line in another processor is detected or when the same line is invalidated in another processor's cache, and the system broadcasts write-backs from the selected local cache only when the line being written back has a write-back bit that has been set.
摘要翻译：本发明提供一种缓存管理系统，其包括在各种实施例中预先加载和预先拥有的功能，以增强共享存储器分布式高速缓存多处理器计算机系统中的高速缓存效率。本发明的一些实施例包括无效历史表，用于记录通过脏或无效无效而无效的高速缓存行的行地址，并且其被使用，使得记录在无效历史表中的无效高速缓存行通过监视高速缓存的总线被重新加载到高速缓存中记录在无效历史表中的高速缓存行的行地址。在一些另外的实施例中，与每个L2高速缓存条目相关联的回写位在检测到另一个处理器中的同一行的命中时或者当另一个处理器的高速缓存中的同一行无效时记录，并且系统广播回写从所选择的本地缓存只有当正在写回的行具有已设置的回写位时。

3. 发明授权

US5548742A Method and apparatus for combining a direct-mapped cache and a multiple-way cache in a cache memory 失效
标题翻译：用于将直接映射高速缓存与多路高速缓存组合在高速缓冲存储器中的方法和装置
公开(公告)号：US5548742A
公开(公告)日：1996-08-20
申请号：US288923
申请日：1994-08-11
申请人： Wen-Hann Wang , Konrad K. Lai
发明人： Wen-Hann Wang , Konrad K. Lai
IPC分类号： G06F12/08 , G06F13/14
CPC分类号： G06F12/0864
摘要： A two-way set-associative cache memory includes both a set array and a data array in one embodiment. The data array comprises multiple elements, each of which can contain a cache line. The set array comprises multiple sets, with each set in the set array corresponding to an element in the data array. Each set in the set array contains information which indicates whether an address received by the cache memory matches the cache line contained in its corresponding element of the data array. The information stored in each set includes a tag and a state. The tag contains a reference to one of the cache lines in the data array. If the tag of a particular set matches the address received by the cache memory, then the cache line associated with that particular set is the requested cache line. The state of a particular set indicates the number of cache lines mapped into that particular set.
摘要翻译：双向组合关联高速缓冲存储器在一个实施例中包括集阵列和数据阵列。数据阵列包括多个元素，每个元素可以包含高速缓存行。集合阵列包括多个集合，集合阵列中的每个集合对应于数据数组中的一个元素。集合阵列中的每个集合包含指示高速缓冲存储器接收的地址与数据阵列的相应元素中包含的高速缓存行匹配的信息。存储在每个集合中的信息包括标签和状态。该标记包含对数据数组中的一条缓存行的引用。如果特定集合的标签与高速缓冲存储器接收的地址匹配，则与该特定集合相关联的高速缓存行是所请求的高速缓存行。特定集合的状态指示映射到该特定集合的高速缓存行数。

4. 发明授权

US08255605B2 Scalable distributed memory and I/O multiprocessor system 有权
标题翻译：可扩展分布式内存和I / O多处理器系统
公开(公告)号：US08255605B2
公开(公告)日：2012-08-28
申请号：US13076041
申请日：2011-03-30
申请人： Linda J. Rankin , Paul R. Pierce , Gregory E. Dermer , Wen-Hann Wang , Kai Cheng , Richard H Hofsheier , Nitin Y. Borkar
发明人： Linda J. Rankin , Paul R. Pierce , Gregory E. Dermer , Wen-Hann Wang , Kai Cheng , Richard H Hofsheier , Nitin Y. Borkar
IPC分类号： G06F13/00
CPC分类号： G06F13/4022 , G06F13/4027
摘要： A multiprocessor system comprises at least one processing module, at least one I/O module, and an interconnect network to connect the at least one processing module with the at least one input/output module. In an example embodiment, the interconnect network comprises at least two bridges to send and receive transactions between the input/output modules and the processing module. The interconnect network further comprises at least two crossbar switches to route the transactions over a high bandwidth switch connection. Using embodiments of the interconnect network allows high bandwidth communication between processing modules and I/O modules. Standard processing module hardware can be used with the interconnect network without modifying the BICS or the operating system. Furthermore, using the interconnect network of embodiments of the present invention is non-invasive to the processor motherboard. The processor memory bus, clock, and reset logic all remain intact.
摘要翻译：多处理器系统包括至少一个处理模块，至少一个I / O模块和互连网络，以将所述至少一个处理模块与所述至少一个输入/输出模块连接。在示例实施例中，互连网络包括用于在输入/输出模块和处理模块之间发送和接收事务的至少两个桥。互连网络还包括至少两个交叉开关以通过高带宽交换机连接路由交易。使用互连网络的实施例允许处理模块和I / O模块之间的高带宽通信。标准处理模块硬件可以与互连网络一起使用，而无需修改BICS或操作系统。此外，使用本发明的实施例的互连网络对于处理器主板是非侵入性的。处理器内存总线，时钟和复位逻辑都保持不变。

5. 发明申请

US20090319717A1 SCALABLE DISTRIBUTED MEMORY AND I/O MULTIPROCESSOR SYSTEMS AND ASSOCIATED METHODS 有权
标题翻译：可分配的分布式存储器和I / O多处理器系统及相关方法
公开(公告)号：US20090319717A1
公开(公告)日：2009-12-24
申请号：US12549491
申请日：2009-08-28
申请人： Linda J. Rankin , Paul R. Pierce , Gregory E. Dermer , Wen-Hann Wang , Kai Cheng , Richard H. Hofsheier , Nitin Y. Borkar
发明人： Linda J. Rankin , Paul R. Pierce , Gregory E. Dermer , Wen-Hann Wang , Kai Cheng , Richard H. Hofsheier , Nitin Y. Borkar
IPC分类号： G06F13/00
CPC分类号： G06F13/4022 , G06F13/4027
摘要： A multiprocessor system comprises at least one processing module, at least one I/O module, and an interconnect network to connect the at least one processing module with the at least one input/output module. In an example embodiment, the interconnect network comprises at least two bridges to send and receive transactions between the input/output modules and the processing module. The interconnect network further comprises at least two crossbar switches to route the transactions over a high bandwidth switch connection. Using embodiments of the interconnect network allows high bandwidth communication between processing modules and I/O modules. Standard processing module hardware can be used with the interconnect network without modifying the BIOS or the operating system. Furthermore, using the interconnect network of embodiments of the present invention is non-invasive to the processor motherboard. The processor memory bus, clock, and reset logic all remain intact.
摘要翻译：多处理器系统包括至少一个处理模块，至少一个I / O模块和互连网络，以将所述至少一个处理模块与所述至少一个输入/输出模块连接。在示例实施例中，互连网络包括用于在输入/输出模块和处理模块之间发送和接收事务的至少两个桥。互连网络还包括至少两个交叉开关以通过高带宽交换机连接路由交易。使用互连网络的实施例允许处理模块和I / O模块之间的高带宽通信。标准处理模块硬件可以与互连网络一起使用，而无需修改BIOS或操作系统。此外，使用本发明的实施例的互连网络对于处理器主板是非侵入性的。处理器内存总线，时钟和复位逻辑都保持不变。

6. 发明授权

US07603508B2 Scalable distributed memory and I/O multiprocessor systems and associated methods 有权
标题翻译：可扩展分布式存储器和I / O多处理器系统及相关方法
公开(公告)号：US07603508B2
公开(公告)日：2009-10-13
申请号：US12013595
申请日：2008-01-14
申请人： Linda J. Rankin , Paul R. Pierce , Gregory E. Dermer , Wen-Hann Wang , Kai Cheng , Richard H. Hofsheier , Nitin Y. Borkar
发明人： Linda J. Rankin , Paul R. Pierce , Gregory E. Dermer , Wen-Hann Wang , Kai Cheng , Richard H. Hofsheier , Nitin Y. Borkar
IPC分类号： G06F13/00
CPC分类号： G06F13/4022 , G06F13/4027
摘要： A multiprocessor system comprises at least one processing module, at least one I/O module, and an interconnect network to connect the at least one processing module with the at least one input/output module. In an example embodiment, the interconnect network comprises at least two bridges to send and receive transactions between the input/output modules and the processing module. The interconnect network further comprises at least two crossbar switches to route the transactions over a high bandwidth switch connection. Using embodiments of the interconnect network allows high bandwidth communication between processing modules and I/O modules. Standard processing module hardware can be used with the interconnect network without modifying the BIOS or the operating system. Furthermore, using the interconnect network of embodiments of the present invention is non-invasive to the processor motherboard. The processor memory bus, clock, and reset logic all remain intact.
摘要翻译：多处理器系统包括至少一个处理模块，至少一个I / O模块和互连网络，以将所述至少一个处理模块与所述至少一个输入/输出模块连接。在示例实施例中，互连网络包括用于在输入/输出模块和处理模块之间发送和接收事务的至少两个桥。互连网络还包括至少两个交叉开关以通过高带宽交换机连接路由交易。使用互连网络的实施例允许处理模块和I / O模块之间的高带宽通信。标准处理模块硬件可以与互连网络一起使用，而无需修改BIOS或操作系统。此外，使用本发明的实施例的互连网络对于处理器主板是非侵入性的。处理器内存总线，时钟和复位逻辑都保持不变。

7. 发明授权

US07343442B2 Scalable distributed memory and I/O multiprocessor systems and associated methods 有权
标题翻译：可扩展分布式存储器和I / O多处理器系统及相关方法
公开(公告)号：US07343442B2
公开(公告)日：2008-03-11
申请号：US11422542
申请日：2006-06-06
申请人： Linda J. Rankin , Paul R. Pierce , Gregory E. Dermer , Wen-Hann Wang , Kai Cheng , Richard H. Hofsheier , Nitin Y. Borkar
发明人： Linda J. Rankin , Paul R. Pierce , Gregory E. Dermer , Wen-Hann Wang , Kai Cheng , Richard H. Hofsheier , Nitin Y. Borkar
IPC分类号： G06F13/00
CPC分类号： G06F13/4022 , G06F13/4027
摘要： A multiprocessor system comprises at least one processing module, at least one I/O module, and an interconnect network to connect the at least one processing module with the at least one input/output module. In an example embodiment, the interconnect network comprises at least two bridges to send and receive transactions between the input/output modules and the processing module The interconnect network further comprises at least two crossbar switches to route the transactions over a high bandwidth switch connection. Using embodiments of the interconnect network allows high bandwidth communication between processing modules and I/O modules Standard processing module hardware can be used with the interconnect network without modifying the BIOS or the operating system. Furthermore, using the interconnect network of embodiments of the present invention is non-invasive to the processor motherboard. The processor memory bus, clock, and reset logic all remain intact.
摘要翻译：多处理器系统包括至少一个处理模块，至少一个I / O模块和互连网络，以将所述至少一个处理模块与所述至少一个输入/输出模块连接。在示例实施例中，互连网络包括用于在输入/输出模块和处理模块之间发送和接收事务的至少两个桥。互连网络还包括至少两个交叉开关以通过高带宽交换机连接路由交易。使用互连网络的实施例允许处理模块和I / O模块之间的高带宽通信。标准处理模块硬件可以与互连网络一起使用，而无需修改BIOS或操作系统。此外，使用本发明的实施例的互连网络对于处理器主板是非侵入性的。处理器内存总线，时钟和复位逻辑都保持不变。

8. 发明授权

US5551005A Apparatus and method of handling race conditions in mesi-based multiprocessor system with private caches 失效
标题翻译：在具有私有高速缓存的基于Mesi的多处理器系统中处理竞争条件的装置和方法
公开(公告)号：US5551005A
公开(公告)日：1996-08-27
申请号：US201854
申请日：1994-02-25
申请人： Nitin V. Sarangdhar , Wen-Hann Wang , Matthew Fisch
发明人： Nitin V. Sarangdhar , Wen-Hann Wang , Matthew Fisch
IPC分类号： G06F12/08
CPC分类号： G06F12/0808 , G06F12/0831
摘要： In a computer system having a plurality of processors with internal caches, a method for handling race conditions arising when multiple processors simultaneously write to a particular cache line. Initially, a determination is made as to whether the cache line is in an exclusive, modified, invalid, or shared state. If the cache line is in either the exclusive or modified state, the cache line is written to and then set to the modified state. If the cache line is in the invalid state, a Bus-Read-Invalidate operation is performed. However, if the cache line is in the shared state and multiple processors initiate Bus-Write-Invalidate operations, the invalidation request belonging to the first processor is allowed to complete. Thereupon, the cache line is sent to the exclusive state, data is updated, and the cache line is set to the modified state. The second processor receives a second cache line, updates this second cache line, and sets the second cache line to the modified state.
摘要翻译：在具有多个具有内部高速缓存的处理器的计算机系统中，一种用于处理当多个处理器同时写入特定高速缓存行时产生的竞争条件的方法。首先，确定高速缓存行是否处于排他，修改，无效或共享状态。如果缓存行处于独占状态或修改状态，则将高速缓存行写入并设置为修改状态。如果缓存行处于无效状态，则执行总线读取无效操作。然而，如果高速缓存行处于共享状态，并且多个处理器启动总线写入无效操作，则允许属于第一处理器的无效请求完成。于是缓存行被发送到独占状态，数据被更新，高速缓存行被设置为修改状态。第二处理器接收第二高速缓存行，更新第二高速缓存行，并将第二高速缓存行设置为修改状态。

9. 发明申请

US20120317328A1 SCALABLE DISTRIBUTED MEMORY AND I/O MULTIPROCESSOR SYSTEM 有权
标题翻译：可分配的分布式存储器和I / O多处理器系统
公开(公告)号：US20120317328A1
公开(公告)日：2012-12-13
申请号：US13590936
申请日：2012-08-21
申请人： Linda J. Rankin , Paul R. Pierce , Gregory E. Dermer , Wen-Hann Wang , Kai Cheng , Richard H. Hofsheier , Nitin Y. Borkar
发明人： Linda J. Rankin , Paul R. Pierce , Gregory E. Dermer , Wen-Hann Wang , Kai Cheng , Richard H. Hofsheier , Nitin Y. Borkar
IPC分类号： G06F13/28 , G06F13/00
CPC分类号： G06F13/4022 , G06F13/4027
摘要： A multiprocessor system comprises at least one processing module, at least one I/O module, and an interconnect network to connect the at least one processing module with the at least one input/output module. In an example embodiment, the interconnect network comprises at least two bridges to send and receive transactions between the input/output modules and the processing module. The interconnect network further comprises at least two crossbar switches to route the transactions over a high bandwidth switch connection. Using embodiments of the interconnect network allows high bandwidth communication between processing modules and I/O modules. Standard processing module hardware can be used with the interconnect network without modifying the BIOS or the operating system. Furthermore, using the interconnect network of embodiments of the present invention is non-invasive to the processor motherboard. The processor memory bus, clock, and reset logic all remain intact.
摘要翻译：多处理器系统包括至少一个处理模块，至少一个I / O模块和互连网络，以将所述至少一个处理模块与所述至少一个输入/输出模块连接。在示例实施例中，互连网络包括用于在输入/输出模块和处理模块之间发送和接收事务的至少两个桥。互连网络还包括至少两个交叉开关以通过高带宽交换机连接路由交易。使用互连网络的实施例允许处理模块和I / O模块之间的高带宽通信。标准处理模块硬件可以与互连网络一起使用，而无需修改BIOS或操作系统。此外，使用本发明的实施例的互连网络对于处理器主板是非侵入性的。处理器内存总线，时钟和复位逻辑都保持不变。

10. 发明授权

US07930464B2 Scalable memory and I/O multiprocessor systems 有权
标题翻译：可扩展内存和I / O多处理器系统
公开(公告)号：US07930464B2
公开(公告)日：2011-04-19
申请号：US12549491
申请日：2009-08-28
申请人： Linda J. Rankin , Paul R. Pierce , Gregory E. Dermer , Wen-Hann Wang , Kai Cheng , Richard H. Hofsheier , Nitin Y. Borkar
发明人： Linda J. Rankin , Paul R. Pierce , Gregory E. Dermer , Wen-Hann Wang , Kai Cheng , Richard H. Hofsheier , Nitin Y. Borkar
IPC分类号： G06F13/00
CPC分类号： G06F13/4022 , G06F13/4027
摘要： A multiprocessor system comprises at least one processing module, at least one I/O module, and an interconnect network to connect the at least one processing module with the at least one input/output module. In an example embodiment, the interconnect network comprises at least two bridges to send and receive transactions between the input/output modules and the processing module. The interconnect network further comprises at least two crossbar switches to route the transactions over a high bandwidth switch connection. Using embodiments of the interconnect network allows high bandwidth communication between processing modules and I/O modules. Standard processing module hardware can be used with the interconnect network without modifying the BIOS or the operating system. Furthermore, using the interconnect network of embodiments of the present invention is non-invasive to the processor motherboard. The processor memory bus, clock, and reset logic all remain intact.
摘要翻译：多处理器系统包括至少一个处理模块，至少一个I / O模块和互连网络，以将所述至少一个处理模块与所述至少一个输入/输出模块连接。在示例实施例中，互连网络包括用于在输入/输出模块和处理模块之间发送和接收事务的至少两个桥。互连网络还包括至少两个交叉开关以通过高带宽交换机连接路由交易。使用互连网络的实施例允许处理模块和I / O模块之间的高带宽通信。标准处理模块硬件可以与互连网络一起使用，而无需修改BIOS或操作系统。此外，使用本发明的实施例的互连网络对于处理器主板是非侵入性的。处理器内存总线，时钟和复位逻辑都保持不变。

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