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    • 1. 发明授权
    • Method and apparatus for access demarcation
    • 访问分界的方法和装置
    • US06507895B1
    • 2003-01-14
    • US09539665
    • 2000-03-30
    • Hong WangRalph KlingJeff BaxterKonrad Lai
    • Hong WangRalph KlingJeff BaxterKonrad Lai
    • G06F1202
    • G06F12/0862G06F2212/6022G06F2212/6028
    • An embodiment of the present invention provides for an apparatus for memory access demarcation. Data is accessed from a first cache, which comprises a first set of addresses and corresponding data at each of the addresses in the first set. A plurality of addresses is generated for a second set of addresses. The second set of addresses follows the first set of addresses. The second set of addresses are calculated based on a fixed stride, where the second set of addresses are associated with data from a first stream. A plurality of addresses is generated for a third set of addresses. The third set of addresses follows the first set of addresses. Each address in the third set of addresses is generated by tracing a link associated with another address in the third set of addresses. The third set of addresses is associated with data from a second stream.
    • 本发明的实施例提供了一种用于存储器访问分界的装置。 数据从第一高速缓存访​​问,第一高速缓存包括第一组地址中的第一组地址和相应的数据。 为第二组地址生成多个地址。 第二组地址遵循第一组地址。 基于固定步幅计算第二组地址,其中第二组地址与来自第一流的数据相关联。 为第三组地址生成多个地址。 第三组地址遵循第一组地址。 通过跟踪与第三组地址中的另一地址相关联的链接来生成第三组地址中的每个地址。 第三组地址与来自第二个流的数据相关联。
    • 5. 发明授权
    • Dependency matrix
    • 依赖矩阵
    • US6065105A
    • 2000-05-16
    • US780255
    • 1997-01-08
    • Nazar ZaidiGary HammondKen ShoemakerJeff Baxter
    • Nazar ZaidiGary HammondKen ShoemakerJeff Baxter
    • G06F9/38G06F15/00
    • G06F9/3836G06F9/3838G06F9/384
    • In a microprocessor, an instruction scheduler 30 includes a dependency matrix 36 and a waiting buffer 34. A dependency determination unit 32 receives instructions to be executed, forwards the instructions to the waiting buffer 34, determines if any dependency exists between the instructions, and forwards the dependency information to the dependency matrix 36 in the form of a dependency vector 40. The dependency matrix 36 periodically determines whether any of the instructions contained in the waiting buffer 34 are ready to be executed, that is, no dependencies exist for that instruction. As each instruction is dispatched for execution from the waiting buffer 34, the dependency vector 40 for all dependent instructions is cleared for subsequent execution. In this manner, an out-of-order processing scheme is implemented that efficiently accounts for data dependency between processed instructions.
    • 在微处理器中,指令调度器30包括依赖矩阵36和等待缓冲器34.依赖性确定单元32接收要执行的指令,将指令转发到等待缓冲器34,确定指令之间是否存在任何依赖关系,并转发 依赖关系矩阵36以依赖性向量40的形式被依赖性矩阵36.依赖矩阵36周期性地确定包含在等待缓冲器34中的任何指令是否准备好被执行,也就是说,对于该指令不存在依赖性。 当每个指令从等待缓冲器34调度执行时,所有相关指令的依赖向量40被清除以供后续执行。 以这种方式,实现了有效地考虑处理的指令之间的数据依赖性的无序处理方案。